ELEC 7770 Advanced VLSI Design Spring 2014 VLSI Yield and Moore’s Law

Spring 2014, Jan 15Spring 2014, Jan 15 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 11

ELEC 7770ELEC 7770Advanced VLSI DesignAdvanced VLSI Design

Spring 2014Spring 2014VLSI Yield and Moore’s LawVLSI Yield and Moore’s Law

Vishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher Professor

ECE Department, Auburn UniversityECE Department, Auburn University

Auburn, AL 36849Auburn, AL 36849

[email protected]://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14/course.html


VLSI Chip YieldVLSI Chip YieldVLSI Chip YieldVLSI Chip Yield

A manufacturing defect is a finite chip area with A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by electrically malfunctioning circuitry caused by errors in the fabrication process.errors in the fabrication process.

A chip with no manufacturing defect is called a A chip with no manufacturing defect is called a good chip.good chip.

Fraction (or percentage) of good chips produced Fraction (or percentage) of good chips produced in a manufacturing process is called the yield. in a manufacturing process is called the yield. Yield is denoted by symbol Yield is denoted by symbol YY..


Importance of YieldImportance of Yield

Cost of a chip =Cost of a chip =

Cost of fabricating and testing a wafer

Yield × Number of chip sites on the wafer


Clustered VLSI DefectsClustered VLSI DefectsClustered VLSI DefectsClustered VLSI Defects

WaferDefects

Faulty chips

Good chips

Unclustered defectsWafer yield = 12/22 = 0.55

Clustered defects (VLSI)Wafer yield = 17/22 = 0.77


Yield ParametersYield ParametersYield ParametersYield Parameters Defect density (Defect density (d d ) = Average number of defects per unit ) = Average number of defects per unit

chip areachip area Chip area (Chip area (A A )) Clustering parameter (Clustering parameter ()) Negative binomial distribution of defects, Negative binomial distribution of defects,

p p ((x x ) = Prob(number of defects on a chip = ) = Prob(number of defects on a chip = x x ))

Γ (α +x ) (Ad / α) x

= .

x ! Γ (α) (1+Ad / α) α+x

where Γ is the gamma functionα = 0, p (x ) is a delta function (max. clustering)α = , p (x ) is Poisson distribution (no clustering)


Yield EquationYield EquationYield EquationYield Equation

Y = Prob( zero defect on a chip ) = p (0)

Y = ( 1 + Ad / α ) – α

Example: Ad = 1.0, α = 0.5, Y = 0.58

Unclustered defects: α = , Y = e – Ad

Example: Ad = 1.0, α = , Y = 0.37

too pessimistic !


Effect of Defect ClusteringEffect of Defect Clustering

0 0.5 1.0 1.5 2.0

1.00

0.75

0.50

0.25

0.00

Yie

ld

Ad = 0.5

Clustering Parameter, α

e-0.5 = 0.607


Ranges of Yield ParametersRanges of Yield Parameters

Yield of1 cm2 chip

Defect density, d in defects per cm2

0.1 1.5

5.0

0.5 0.913

0.906

0.50

0.27

Clu

ster

ing

para

met

er,

α

Mat

ure

proc

ess

Initi

al p

roce

ss


ReferencesReferences Clustered yield modelClustered yield model

M. L. Bushnell and V. D. Agrawal, M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI CircuitsDigital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000, , Springer, 2000, Chapter 3.Chapter 3.

C. H. Stapper, “On Yield, Fault Distributions, and Clustering of C. H. Stapper, “On Yield, Fault Distributions, and Clustering of Particles,” Particles,” IBM Jour. of Res. and DevIBM Jour. of Res. and Dev., vol. 30, no. 3, pp. 326-338, ., vol. 30, no. 3, pp. 326-338, May 1986.May 1986.

The unclustered defect model was first described in paper:The unclustered defect model was first described in paper: B. T. Murphy, “Cost-Size Optima of Monolithic Integrated Circuits,” B. T. Murphy, “Cost-Size Optima of Monolithic Integrated Circuits,”

Proc. IEEEProc. IEEE, vol. 52, no. 12, pp. 1537-1545, December 1964., vol. 52, no. 12, pp. 1537-1545, December 1964.

A general reference on clustered distributions:A general reference on clustered distributions: A. Rogers, A. Rogers, Statistical Analysis of Spatial DispersionsStatistical Analysis of Spatial Dispersions, London, United , London, United

Kingdom: Pion Limited, 1974.Kingdom: Pion Limited, 1974.


Gordon E. MooreGordon E. Moore


19651965 ““Cramming More Components onto Integrated Cramming More Components onto Integrated

Circuits,” Circuits,” ElectronicsElectronics, vol. 38, no. 8, April 19, 1965., vol. 38, no. 8, April 19, 1965. The complexity for minimum component costs has

increased at a rate of roughly a factor of two per year (see graph on next page). Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years. That means by 1975, the number of components per integrated circuit for minimum cost will be 65,000.

I believe that such a large circuit can be built on a single wafer.


Moore’s 1965 GraphMoore’s 1965 Graph

1975

Higher integrationreduces cost

Lower yield oflarger chipsIncreases cost


19751975

““Progress in Digital Integrated Electronics,” Progress in Digital Integrated Electronics,” IEDM Tech. DigestIEDM Tech. Digest, 1975, pp. 11-13., 1975, pp. 11-13.

. . . the rate of increase of complexity can be expected to change slope in the next few years as shown in Figure 5. The new slope might approximate a doubling every two years, rather than every year, by the end of the decade.


Figure 5 of Moore’s 1975 PaperFigure 5 of Moore’s 1975 Paper

16M

1M

64K

4K

256

16

160 65 70 75 80 85

Year

Com

pone

nts

per

chip


19951995 ““Lithography and the Future of Moore’s Law,” Lithography and the Future of Moore’s Law,”

Proc. SPIEProc. SPIE, vol. 2437, May 1995., vol. 2437, May 1995. By making things smaller, everything gets better

simultaneously. There is little need for trade-offs. The speed of our products goes up, the power consumption goes down, system reliability, as we put more of the system on a chip, improves by leaps and bounds, but especially the cost of doing thing electronically drops as a result of the technology.

(SPIE – Society of Photonic Instrumentation Engineers)


Also in the 1995 PaperAlso in the 1995 Paper

. . . I have no idea what will happen beyond 0.18 microns.

In fact, I still have trouble believing we are going to be comfortable at 0.18 microns using conventional optical systems. Beyond this level, I do not see any way that conventional optics carries us any further. Of course, some of us said this about the one micron level. This time, however, I think there are fundamental materials issues that will force a different direction. The people at this conference are going to have to come up with something new to keep us on the long term trend.


Moore’s LawMoore’s Law

Sou

rce:

Wik

iped

ia


20122012

Problems with technology advances:Problems with technology advances: High power consumptionHigh power consumption

Power densityPower density LeakageLeakage

Process variation – larger as a fraction of feature sizeProcess variation – larger as a fraction of feature size Increased noise sensitivityIncreased noise sensitivity

Problems with design:Problems with design: Verification of correctness – logic and timingVerification of correctness – logic and timing Ensuring reliable operationEnsuring reliable operation TestingTesting

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ELEC 7770 Advanced VLSI Design Spring 2014 VLSI Yield and Moore’s Law