VLSI Design, Characterization, and Use of Custom Standard Cells

8/9/2019 VLSI Design, Characterization, and Use of Custom Standard Cells

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INVERTER (NOT)This was implemented by connecting n-mos and p-mos transistors inseries with each otherThe size of both the nmos and pmos (W/L) were chosen at 220n/180n,representing minimum sizes they could be scaled to, without violatingDRC rules.Standard cell dimensions of the inverter was 7.75um by 2.830um(height-width) representing a total area of 21.93um2Input pins were connected to the poly and out put to metal 1.

Metal 1 width was also reduced to 0.25um to further minimise spaceand allow for greater routing.The inverters final dimensions were 7.75um in height by 2.83um.Theheight represents the standard cell design which was used forsubsequent gate designs.The simulation of the inverter was carried out using a modified circuitconsisting of four inverters in series Connected to a v pulse and vdcgeneratorthe vdc generator had its DC voltage set to 1.8 V.the vpulse generator had its properties set as follows:DC voltage: 0 V

Voltage 1: 0 VVoltage 2: 1.8 VDelay time:200 sRise Time 200p sFall time: 200p sPulse width: 3.6n sPeriod: 8n sFrom the output graph the following were recorded

Rise Input(ns)

RiseOutput(ns)

dx/dy (ps) dx/dy/2(ps)

10%Voltage

4.133 4.221 87.4 43.7

90%Voltage

4.235 4.239 57.67 28.835

Input risetime

0.102 Outputrise time

0.018

fall Input(ns)

fallOutput


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(ns)10%Voltage

8.346 8.407 60.31 30.155

90%Voltage

8.277 8.366 88.61 44.305

Input FALLtime

0.069 Output falltime

0.041

The average delay was (43.7+28.835+30.155+44.305) /4 = 36.748ps

The power consumed by the inverter was obtained by placing two 0VD.C. sources as passive devices in our circuit to isolate the invertersfrom the remaining circuit . Using the calculator to integrate currentover one period, and multiplying by 1.8V we have 8.006fJ

Average power = 8.006fJ/T= 8.006f/8.067n= 0.99uW at 125MHz

The transfer characteristics was obtained using a D.C. ResponseAnalysis for the inverter to obtain switching values of 583.6mVat1.623V(90%) and 738.8mV at 181.1mV(10%)

The same tests were repeated using parasitic capacitances. This wasachieved by setting the DRC switches to parasitic capacitance during

the extraction processFrom the output graph the following were recorded

Rise Input(ns)

RiseOutput(ns)


10%Voltage

4.126 4.216 90.03 45.015

90%Voltage

4.24 4.30 63.79 31.895

Input risetime


0.084

fall Input(ns)

fall Output(ns)

10%Voltage

8.349 8.415 66.46 33.23

90%Voltage

8.279 8.372 92.87 46.435

Input fall 0.007 Output 0.043


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DELAY XTICS WITH PARASITIC CAPACITANCE


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MEASURING DELAY AND POWER(SCHEMATIC)

MEASURING DELAY


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LAYOUT


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THE 2 INPUT NAND GATEThis layout was implemented using a combination of 3 nmos and pmoscells each. The P-channel transistors are connected in parallel whilethe two N-channel are connected in series The overall dimensions forthis gate were height 7.75um by 5.100um in Width giving a total areaof 39.525um2The delay characteristics as obtained from the graph are recorded asfollows

Rise Input(ns)

RiseOutput(ns)


10%Voltage

4.138 4.292 154.1 77.05

90%Voltage

4.3179 4.3702 52.355 26.175

Input risetime


0.0787

fall Input

(ns)

fall Output

(ns)10%Voltage

16.413 16.506 92.535 46.267

90%Voltage

16.312 16.425 112.54 56.27

Input falltime

0.101 Outputfall time

0.081


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The average delay is (77.05+26.175+46.267+56.27) /4 = 51.44ps

The power consumed by the NAND was obtained by placing two 0VD.C. sources as passive devices in our circuit to isolate the NAND from

the remaining circuit . Using the calculator to integrate current overone period, and multiplying by 1.8V we have6.13fX1.8= 11.04fJ

Average power = 11.04fJ /T= 11.04fJ /8.167n= 1.352uW at 125MHz

The same tests were repeated using parasitic capacitancesFrom the output graph the following were recorded

Rise Input(ns)

RiseOutput

(ns)


10%Voltage

4.147 4.339 182.34 91.17

90%Voltage

4.258 4.45 192.5 96.25

Input risetime


0.111

fall Input(ns)

fall Output(ns)

10%Voltage

16.44 16.57 133.8 66.9

90%Voltage

16.3 16.46 156.9 78.45

Input falltime

0.14 Outputfall time

0.11


The power consumed by the NAND was obtained by placing two 0VD.C. sources as passive devices in our circuit to isolate the invertersfrom the remaining circuit . Using the calculator to integrate currentover one period, and multiplying by 1.8V we have

10.02fX1.8= 18.50fJ



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A B Y0 0 10 1 11 0 11 1 0

NAND TRUTH TABLE

OUTPUT


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DELAY


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POWER OUTPUT/ MEASUREMENT SCHEMATIC

LAYOUT


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THE 2 INPUT NOR GATE

This layout was implemented using a combination of 2 nmos and pmoscells each. P-mos are connected in series while n-mos in parallel Theoverall dimensions for this gate were height 7.75um by 5.00um in

Width representing a total area of 38.75um2

The delay characteristics as obtained from the graph are recorded asfollows

Rise Input(ns)

RiseOutput(ns)


10% 12.15 12.29 141.7 70.85


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Voltage

Input fall time 0.066ps output fall time 0.087psThe average delay is (96.505+98.435+95.355+87.25) /4 = 94.386ps

The power consumed by the NOR was obtained by placing two 0V D.C.sources as passive devices in our circuit to isolate it from theremaining circuit . Using the calculator to integrate current over oneperiod, and multiplying by 1.8V we have10.640fX1.8= 19.15fJ


NOR TRUTH TABLEA B Y0 0 10 1 01 0 01 1 0

NOR OUTPUT


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POWER OUTPUT


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LAYOUT


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THE 2 INPUT XOR GATE

This layout was implemented using a combination of 6 nmos and pmoscells,3 of each. The overall dimensions for this gate were height7.75um by 7.63um in WidthThe delay characteristics as obtained from the graph are recorded asfollows

Rise Input(ns)

RiseOutput (ns)


10%Voltage

4.132 4.272 139.73

90%Voltage

4.278 4.409 130.69

fall Input(ns)

fall Output(ns)

10%Voltage

8.369 8.511 142.02

90%Voltage

8.281 8.424 142.44


The power consumed by the XOR was obtained by placing two 0V D.C.sources as passive devices in our circuit to isolate the inverters fromthe remaining circuit . Using the calculator to integrate current overone period, and multiplying by 1.8V we have10.230fX1.8= 7.698fJ


The same tests were repeated using parasitic capacitancesFrom the output graph the following were recorded

Rise Input(ns)

Rise Output(ns)


10% Voltage 16.38 16.62 236.990% Voltage 16.625 16.886 261.05


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fall Input(ns)

fall Output(ns)

10% Voltage 20.286 20.552 266.0590% Voltage 20.053 20.375 322.78


The power consumed by the XOR was obtained by placing two 0V D.C.sources as passive devices in our circuit to isolate the inverters fromthe remaining circuit . Using the calculator to integrate current overone period, and multiplying by 1.8V we have11.830fX1.8= 21.29fJ

Average power = 21.29fJ /T

= 21.29fJ /8.011n= 2.65uW at 125MHz

XOR TRUTH TABLEA B Y0 0 00 1 11 0 11 1 0


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XOR OUTPUT

RISE/FALL TIMES


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This layout was implemented using a combination of 4 of the cellsabove.( XOR,NAND,NOR,NOT)The overall dimensions for this gate were height 7.75um by 7.64um in

Width

The delay characteristics as obtained from the graph are recorded asfollows

Rise Input(ns)

Rise Output(ns)


10% Voltage 4.694 4.99 295.890% Voltage 4.959 5.084 125.7


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1 1 1 1 1OUTPUT


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AND GATE


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VLSI Design, Characterization, and Use of Custom Standard Cells