Characterization and Abstraction in the Custom Design Flowee241/sp21/assignments/... · 2021. 2. 18. · Characterization and Abstraction in the Custom Design Flow EE241B Lab 4 Written

Characterization and Abstraction in the Custom Design Flow

EE241B Lab 4Written by Harrison Liew (2021)

Overview

In Lab 3, you learned how to do extracted simulations on a placed-and-routed block, then learnedhow to run a standard cell through the the first part of the custom design flow. At the end,you set up extracted simulations of the flip-flop to calculate its setup time. The next task is tobridge the gap from designing the cells to abstracting then in a form that the VLSI flow tools canefficiently consume and process. For example, synthesis and P&R tools must be able to calculatepath delay without running a Spice simulation itself, necessitating timing models. Similarly, P&Ronly cares about the boundary, pins, and blockages of cells instead of the entire transistor-levellayout, necessitating layout abstracts.

In real PDKs, the standard cell library consists of many more cells than a single flip-flop. Each ofthese cells have different functions and therefore different timing parameters beyond setup time.Furthermore, it is important to know how much power each cell consumes, so that the synthesisand P&R tools can minimize overall power consumption. This is all compounded by the fact thatlibraries must be characterized at multiple operating conditions (process, voltage, and temperature),which at the very minimum need to support setup and hold time calculations. With ever-increasingcomplexity and end-applications, successively smaller CMOS nodes have required an characterizingan exponentially larger set of cells and operating conditions, as shown in Fig. 1.

In this lab, we will generate Liberty Timing Files (LIBs) and Library Exchange Format files (LEFs),the two main abstraction collaterals for the VLSI flow. We will also generate the remaining piecesof collateral needed for the VLSI flow and see how this is applicable to not only the standard cells,but also non-digital blocks (such as analog IP) that need to be integrated into a design.

Getting Started

We will once again start with updating our environment. Pull the latest changes to the lab Chipyardrepository.

Then, start your Virtuoso environment as in Lab 3 and make a note of where your exported netlistand extracted netlists are for the flip-flop that you analyzed.

Cadence Liberate: Characterization

Cadence Liberate is a tool that can analyze the function of any circuit and output ”electricalviews”, which contain all the relevant timing relationships between pins, the power consumptioninformation, and more. It accomplishes this by intelligently finding timing arcs, setting up Spice

EE241B Lab 4, The Custom Design Flow: Characterization and Abstraction, Spring 2021 2

Figure 1: Exponential Growth in Library Characterization

simulations, and measuring parameters like delay and currents automatically, thereby vastly im-proving the time it takes to prepare a cell for the digital VLSI flow.

A summary of all the things that various Liberate tools can characterize is shown in Fig. 2, which istaken from the reference manual at /share/instsww/cadence/LIBERATE/doc/liberate/liberate.pdf.In this lab, we will only use Liberate Characterization to generate LIBs for our flip-flop.

Figure 2: The Complete Cadence Liberate Suite


LIB Files

Liberty Timing Files (LIBs) are an IEEE standard. A very high-level introduction of the keyparameters and format of the standard is described here, which corresponds to a basic timingmodel called the Non-Linear Delay Model (NLDM). It is a simple lookup table-based model whichdescribes delays and rise/fall times for various input waveforms and output loads that results insmall LIB files at a moderate accuracy loss compared to a Spice simulation.

With deeply-scaled technologies, however, switching events actually generate significant transientcurrent and voltage spikes, which can cause glitching on critical and neighboring nets. As a result,additional LIB models are needed to accurately model these effects, namely Composite CurrentSource (CCS) and Effective Current Source Model (ECSM), which non-linearly sample the outputcurrent and voltage waveforms, respectively, and are shown in Figs 3 and 4. CCS models aregenerally used for Synopsys VLSI tools (Design Compiler, IC Compiler), while ECSM models aregenerally used for the Cadence tools that we have used so far.

Finally, there are additional things to characterize: power, noise immunity, signal integrity, processvariation, and electromigration. Liberate will by default analyze power and its importance is self-explanatory, but the latter few are used to ensure product reliability. You will learn about these inlecture but they are outside the scope of this lab.

Figure 3: Composite Current Source Model

Figure 4: Effective Current Source Model

http://web.engr.uky.edu/~elias/lectures/LibertyFileIntroduction.pdf


Generating LIBs

Notice that there is now a folder called vlsi/asap7 lib. Inside, there are a few TCL files anda Makefile. Let’s go through them one-by-one to see how Liberate works in order to characterizethe flip-flop we looked at in Lab 3. We will also then compare it against the LIB that comes from thePDK, which is located at ~ee241/spring21-labs/asap7libs 24/lib/asap7sc7p5t 24 SEQ RVT TT.lib.

The Makefile is very simple. You can see that CELL TYPE is set to DFF, which passes char DFF.tcl

to the liberate command. This TCL file is set up for characterizing D flip-flops.

char DFF.tcl is divided into a few short sections:

1. It sources a template file template asap7.tcl that we will look at next.

2. You then choose between 3 PVT corners: TT 0p7V 25C, SS 0p63V 100C, and FF 0p77V 0C.These PVT corners correspond to the corners that were characterized by the developers ofthe ASAP7 PDK. The relevant ASAP7 Spice transistor model file is selected based on theprocess corner.

3. You then specify the names of the D flip-flops that you want to characterize for this LIB, readthe PEX netlists for those cells, and define I/O and template parameters of this cell family,which denotes that CLK is the clock port, D is an input port, QN is the output port, and somedelay/constraint/power templates (see below).

4. Finally, the cells are characterized at the chosen PVT corner and written to a .lib file.

template asap7.tcl sets some base units and a bunch of variables and templates that are actuallygenerated from the source LIB for the flip-flip we are analyzing (DFFHQNx1 ASAP7 75t R). Here’swhat the variables mean (summarizing from the reference manual):

• (measure )slew lower/upper rise/fall: Together, these 8 variables pass through to theoutput LIB and tell Liberate that output transition time values are measured between 10%to 90% of the supply voltage.

• delay inp/out rise/fall: Together, these tell Liberate to measure the delay from an inputto output for both edges at the 50% of supply voltage point.

• def arc msg level and process match pins to ports: These tell Liberate to throw an errorif no valid arcs are found and if the pin list is incorrect. This can help detect an mismatcheddefine cell command setup relative to the cell being characterized.

• max/min transition: These get encoded in the LIB as a min/max bound for transition timeson any pin. These values are passed onto synthesis and P&R to prevent them from sizingdriving cells and loads too large or small.

• min output cap: This sets the minimum output load during the characterization simulations.

• define template -type delay: This is a table for delay characterization for various valuesof input slew (index 1) and output load (index 2). It is named delay template 7x7 whichthe delay tables will refer to in the generated LIB.

• define template -type constraint: This is a table for timing constraint (setup, hold, etc.)characterization. Here, index 1 is a range of input slews on the data and index 2 is a rangeof input slews of the reference signal (clock, reset, etc.).


• define template -type power: This is a table for switching and internal power consump-tion. Here, index 1 is a range of input slews and index 2 is a range of output loads.

Q1: What is the benefit of specifying min/max transition times? Hint: think aboutsignal integrity and crowbar currents.

Q2: The template tables are optimized for a DFFHQNx1 ASAP7 75t R cell, which is thesmallest available D flip-flop. For larger D flip-flops (i.e. larger internal transistorsand output drive strengths), are the provided template tables suitable? If not, whichtables might we want to change and how? To verify your hypothesis, check againstthe PDK’s LIB.

Now, let’s generate the LIB. Copy or symlink the PEX netlists for your flip-flop from Lab 3into this asap7 lib folder. There are 3 files you need: the ones that end in .pex.netlist,.pex.netlist.pex, and .pex.netlist.<cellname>.pxi. Then, run:

make gen-libs

After a couple minutes, it will output a DFF <PVT corner>.lib file, as well as a log a file. Openup the generated LIB to compare against the PDK’s LIB, then answer these questions:

Q3: Glance through the two LIBs and note any high-level differences between thecharacterization results of your flip-flop and the PDK’s DFFHQNx1 ASAP7 75t R.

Q4: Examine the setup and hold time tables. Given the constraint template, explainwhy there are both positive and negative values.

Q5: Repeat the characterization for the PVT corners that would be used for setup andhold analysis (which corners are these, respectively?). Show some general comparisonsof setup/hold timing and active/leakage power between these LIBs and the typicalPVT corner LIB we generated first.

Extra Credit: Decoder LIB

Characterize the decoder that we extracted in Lab 3 at the setup PVT corner. You will need tomake your own char decoder.tcl script. Note that the clk pin in the decoder is not a clock,just a regular input. You can also use bus notation such as A[3:0] for the A and Z pins. Thecharacterization will take a few hours with significant compute utilization, so be mindful of otherusers. Attach your new characterization script to your lab report, then answer these questions:

Q6: Compare the leakage power characterized by Liberate against the post-synthesisfinal gates.rpt – how well do they match up?

Q7: Compare the LIB’s combinational delay table against the post-P&R timing report.Can you estimate the output load capacitance that is modeled in Innovus for thelongest delay path?

Q8: Why are synthesis and P&R tools are able to time this block much faster thanLiberate, beyond the fact that standard cell LIBs are available? Is Liberate the righttool for generating LIBs for all kinds of designs? If not, why?


Cadence Abstract: Layout Abstracts

Cadence Abstract is a tool attached to Virtuoso that generates a layout abstraction for P&R tools.An abstract is a high-level representation of a layout view, containing information about the typeand size of cells, positions of pins, and the size and type of blockages. These abstracts are usedin place of full physical layouts so that P&R tools can have better performance. In the P&Rprocess, only the bare minimum information is needed for it to know where it is allowed to placecells and how to route to them; extracting this information from the full layouts would consumeexcess resources. Finally, if you want to integrate some IP into your chip, whether it is SRAM,data converters, etc., abstracts are a way to keep everything inside the IP as a blackbox from theperspective of the physical design flow.

A summary of the Abstract tool and instructions are found in the documentation at/share/instsww/cadence/IC617/doc/abstract/abstract.pdf. If you are going to generate morecomplex abstracts for your project, this is very important to reference. In this lab, we will use Ab-stract to generate LEFs for our flip-flop.

LEF Files

Library Exchange Format (LEF) is an open industry standard that was developed by a companythat has since been acquired by Cadence. It is an ASCII text format and is often used in conjunctionwith the very similar Design Exchange Format (DEF) files in order to fully describe abstract layouts.An introduction to LEF can be found here and the full LEF/DEF Language Reference Manual canbe found at /share/instsww/cadence/IC617/doc/lefdefref/lefdefref.pdf.

In general, VLSI tools need to take a set of abstracts that in aggregate describe the basic technologyrules and information about all macros to be used. In the LEF specification, technology rules arespecified in a technology LEF that will contain definitions of layers, manufacturing grids, vias, andsites (i.e. the standard cell unit height/width). Macro information is specified in separate LEFsthat contain definitions of class (type of cell), size, symmetry, pins, and obstructions (i.e. areas notavailable for routing). We will now explore how to generate the latter type of LEF.

Generating LEFs

In the directory which you have set up your Virtuoso environment from Lab 3, source all thenecessary environment scripts again, and then run abstract:

abstract &

Be advised that Abstract is quite an old tool, and may display like this in your X2Go session, wherea lot of the menu text is invisible:

https://www.csee.umbc.edu/courses/graduate/CMPE641/Fall08/cpatel2/slides/lect04_LEF.pdf


Figure 5: Incorrectly Displayed Abstract

There are 2 possible solutions. The first is to shutdown your existing X2Go session and re-installyour X2Go with all legacy fonts, as shown here for a Windows installer:

Figure 6: Selecting Legacy Fonts in X2Go Installer

The other solution is to rely solely on X11 forwarding over an SSH terminal, which may be slowand cause you to lose your work if the connection drops.

Take a look at the toolbar buttons – these correspond to the steps needed to generate an abstract.We are going to go through them from left to right:

1. Click the Library button (looks like a book). Select the Virtuoso library that contains yourcustom DFF from Lab 3. You should see that the custom dff R cell appears on the rightpane – click on it. You should also see 1 cell in the Core ”bin” on the left pane. The binscorrespond to the types of cells that the LEF specification defines; for a standard cell that wehave it should be in the Core bin, but for things like larger IP blocks, you would want themin the Block bin. To do this, you would select the cell, go to Cell > Move, and select thedestination bin.

2. Click the Layout button (looks like 2 wires and 2 vias). This is used to import a layout froma GDS file, such as if somebody else gave you a finished layout in GDS format and not as aVirtuoso library. Since our flip-flop already has a layout view in Virtuoso, we can hit Cancelout of this dialog box.


3. Click the Logical button (looks like an inverter symbol). This tells the tool what the pinsare. Since we just generated a LIB, select LIB as the Filetype and browse to the LIB youcreated just now. For other cells, we can also import Verilog shell instead, which would justdefine the module and ports but does not need implementation.

4. Click on the Pins button (a square with an X inside). This is where we select options forhow to extract pin shapes from the pin labels in the layout view and pin directions from thelogical view. There are 4 tabs: Map, Text, Boundary, and Blocks.

• In the Map tab, under the field ”Map text labels to pins”, type (M1 M1) (M2 M2) (M3

M3) (M4 M4) (M5 M5) (M6 M6) (M7 M7) (M8 M8) (M9 M9) (Pad Pad). This meansthat all pin labels on each layer M1 are mapped to shapes on the same layer. Leave theother fields as-is.

• In the Text tab, do not change anything. However, this can be used if you want touse regex to change the pin names between the layout and abstract view (e.g. bus bitdesignators).

• In the Boundary tab, do not change anything. Here, the listed layers will designate therectangular P&R boundary of the cell we want to extract. With the ”as needed” option,it will create a boundary only if a prBoundary shape is not defined in the layout view.Other designs may want to restrict the layers used.

• In the Blocks tab, do not change anything. This is only used to process pre-routedlayouts that are imported from a DEF file.

Now, click Run. The abstract log should tell you that 5 pins have been created.

5. Click on the Extract button (like the Layout button without the wire underneath). Thisis used to trace the connectivity between shapes and terminals, and also generate antennadata. There are 4 tabs: Signal, Power, Antenna, and General. You do not need to changeanything in any tab. In the first 3 tabs, for each layer, there exists a ”Geometry Specification”field. For advanced usage, you can generate Boolean functions of multiple layers to defineconnectivity layers. Here are some other pointers for advanced usage later on:

• Must connect pins are for situations where the same pin name exists in disjoint locations(i.e. not internally connected), and must be connected together in P&R, which recognizesthe MUSTJOIN specification.

• Antenna extraction is necessary for larger blocks with pins that have long wires. Thisinformation is used for P&R to decide whether it needs to do things like switch layersto avoid antenna violations. This is beyond the scope of this lab.

• The layer connectivity list in the General tab is very important to get right. By default,this is filled in correctly and lists the via layers that join adjacent metal layers.

Now, click Run. The abstract log should tell you that all 5 nets have been extracted.

6. Click on the Abstract button (square nestled in an L-shape route). This step adjusts pins andcreates blockages, overlaps, and grids. There are 7 tabs: Adjust, Blockage, Density, Fracture,Site, Overlap, and Grids.

• In the Adjust tab, do not change anything. However, for larger designs (such as analogblackboxes), you will often want to select the ”Create boundary pins” option to confinethe generated pin shape to a square abutting the P&R boundary rather than over theentire block (prerequisite is that all pins are routed to the edge of the boundary).


• In the Blockage tab, we encode how shapes on various layers turn into blockages. For thisflip-flop, do not change anything; however, for larger designs (such as analog blackboxes),this is a very important tab. There are 3 types of blockages that can be generated foreach layer: detailed, shrink, and cover. Detail generates a blockage shape for everypiece of geometry on that layer – this is useful only for standard cells and the topmostlayers of large blocks. Shrink fills in the smaller, less useful spaces between shapes,which would allow for over-the-cell routing without modeling each obstruction in detail.Cover generates an obstruction covering the entire block for that layer, which is usedfor layers which should be off-limits for the P&R tool. In general, you want to coveras much of your block as necessary, and only expose in shrink or detail the layers thatare available for P&R to do routing on. This both increases the efficiency of P&R andreduces the chances that routing will cause DRC/LVS issues with the abstracted block.In the extreme case, analog IP with structures like inductors at the top-level need tocover block all layers, exposing only boundary pins. Additional advanced options in thistab will generate cutouts around pins and create routing channels on cover block layers.

• In the Density tab, do not change anything. This is used to encode density information,which is particularly helpful to help automatic fill tools achieve required min/max densitywithout needing to calculate it from the full layout of any blackboxes.

• In the Fracture tab, do not change anything. This is used to fracture pins and blockagesfrom polygons to rectangles if required for certain P&R tools.

• In the Site tab, for the site name, select coreSite. This is required for cells in the CORE

bin like our flip-flop in order to tell the tool that it belongs to the coreSite site, likefor all standard cells that need to be placed in ordered rows. For other types of cells, donot do this.

• In the Overlap tab, do not change anything. This is particularly useful for larger de-signs where you want to generate a second, more detailed boundary that is a rectilinearpolygon. This overlap layer can be generated from specific layers and will be used totest if cells truly overlap when in P&R they are placed with overlapping boundaries.

• In the Grids tab, do not change anything. This is a tool to help check if all geometry(wires and pins) are properly on the manufacturing grids, which is useful for standardcells but less so for larger designs. Our flip-flop is already fine, so we can skip this tool.

Now, click Run. The abstract log should tell you that blockages are created for each layerand do a power rail analysis.

7. Finally, click the Verify button (it has a check mark). This step helps you check your abstractagainst rules and various P&R tools. Cancel out of this step, as we will just move ontogenerating the LEF.

Q9: Why do we generally only want to generate pin shapes on metal layers, and notlayers such as n-well and p-substrate?

Q10: Say we want to abstract an SRAM block with signal and power pins on M4 andall internal routing on M4 and below. For which layers should we generate cover,shrink, and detailed blockages? Should we create boundary pins for signal and/or


power nets?

Q11: Why are there minimum and maximum density requirements for every layer ina technology stackup?

Q12: Provide a simple drawing of a case where creating an Overlap layer would bebeneficial.

Finally, we are ready to export the LEF. Go to File > Export > LEF. In the window thatappears, set the LEF filename to custom dff R.lef (or something else of your choosing). Select5.8 as the LEF version, then hit OK.

Now, open the LEF you just created alongside the LEF provided in the PDK at~ee241/spring21-labs/asap7libs 24/lef/scaled/asap7sc7p5t 24 R 4x 170912.lef. In the lat-ter file, scroll down to the part that starts with MACRO DFFHQNx1 ASAP7 75t R. As you compare thetwo files, note that the LEFs provided in the PDK have been manually scaled up by 4x in order toget around needing extra sub-20nm Innovus licenses.

Q13: Minus the scaling factor, would the the abstract of the flip-flop we just generatedfit properly in the coreSite site, which is 1.08um tall (4x scaled dimension)? If not,why (hint: look at the layout), and what would we need to change when generatingthe abstract?

Q14: Notice how for the CLK pin it says USE CLOCK for our LEF while in the PDK’s LEFit says USE SIGNAL. How did our abstract run know it’s a clock pin, and what wouldwe do differently to make it just a signal?

Q15: The OBS section contains our detailed obstructions. What would it look like ifinstead we did COVER for layer M2? Why would this pose problems for us in P&R?What about COVER for layer V1?

All the the steps we took in the Abstract GUI have actually been recorded for us. In the directoryof the library containing the flip-flop, there is a .abstract.options file. This file contains all ofthe options corresponding to the current state of our Abstract GUI after all of our changes. In thedirectory in which you launched Abstract, there is a abstract.record file. This file contains thecommands corresponding to the steps we took. In the future, you can take and modify these twofiles in order to run Abstract from the command line (see the section ”Log, Replay, and RecordFile Behavior” in the Abstract user guide).

Finally, in the Virtuoso library, for the custom dff R cell, there is now an abstract view. We canopen this in the Virtuoso layout editor!

Q16: Submit a screenshot of the abstract view of the flip-flop, as viewed in Virtuoso.

Extra Credit: Decoder LEF

Your challenge is to use both Innovus and Abstract to generate a LEF of the decoder from Lab 3.To generate a LEF from Innovus, open the P&R’d decoder using the open chip script. Then, inthe Innovus, use the write lef abstract command with the following options:-stripe pins -pg pin layers 9. To figure out how to use this command, type man write lef abstract


first. Study the generated LEF to understand what it specifies.

Note for Abstract: from our P&R run, we have already generated a GDS and a Verilog file usedfor LVS. These two files are sufficient to generate a LEF with Virtuoso and Abstract.

Q17: In your lab report, detail the steps/options you set in order to get Abstractto generate a LEF that is as close as possible to the LEF generated from Innovus.Summarize any remaining discrepancies between the generated LEFs.

Note that P&R flows for complex chips require a hierarchical flow, which would require generatingall the views of P&R’d sub-blocks before integrating in a higher level of P&R. In this case, Innovuswill generate all that for you when the hierarchical flow is setup properly.

Remaining Views

So far, we have learned how to generate the Spice netlist (CDL), LIB, and LEF of custom designs.The remaining important views are the Verilog netlist (for synthesis and simulation) and the fulllayout GDS, for merging into the final layout.

Verilog

There are two cases where Verilog is used. The first is for synthesis, which are just wrappers andare needed for blackboxes (e.g. SRAMs, analog IP). This can be generated using Liberate withthe write top netlist command (see the manual or type help write top netlist for details).More often, it is done manually in your source netlist, since only the port list needs to be defined.

The second case is for simulation. This Verilog file would describe the behavior of the design, andis often hand-written along with your design during functional verification.

GDS

This can be generated from Virtuoso. In the CIW, go to File > Export > Stream. Then,select the layout view of the cell to export, change the Stream File name if desired, and selectasap7 TechLib as the Technology Library. Hit Translate and it will generate a GDS file.

Adding an Extra Library in Hammer

To ensure that the Hammer flow knows about our new custom cell, we would need to append to thelist of vlsi.technology.extra libraries. An example is found in the vlsi/example-asap7.ymlfile in your Chipyard repository, starting on line 85 and reproduced here for a dummy DCO. Toround it out for the whole flow, you would also include spice netlist for LVS, verilog synth

for synthesis (if not already included in your source Verilog), and verilog sim for simulation.

vlsi.technology.extra_libraries_meta: ["append", "deepsubst"]

vlsi.technology.extra_libraries:

- library:

nldm liberty file_deepsubst_meta: "local"

nldm liberty file: "extra_libraries/example/ExampleDCO_PVT_0P63V_100C.lib"


lef file_deepsubst_meta: "local"

lef file: "extra_libraries/example/ExampleDCO.lef"

gds file_deepsubst_meta: "local"

gds file: "extra_libraries/example/ExampleDCO.gds"

corner:

nmos: "slow"

pmos: "slow"

temperature: "100 C"

supplies:

VDD: "0.63 V"

GND: "0 V"

- library:

nldm liberty file_deepsubst_meta: "local"

nldm liberty file: "extra_libraries/example/ExampleDCO_PVT_0P77V_0C.lib"

lef file_deepsubst_meta: "local"

lef file: "extra_libraries/example/ExampleDCO.lef"

gds file_deepsubst_meta: "local"

gds file: "extra_libraries/example/ExampleDCO.gds"

corner:

nmos: "fast"

pmos: "fast"

temperature: "0 C"

supplies:

VDD: "0.77 V"

GND: "0 V"

Conclusion

This lab was meant to round out the custom design flow. You now know how to generate all of therequired collateral for the VLSI tools for both a standard cell and a bigger custom cell. You learnedhow to use Cadence Abstract Generator (to create the LEF) and Cadence Liberate (to create theLIB) in detail, which may come in handy for your projects if you need to rapidly characterize andabstract custom cells.

As described, there are still multiple characterizations that we have not explored in depth, such aspower, leakage, electromigration, antenna, and more. We have also not taken into account processvariation in the characterization results. These are left for you to explore for your projects or futureresearch.

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Characterization and Abstraction in the Custom Design Flowee241/sp21/assignments/... · 2021. 2. 18. · Characterization and Abstraction in the Custom Design Flow EE241B Lab 4 Written