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VHDL Overview
Arturo Díaz-PérezDepartamento de Computación
Laboratorio de Tecnologías de InformaciónCINVESTAV-IPN
Outline
HistoryExisting LanguagesVHDL RequirementsVHDL LanguageVHDL Based Design ProcessLevels of Abstraction
VHDL Milestones
1981 DoD, Woods Hole MA. Workshop on HDLs.1983 Dod. Requirements were established. Contract awarded to IBM, TI, Intermetrics.1984 IBM, TI, Intermetrics. VHDL 2.0 was defined.December 1984. VHDL 6.0 was released. Software development started.1985. VHDL 7.2 was released to IEEE.May 1985. Standard VHDL 1076/A.December 1987. VHDL 1076-1987 became IEEE standard.1993. VHDL 1076-1993 was approved.
VHDL Requirements Hierarchy
Use various levels of abstraction for defining a system.Upper level systems are partitioned into lower.
StackALU
MUX
Counter
ALU bitAdder MUX Logic
AND OR NOTMUX
Bit n Bit n-1 Bit 0ALU
VHDL Language
A concurrent language for hardware descriptionAllows sequential bodies
EntittyArchitecturePackageConfigurationsStrong Timing Support
VHDL Environment
TextEditorText
Editor
AnalyzerAnalyzer
VHDLSimulatorVHDL
SimulatorVHDL Input
LibraryManagement
Library System
Design Libraries
LayoutSynthesizer
LayoutSynthesizer
NetlistSynthesizer
NetlistSynthesizer
Other ToolsOther Tools
LibraryEnvironment
LibraryEnvironment
Existing HDLs
AHPL: A Hardware Programming LanguageCDL: Computer Design LanguageCONLAN: CONsensus LANguageIDL: Interactive Design LanguageISPS: Instruction Set Processor SpecificationTEGAS: TEst Generation And SpecificationTI-HDL: Texas Instruments Hardware Description LanguageZEUS: An HDL by GE corporation
VHDL Requirements
General Features: documentation, high level design, simulation, synthesis, test, automatic hardware.Design Hierarchy: Multilevel description, partitioning.Library Support: Standard packages, cell based design.Sequential Statements: Behavioral software-like constructs.Generic Design: Binding to specific libraries.Type Declaration: strongly typed language.Subprograms.Timing: delay and concurrency.Structural specification: wiring components.
VHDL Modeling
ENTITY unit ISPORT( i0, i1, …, in, clk: IN BIT; q0, q1 …, qm: OUT BIT );
END unit;--ARCHITECTURE structural/behavioral OF
unit IS…..
BEGIN// Concurrent statements. . .
END structural/behavioral;
i0
i1i2
in
q0
q1q2
qm
Basic Components
invi1 o1
nand2i1o1
i2
nand3i1o1i2
i3
Syntax Details
ENTITY inv ISPORT(
i1: IN BITo1: OUT BIT
);
END inv;
PORT(
i1, i2:INBIT;
o1: OUT BIT)
interface signal declarationinterface signal declaration
portclause
entitydeclaration
portclause
identifier list
modetype
interface signal declaration
interfacesignaldeclaration interface
list
Hardware Modeling Requirements
a
b
c
x
y
zg2
g3
g4g1
g1
g2
g3
g4
reacting
reacting
reacting
reacting reacting
0 12 24 36 0 12 24 36
a
b
c
w
x
y
z
• Proper modeling requires simultaneous processing• Waveform shows node values
Objects and Classes
v_vars_sig
del 1CKT
a
b y
x
signals
• Signals for hardware carriers• Variables are temporary carriers• Constants for fixed parameters• A signal is an object whose class is signal
Signals and Variables
sequential body concurrent body..variable x_var .....
.
.signal x_sig .....
.
.x_var := .....x_sig <= .....
.
.x_sig <= .....
• Signal assignments have a time component• x_sig <= value AFTER 6 NS;
Concurrent & sequential assignments
.
.x_sig <= val1 ;.y_sig <= a_sig ;..z_sig <= val2
WAIT FOR 5 NS;z_sig <= val3;..
sequential body concurrent body
.x_sig <= val1 ;.y_sig <= a_sig ;..z_sig <= val2, val3 AFTER 5 NS ;..
• val2 and val3 are sequentially placed on z_sig• Assignment of a_sig to y_sig is done:
• in the concurrent body, when event ocurrs on a_sig• in the sequential body, when program flow reaches it
A Concurrency Example
ENTITY example ISPORT( a, b, c: IN BIT; z: OUT BIT );
END example;--ARCHITECTURE concurrent OF
example ISSIGNAL w, x, y: BIT;
BEGINw <= NOT a AFTER 12 NS;x <= a AND b AFTER 12 NS;y <= c AND w AFTER 12 NS;z <= x OR y AFTER 12 NS;
END concurrent;
0 12 24 36
a
b
c
w
x
y
z
• Properly model gate lavel circuit by concurrency• Assume a changes from ‘1’ to ‘0’ at time 0
Multiplexer VHDL DescriptionUSE WORK.basic_utilities.ALL;-- FROM PACKAGE USE: qit, qit_vectorENTITY mux_8_to_1 IS
PORT( i7, i6, i5, i4, i3, i2, i1, i0: IN qit;s7, s6, s5, s4, s3, s2, s1, s0: IN qit; z: OUT qit );
END mux_8_to_1;--ARCHITECTURE dataflow OF mux_8_to_1 IS
SIGNAL sel_lines: qit_vector( 7 DOWNTO 0 );BEGINsel_lines <= s7&s6&s5&s4&s3&s2&s1&s0;WITH sel_lines SELECT
z <= ‘0’ AFTER 3 NS WHEN “00000000”,i7 AFTER 3 NS WHEN “10000000” | “Z0000000”,i6 AFTER 3 NS WHEN “01000000” | “0Z000000”,i5 AFTER 3 NS WHEN “00100000” | “00Z00000”,i4 AFTER 3 NS WHEN “00010000” | “000Z0000”,i3 AFTER 3 NS WHEN “00001000” | “0000Z000”,i2 AFTER 3 NS WHEN “00000100” | “00000Z00”,i1 AFTER 3 NS WHEN “00000010” | “000000Z0”,i0 AFTER 3 NS WHEN “00000001” | “0000000Z”,‘X’ WHEN OTHERS;
END dataflow;
01234567
G0G1G2G3G4G5G6G7 z
MUX
Syntax Details
WITHsel_linesSELECTz <=
. . .i4 AFTER 3 NS
WHEN“00010000” | “000Z0000”,
. . .‘X’
WHENOTHERS;
waveform
choices
waveform
choices
selectedwaveform
selectedwaveform
expressiontarget
selectedwaveforms
Decoder
USE WORK.basic_utilities.ALL;-- FROM PACKAGE USE: qit, qit_vectorENTITY dcd_3_to_8 IS
PORT( adr: IN qit_vector(2 DOWNTO 0);s0: OUT qit_vector(7 DOWNTO 0) );
END dcd_3_to_8;--ARCHITECTURE dataflow OF dcd_3_to_8 IS
BEGINWITH adr SELECT
s0 <= “00000001” AFTER 2 NS WHEN “000”,“00000010” AFTER 2 NS WHEN “00Z” | “001”,“00000100” AFTER 2 NS WHEN “0Z0” | “010”,“00001000” AFTER 2 NS WHEN “0ZZ” | “0Z1” | “01Z” | “011”“00010000” AFTER 2 NS WHEN “Z00” | “100”,“00100000” AFTER 2 NS WHEN “Z0Z” | “Z01” | “10Z” | “101”,“01000000” AFTER 2 NS WHEN “ZZ0” | “Z10” | “1Z0” | “11Z”,“10000000” AFTER 2 NS WHEN “ZZZ” | “ZZ1” | “Z1Z” | “1ZZ” |
“Z11” | “1Z1” | “11Z” | “111”,‘XXXXXXX’ WHEN OTHERS;
END dataflow;
A0A1A2
G0G1G2G3G4G5G6G7
DCD
Single Bit Comparatora
b
gt
eq
lt
a_gt_b
a_eq_b
a_lt_b
A
B
>
=<
A>BA=B
A<B
11 1 1
00 01 11 100
1
a,b>
a>b
1 1
00 01 11 100
1
a,b=
a=b
11 1 1
00 01 11 100
1
a,b<
a<b
• A cascadable bit comparator• When a > b the a_gt_b becomes 1• When a < b the a_lt_b becomes 1• If a = b outputs become the same as corresponding inputs
SBC: Logic Design
a
bgt
eq
lt
a_gt_b
a_eq_b
a_lt_b
ab
b
a
SBC: Aspect Notationabgteqlt
a_gt_ba_eq_ba_lt_b
bit comparator
b
gteqlt
a
a_gt_b
a_eq_b
a_lt_b
invi1 o1
invi1 o1
nand3i1o1i2
i3
i1i2
nand2o1
i1i2
nand2o1
i1i2
nand2o1
nand3i1o1i2
i3
i1i2
nand2o1
i1i2
nand2o1
i1i2
nand2o1
i1i2
nand2o1
nand3i1o1i2
i3
nand3i1o1i2
i3
bit comparator (gate level)
im1
im2
im3
im4
im5
im6
im7
im8
im9
im10
SBC: Structural DescriptionENTITY bit_comparator IS
PORT ( a, b, -- data inputsgt, -- previous greater thaneq, -- previous equallt: IN BIT -- previous less thana_gt_b, -- greatera_eq_b, -- equala_lt_b: OUT BIT ); -- less than
END bit_comparator;--ARCHITECTURE gate_level OF bit_comparator IS...BEGIN
. . .END gate_level;
VHDL description consists of an entity and an architectureInterface description is done by the entity declarationDescription of the operation will be given in the architectureSignal names of interface and composition aspects are used
SBC: VHDL StructuralDescription
ARCHITECTURE gate_level OF bit_comparator ISCOMPONENT n1 PORT( i1: IN BIT; o1: OUT BIT ); END COMPONENT;COMPONENT n2 PORT( i1, i2: IN BIT; o1: OUT BIT ); END COMPONENT;COMPONENT n3 PORT( i1, i2, i3: IN BIT; o1: OUT BIT ); END COMPONENT;FOR ALL: n1 USE ENTITY WORK.inv( single_delay );FOR ALL: n2 USE ENTITY WORK.nand2( single_delay );FOR ALL: n3 USE ENTITY WORK.nand3( single_delay );
-- Intermediate signalsSIGNAL im1, im2, im3. im4, im5, im6, im7, im8, im9, im10;
BEGIN-- a_gt_b output
g0: n1 PORT MAP( a, im1 );g1: n1 PORT MAP( b, im2 );g3: n2 PORT MAP( a, im2, im3 );g4: n2 PORT MAP( a, gt, im4 );g5: n3 PORT MAP( im3, im4, im5, a_gt_b );
-- a_eq_b outputg6: n3 PORT MAP( im1, im2, eq, im6 );g7: n3 PORT MAP( a, b, eq, im7 );g8: n2 PORT MAP( im6, im7, a_eq_b );
-- a_lt_b outputg9: n2 PORT MAP( im1, b, im8 );g10: n2 PORT MAP( im1, lt, im9 );g11: n2 PORT MAP( b, lt, im10 );g12: n3 PORT MAP( im8, im9, im10, a_lt_b );
END gate_level;
Syntax Details
ARCHITECTURE gate_level OF bit_comparator ISCOMPONENT n3
PORT( i1, i2, i3: IN BIT;o1: OUT BIT );
END COMPONENT;...
FOR ALL: n3USE ENTITY WORK.nand3( single_delay );
....SIGNAL im1, im2, im3. im4, im5,
im6, im7, im8, im9, im10;BEGIN...
g7:n3
PORT MAP( a, b, eq, im7 );g8: n2 PORT MAP( im6, im7, a_eq_b );
....END gate_level;
componentdeclaration
configurationspecification
signaldeclaration
componentinstantiationstatement
architecturedeclarativepart
architecturestatementpart
architecturebody
VHDL Design Process
IF 110 found on x_in THENz_out := NOT y_in
ELSEz_out := 0
x_in
y_in
enable
z_out
VHDL Behavioral Description
ba c
0/00/0
1/0 1/0
1/0
0/(z_out := NOT y_in)
VHDL Behavioral Description
ENTITY moore_110_detector IS PORT( x, y, clk: IN BIT; z: OUT BIT );
END moore_1110_detector;--ARCHITECTURE behavioral OF
moore_110_detector ISTYPE state IS (reset, goto1, goto11, goto110);
SIGNAL current: state := reset;BEGIN
PROCESS(clk)BEGIN
IF clk = ‘1’ THENCASE current IS
WHEN reset =>IF x = ‘1’ THEN current <= goto1;ELSE current <= reset; END IF;
WHEN goto1 =>IF x = ‘1’ THEN current <= goto11;ELSE current <= reset; END IF;
WHEN goto11 =>IF x = ‘1’ THEN current <= goto11;ELSE current <= goto110; END IF;
WHEN goto110 =>IF x = ‘1’ THEN current <= goto1;ELSE current <= reset; END IF;
END CASE;END IF;
END PROCESS;z <= not y WHEN current = goto110 ELSE ‘0’;
END behavioral;
VHDL Dataflow Description
STATE V0 V1 0 1x_in
abc-
0011
0101
00,000,000,y--,-
01,010,010,y--,-
• Clock level timing details are specified• Can generate corresponding VHDL
Moore_110_Detector
Moore_110_DetectorMoore_110_Detector
Logical PartLogical Part Memory PartMemory Part
d logic 1d logic 1 d logic 2d logic 2 z logicz logic dff0dff0 dff1dff1
Moore_110_Detector: Overall Structure
D 0 QCLK
D 1 QCLK
clk
x
d logic 0
d logic 1
z logic
z
memorypart
logical part
Moore_110_detector: Logical Functions
ENTITY dff ISPORT( d, clk: IN BIT; q: OUT BIT );
END dff;--ARCHITECTURE dataflow OF dff ISBEGIN
b: BLOCK (clk = ‘1’ AND NOT clk’STABLE)BEGIN
q <= GUARDED d AFTER 11 NS;END BLOCK;
END dataflow;
ENTITY logicfunction_f ISPORT( i1, i2, i3: IN BIT; o1: OUT BIT );
END logicfunction_f;--ARCHITECTURE dataflow OF logicfunction_f ISBEGIN
o1 <= ((NOT i1) AND i2) OR ((NOT i2) AND i1 AND i3 ) AFTER 8 NS;END dataflow;
Moore_110_detector: Logical Functions
ENTITY logicfunction_g ISPORT( i1, i2, i3: IN BIT; o1: OUT BIT );
END logicfunction_g;--ARCHITECTURE dataflow OF logicfunction_g ISBEGIN
o1 <= (i2 AND (NOT i1) AND (NOT i3)) OR (i2 AND i1 AND i3) OR ((NOT i2) AND (NOT i1) AND i3) AFTER 8 NS;
END dataflow;
ENTITY logicfunction_z ISPORT( i1, i2, i3: IN BIT; o1: OUT BIT );
END logicfunction_z;--ARCHITECTURE dataflow OF logicfunction_z ISBEGIN
o1 <= (i2 AND (NOT i1) AND (NOT i3)) AFTER 8 NS;END dataflow;
Moore_110_detector: LogicalPart
ENTITY logical_part ISPORT( x, q0_in, q1_in: IN BIT; d0_out, d1_out, z_out: OUT BIT );
END logical_part;--ARCHITECTURE structural OF logical_part IS
COMPONENT c1 PORT( i1, i2, i3: IN BIT; o1: OUT BIT );END COMPONENT;FOR d_logic0: c1 USE ENTITY WORK.logicfunction_g( dataflow );COMPONENT c2 PORT( i1, i2, i3: IN BIT; o1: OUT BIT );END COMPONENT;FOR d_logic1: c1 USE ENTITY WORK.logicfunction_f( dataflow );COMPONENT c2 PORT( i1, i2, i3: IN BIT; o1: OUT BIT );END COMPONENT;FOR z_logic: c1 USE ENTITY WORK.logicfunction_z( dataflow );
BEGINd_logic0: c1 PORT MAP( q0_in, q1_in, x, d0_out );d_logic1: c1 PORT MAP( q0_in, q1_in, x, d1_out );d_logic1: c1 PORT MAP( q0_in, q1_in, x, z_out );
END structural;
Moore_110_detector: MemoryPart
ENTITY memory_part ISPORT( d0_in, d1_in, clk: IN BIT; q0_out, q1_out: OUT BIT );
END memory_part;--ARCHITECTURE structural OF memory_part IS
COMPONENT mPORT( d, clk: IN BIT; q: OUT BIT );
END COMPONENT;FOR dff0, dff1: m USE ENTITY WORK.dff( dataflow );
BEGINdff0: m PORT MAP( d0_in, clk, q0_out );dff1: m PORT MAP( d1_in, clk, q1_out );
END structural;
Moore_110_detector: Complete Wiring
ARCHITECTURE structural OF moore_110_detector ISCOMPONENT l
PORT(x, q0_in, q1_in: IN BIT; d0_out, d1_out, z_out: OUT BIT );END COMPONENT;FOR lpart: l USE ENTITY WORK.logical_part( structural );COMPONENT m
PORT(d0_in, d1_in, clk: IN BIT; q0_out, q1_out: OUT BIT );END COMPONENT;FOR mpart: m USE ENTITY WORK.memory_part( structural );SIGNAL conn0, conn1, conn2, conn3: BIT;
BEGINlpart: l PORT MAP(x, conn0, conn1, conn2, conn3, z);mpart: m PORT MAP( conn2, conn3, clk, conn0, conn1);
END structural;
Moore_110_detector: Testbench
ENTITY Moore_test IS END Moore_test;--ARCHITECTURE input_output OF moore_test IS
COMPONENT comp1 PORT(x, clk: IN BIT; z: OUT BIT );END COMPONENT;FOR c1: comp1 USE ENTITY WORK. moore_110_detector(behavioral);FOR c2: comp1 USE ENTITY WORK. moore_110_detector(structural);SIGNAL x_in, clock, z_beh, z_struct, compare_out: BIT;
BEGINx_in <= ‘0’, ‘1’ AFTER 500 NS,
‘0’ AFTER 900 NS, ‘1’ AFTER 1100 NS,‘0’ AFTER 1300 NS, ‘1’ AFTER 1500 NS,‘0’ AFTER 1900 NS, ‘1’ AFTER 2100 NS,‘0’ AFTER 2300 NS, ‘1’ AFTER 2500 NS,
clock <= NOT clock AFTER 100 NS WHEN NOW < 3000 NS ELSE clock;c1: comp1 PORT MAP( x_in, clock, z_beh );c2: comp1 PORT MAP( x_in, clock, z_struct );compare_out <= z_beh XOR z_struct;
END input_output;
Testbench
Test may be done for various purposesVerify the designCheck the delaysFind maximum clock speedCompare behavioral & dataflowA testbench can instantiate two versions of a componentXOR gates can be used to flag discrepancies
Summary
VHDL is a standard language for describing hardware at diferent levels: behavioral or structural.Usually, VHDL source code is translated to an intermmediate code.Library support must be provided with any VHDL tool.An entity and architectural module must be constructed for each blockTestbench can be realized by constructing test modules
