22
2015 Applied Electronics Engineering Free tutorials and much more VHDL TUTORIAL WITH ACTIVE [ HDL VHDL SOFTWARE] A tutorial showing multiple ways to design multiplexers and encoders using Aldec Software

VHDL tutorial using Aldec VHDL software

  • Upload
    suma

  • View
    287

  • Download
    10

Embed Size (px)

DESCRIPTION

A vhdl tutorial on how to use Aldec VHDL software for design of multiplexer and encoders and much more

Citation preview

  • 2015

    Applied Electronics Engineering Free tutorials and much more

    VHDL TUTORIAL WITH ACTIVE [HDL VHDL SOFTWARE ]A tutorial showing multiple ways to design multiplexers and encoders using Aldec Software

  • For more tutorials visit: http://appliedelectronicsengineering.blogspot.com

    Multiplexer design using dataflow modelling style in VHDL

    In the circuit design using VHDL, one can model the circuit or system in behavioral or dataflow or

    structural model. This tutorial shows you how a mutiplexer can be designed using the dataflow style of

    modelling.

    A multiplexer has many inputs and fewer outputs. Consider two inputs a and b and one output z. An

    additional input in the multiplexer is the selector input. For two inputs we have one bit selector which can

    be 0 or 1. If selector bit sel is 0 then we have a as output and if the selector bit sel is 0 then we have b as

    output.

    From the truth table we can write the output y of the 2x1 mux as,

    \[y = sel'.a+ sel.b\]

    Now this form can be directly implemented in vhdl using the logical operators. The VHDL code illustrates

    this simple mux dataflow model.

    library ieee;

    use ieee.std_logic_1164.all;

    entity mux2x1 is

    port(

    a,b : in std_logic;

    y : out std_logic;

    sel: in std_logic

  • );

    end mux2x1;

    architecture dataflow of mux2x1 is

    begin

    y

  • The following is the VHDL code for the 4x2 multiplexer using dataflow style of modelling.

    library ieee;

    use ieee.std_logic_1164.all;

    entity mux2x1 is

    port(

    a,b,c,d : in std_logic;

    y : out std_logic;

    s0,s1: in std_logic

    );

    end mux2x1;

    architecture dataflow of mux2x1 is

    begin

    y

  • octal to binary encoder VHDL design

    Posted: 15 Feb 2015 10:44 PM PST

    This VHDL tutorial shows how to model a octal to binary encoder in VHDL and simulation using VHDL

    software. The octal to binary encoder is a 8 input 3 output encoder. There are multiple ways we can

    implement the octal to binary encoder. First we can choose the level of abstraction- behavioral, dataflow

    or structural. Second we can choose whether to use concurrent or sequential assignment statement if we

    choose behavioral modelling. Furthermore we can have the ports declared as individual pin or a vector.

    In this tutorial we use behavioral modelling and use concurrent and sequential statement to design the

    encoder. Also individual pins are used instead of vectored inputs and outputs.

    The truth table of a octal to binary encoder is below,

    One way to model the octal to binary encoder is to choose individual pins for input and output as shown

    below,

  • This encoder can be implemented using the when-else concurrent signal assignment as follows,

    library ieee;

    use ieee.std_logic_1164.all;

    entity encoder8x3 is

    port(

    x0,x1,x2,x3,x4,x5,x6,x7 : in std_logic;

    y0,y1,y2 : out std_logic

    );

    end encoder8x3;

    architecture when_else of encoder8x3 is

    signal y : std_logic_vector(2 downto 0);

    begin

    y

  • y0

  • "100" when "00001000",

    "101" when "00000100",

    "110" when "00000010",

    "111" when "00000001",

    "ZZZ" when others;

    y0

  • elsif (x0&x1&x2&x3&x4&x5&x6&x7 = "00000100") then y
  • Furthermore, in vhdl the port can be made as individual ports and as bit vectors.

    The following shows the first kind of decoder which has individual pins/port as input and bit vector as

    output.

    This kind of decoder has VHDL code with when-else statement as follows,

    library ieee;

    use ieee.std_logic_1164.all;

    entity decoder2x4 is

    port(

    a,b: in std_logic;

    y: out std_logic_vector(3 downto 0)

    );

    end decoder2x4;

    architecture when_else of decoder2x4 is

    begin

    y

  • The 2 to 4 decoder in vhdl using concurrent with-select-when assignment is below,

    library ieee;

    use ieee.std_logic_1164.all;

    entity decoder2x4 is

    port(

    a,b: in std_logic;

    y: out std_logic_vector(3 downto 0)

    );

    end decoder2x4;

    architecture with_select_when of decoder2x4 is

    signal sel : std_logic_vector(1 downto 0);

    begin

    sel

  • entity decoder2x4 is

    port(

    a,b: in std_logic;

    y: out std_logic_vector(3 downto 0)

    );

    end decoder2x4;

    architecture if_elsif_else of decoder2x4 is

    begin

    process(a,b)

    begin

    if (a&b="00") then y

  • process(a,b)

    begin

    case a&b is

    when "00" => y y y y

  • port(

    a,b: in std_logic;

    y0,y1,y2,y3: out std_logic

    );

    end decoder2x4;

    architecture when_else of decoder2x4 is

    signal y : std_logic_vector(3 downto 0);

    begin

    y

  • y0,y1,y2,y3: out std_logic

    );

    end decoder2x4;

    architecture with_select_when of decoder2x4 is

    signal sel : std_logic_vector(1 downto 0);

    signal y : std_logic_vector(3 downto 0);

    begin

    sel

  • process(a,b)

    begin

    if (a&b="00") then ytemp

  • when "11" => ytemp
  • use ieee.std_logic_1164.all;

    entity decoder2x4 is

    port(

    a,b: in std_logic;

    y0,y1,y2,y3: out std_logic;

    en : in std_logic

    );

    end decoder2x4;

    architecture when_else of decoder2x4 is

    signal y : std_logic_vector(3 downto 0);

    begin

    y

  • use ieee.std_logic_1164.all;

    entity decoder2x4 is

    port(

    a,b: in std_logic;

    y0,y1,y2,y3: out std_logic;

    en : in std_logic

    );

    end decoder2x4;

    architecture with_select_when of decoder2x4 is

    signal sel : std_logic_vector(2 downto 0);

    signal y : std_logic_vector(3 downto 0);

    begin

    sel

  • Using if sequential statements,

    library ieee;

    use ieee.std_logic_1164.all;

    entity decoder2x4 is

    port(

    a,b: in std_logic;

    y0,y1,y2,y3: out std_logic;

    en : in std_logic

    );

    end decoder2x4;

    architecture if_elsif_else of decoder2x4 is

    signal ytemp : std_logic_vector(3 downto 0);

    begin

    process(a,b,en)

    begin

    if (en = '1') then

    if (a&b="00") then ytemp

  • And using case sequential statement,

    library ieee;

    use ieee.std_logic_1164.all;

    entity decoder2x4 is

    port(

    a,b: in std_logic;

    y0,y1,y2,y3: out std_logic;

    en : in std_logic

    );

    end decoder2x4;

    architecture case_when of decoder2x4 is

    signal ytemp : std_logic_vector(3 downto 0);

    begin

    process(a,b)

    begin

    case a&b&en is

    when "001" => ytemp ytemp ytemp ytemp ytemp

  • end case_when;

    This article explained how a decoder can be designed in vhdl using concurrent and sequential statement.

    For more tutorials visit: http://appliedelectronicsengineering.blogspot.com