CSET 4650 CSET 4650 Field Programmable Logic DevicesField Programmable Logic Devices

Dan SolarekDan SolarekDan SolarekDan Solarek

Introduction to VHDLIntroduction to VHDLAn Overview / ReviewAn Overview / Review

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What is VHDL?What is VHDL?

VHDL = VHDL = VVHSIC HSIC HHardware ardware DDescription escription LLanguageanguage

where VHSIC = where VHSIC = Very High Speed Integrated CircuitVery High Speed Integrated Circuit

A technology independent, standard language for: A technology independent, standard language for: hardware description hardware description

simulation simulation

synthesissynthesis

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What is VHDL?What is VHDL?

VHDL is a programming language that has been VHDL is a programming language that has been designed and optimized for describing the behavior of designed and optimized for describing the behavior of digital systems. digital systems.

Syntax is similar to C (actually, more like Ada)Syntax is similar to C (actually, more like Ada)

It is highly typed – It is highly typed – includes a rich set of data typesincludes a rich set of data types

Allows concurrent processingAllows concurrent processing

Not a general purpose programming languageNot a general purpose programming language

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History of VHDL DevelopmentHistory of VHDL Development

Outgrowth of the DARPA VHSIC ProgramOutgrowth of the DARPA VHSIC ProgramVendors designing large chips needed to exchange Vendors designing large chips needed to exchange data describing their designsdata describing their designsIBM, Texas Instruments, and Intermetrics got the IBM, Texas Instruments, and Intermetrics got the contract in 1983 and released VHDL 7.2 in 1985contract in 1983 and released VHDL 7.2 in 1985Released to the IEEE for standardization in 1986Released to the IEEE for standardization in 1986Became IEEE Std 1076-1987Became IEEE Std 1076-1987Reballoted/upgraded to IEEE Std 1076-1993Reballoted/upgraded to IEEE Std 1076-1993Released IEEE Std 1164-1993, STD_LOGIC_1164 Released IEEE Std 1164-1993, STD_LOGIC_1164

9-valued logic definition, math functions for std_logic9-valued logic definition, math functions for std_logic

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Why VHDL?Why VHDL?

It is a Standard It is a Standard Data Exchange medium between VendorsData Exchange medium between VendorsCommunications medium between CAD ToolsCommunications medium between CAD ToolsNot Proprietary Not Proprietary Promotes interoperability and design re-usePromotes interoperability and design re-use

Not technology-specificNot technology-specificHuman-ReadableHuman-ReadableCan be used to describe the behavior of a design, or to Can be used to describe the behavior of a design, or to synthesize the design itselfsynthesize the design itselfSupports a wide range of abstraction levels Supports a wide range of abstraction levels

Can model a system, board, chip, register-transfer-level (RTL), or Can model a system, board, chip, register-transfer-level (RTL), or gate level designsgate level designs

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VHDL FeaturesVHDL FeaturesSupports HierarchySupports Hierarchy

Flexible design methodology: Top-down, bottom-up, or bothFlexible design methodology: Top-down, bottom-up, or both

Has elements to make large-scale design easierHas elements to make large-scale design easiere.g., components, functions, procedures, packages, configuratione.g., components, functions, procedures, packages, configuration

Supports three types of Supports three types of modeling styles:BehavioralBehavioral (sequential statement model [like a program]) (sequential statement model [like a program])DataflowDataflow (concurrent statement modeling) (concurrent statement modeling)StructuralStructural (for connecting components) (for connecting components)

Test Benches can be written in the same languageTest Benches can be written in the same languagecircuits can be verified by simulation before synthesiscircuits can be verified by simulation before synthesis

Propagation delays, min-max delays, setup and hold timing, Propagation delays, min-max delays, setup and hold timing, timing constraints, etc. can all be described naturallytiming constraints, etc. can all be described naturally

or mixedor mixed

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Basic Hardware Design Flow

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VHDL Design FlowVHDL Design Flow

1. Hierarchical / block diagram Figuring out the basic approach and building blocks at the block-diagram level.

Large logic designs are usually hierarchical, and VHDL gives you a good framework for defining modules and their interfaces and filling in the details later.

2. Coding Actual writing of VHDL code for modules, their interfaces, and their internal details.

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Design FlowDesign Flow

3. Compilation Analyses your code for syntax errors and checks it for compatibility with other modules on which it relies. Compilation also creates the internal information that is needed for simulation.

4. Simulation A VHDL simulator allows you to define and apply inputs to your design, and to observe its outputs. Simulation is part of a larger step called verification. A functional verification is performed to verify that the circuit’s logical operation works as desired independent of timing considerations and gate delays.

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Design FlowDesign Flow

5. Synthesis Converting the VHDL description into a set of primitives or components that can be assembled in the target technology. For example, with PLDs or CPLDs, the synthesis tool may generate two-level sum-of products equations. With ASICs, it may generate a netlist that specifies how the gates should be interconnected.

6. Fitting / Placement & Routing Maps the synthesized components onto physical devices.

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Design FlowDesign Flow

7. Timing verification At this stage, the actual circuit delays due to wire lengths, electrical loading, and other factors are known, so precise timing simulation can be performed. Study the circuit’s operation including estimated delays, and verify that the setup, hold, and other timing requirements for sequential devices (like flip-flops) are met.

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Elements of VHDLElements of VHDL

Syntax (the rules)Syntax (the rules)

Five design units (or elements)Five design units (or elements)

Identifiers (naming constraints)Identifiers (naming constraints)

Data objects (what you name)Data objects (what you name)

Data types (enumerated, integer, arrays, etc.)Data types (enumerated, integer, arrays, etc.)

ExamplesExamples

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VHDL Provides Five Design UnitsVHDL Provides Five Design UnitsEntity DeclarationEntity Declaration

Specifies the Specifies the NAMENAME and lists the interface and lists the interface PORTSPORTS

Architecture BodyArchitecture BodyModels the actual circuit “guts” within an entityModels the actual circuit “guts” within an entity

Configuration DeclarationConfiguration DeclarationIdentifies which arch. should be used with an entityIdentifies which arch. should be used with an entitySpecifies location of components used within arch.Specifies location of components used within arch.

Package Declaration – Package Declaration – like a header file in Clike a header file in C

Package Body – Package Body – like an implementation file in Clike an implementation file in C

PackagesPackages are libraries containing type definitions, overloaded are libraries containing type definitions, overloaded operators, components, functions, and procedures. They have a operators, components, functions, and procedures. They have a “declarative” section and a BODY section. Elements of a Package “declarative” section and a BODY section. Elements of a Package can be used by many entities in a design, or many designs.can be used by many entities in a design, or many designs.

Our initial examples will focus on the first three design units.

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VHDL Identifiers (Names)VHDL Identifiers (Names)Basic identifierBasic identifier

starts with a letterstarts with a letter

made up of letters, numbers, and underscore “_” charactermade up of letters, numbers, and underscore “_” character

cannot end with an underscorecannot end with an underscore

case-insensitive: case-insensitive: MY_Signal_NameMY_Signal_Name = = my_signal_namemy_signal_name

Extended IdentifierExtended Identifierany text within 2 backslashesany text within 2 backslashes

e.g., e.g., \2FOR$\ \-23signal\\2FOR$\ \-23signal\ etc. etc.

case is significant: case is significant: \COUNT\\COUNT\ not equal to not equal to \count\\count\, and, and\FRAMUS\\FRAMUS\ not equal to basic identifier not equal to basic identifier FRAMUSFRAMUS

Not often used – Not often used – not necessarily supported in synthesis !!not necessarily supported in synthesis !!

not recommended

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Four Classes of Data ObjectsFour Classes of Data ObjectsConstantConstant

Holds a single value of a given type – cannot change.Holds a single value of a given type – cannot change.

VariableVariableHolds a single value of a given type.Holds a single value of a given type.New value of same type can be “assigned” – (instantly)New value of same type can be “assigned” – (instantly)

SignalSignalHolds a LIST of values of a given type.Holds a LIST of values of a given type.Present value + a set of possible future valuesPresent value + a set of possible future valuesNew values can be assigned New values can be assigned at some future time – not now!at some future time – not now!Signals have ATTRIBUTES: [signal’attribute]Signals have ATTRIBUTES: [signal’attribute]

FileFileContains a sequence of values of one or more types.Contains a sequence of values of one or more types.Usually read or written to using proceduresUsually read or written to using proceduresFor simulation – not synthesisFor simulation – not synthesis

analogous to a “wire”analogous to a “wire”

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Data TypesData TypesScalar TypesScalar Types

Enumerated : a list of valuesEnumerated : a list of valuesIntegerIntegerFloating PointFloating PointPhysical : with units, for physical quantitiesPhysical : with units, for physical quantities

Composite TypesComposite TypesArray (all of same type)Array (all of same type)Record (can be different types)Record (can be different types)

Access TypeAccess TypeFile TypeFile Type

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Enumerated TypesEnumerated Types

CHARACTER – CHARACTER – one of the ASCII setone of the ASCII set

BOOLEANBOOLEAN – can be FALSE or TRUE – can be FALSE or TRUE

BITBIT – can be ‘0’ or ‘1’ (note single quotes) – can be ‘0’ or ‘1’ (note single quotes)

STD_LOGICSTD_LOGICHas NINE legal values:Has NINE legal values:

‘‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘-’U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘-’

Example DeclarationsExample DeclarationsTypeType CAR_STATE CAR_STATE isis (back, stop, slow, medium, fast); (back, stop, slow, medium, fast);

SubtypeSubtype GO_KART GO_KART isis CAR_STATE CAR_STATE rangerange stop to medium; stop to medium;

TypeType DIGIT DIGIT isis (‘0’, ‘1’, ‘2’, ‘3’, ‘4’, ‘5’, ‘6’, ‘7’, ‘8’, ‘9’ ); (‘0’, ‘1’, ‘2’, ‘3’, ‘4’, ‘5’, ‘6’, ‘7’, ‘8’, ‘9’ );

IEEE std_logic_1164 packageIEEE std_logic_1164 package

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IntegersIntegersAll implementations support 32-bit integers, All implementations support 32-bit integers, with a range of values from –(2with a range of values from –(23131 – 1) to – 1) to +(2+(23131 – 1) – 1)Integer data types with a smaller rage can be Integer data types with a smaller rage can be defined to save hardware (no sense forcing a defined to save hardware (no sense forcing a 32-bit counter when you need a 4-bit counter)32-bit counter when you need a 4-bit counter)Examples of legal integersExamples of legal integers

56349 6E2 0 98_71_2856349 6E2 0 98_71_28(Underscores can be thrown in anywhere, and (Underscores can be thrown in anywhere, and don’t change the value of the number.)don’t change the value of the number.)

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IntegersIntegers

Type DeclarationsType DeclarationsType INDEX is range 0 to 15;Type INDEX is range 0 to 15;

Type WORD_LENGTH is range 31 downto 0;Type WORD_LENGTH is range 31 downto 0;

Subtype DATA_WORD is WORD_LENTH range 15 Subtype DATA_WORD is WORD_LENTH range 15 downto 0;downto 0;

Object DeclarationsObject DeclarationsConstant MUX_ADDRESS: INDEX := 5;Constant MUX_ADDRESS: INDEX := 5;

Signal DATA_BUS: DATA_WORD;Signal DATA_BUS: DATA_WORD;

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ArraysArrays

An Array of type An Array of type BITBIT is called a is called a BIT_VECTORBIT_VECTOR

signal MYSIG : IN BIT_VECTOR( 0 to 3);

An Array of type An Array of type STD_LOGICSTD_LOGIC is called a is called a STD_LOGIC_VECTORSTD_LOGIC_VECTORsignal yourSIG : OUT BIT_VECTOR( 31 downto 0);

A A STRINGSTRING is a character array is a character arraycsonstant GREETING: STRING := “Hello!”;

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VHDL Key IdeaVHDL Key Idea

A key idea in VHDL is to define the interface of a A key idea in VHDL is to define the interface of a hardware module while hiding its internal details.hardware module while hiding its internal details.

A VHDL A VHDL entityentity is simply a declaration of a module’s inputs is simply a declaration of a module’s inputs and outputs, i.e., its external interface signals or ports.and outputs, i.e., its external interface signals or ports.

A VHDL A VHDL architecturearchitecture is a detailed description of the is a detailed description of the module’s internal structure or behavior.module’s internal structure or behavior.

entity

architectureinterface interface

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VHDL Interface - PortsVHDL Interface - Ports

You can think of the entity as a “wrapper” for the You can think of the entity as a “wrapper” for the architecturearchitecture

hiding the details of what’s inside hiding the details of what’s inside

providing “ports” to other modulesproviding “ports” to other modules

input port

entity

architecture output port...

...

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VHDL Conceptual ModelVHDL Conceptual Model

VHDL actually allows you VHDL actually allows you to define multiple to define multiple architectures for a single architectures for a single entity entity

it also provides a it also provides a configuration management configuration management facility that allows you to facility that allows you to specify which architecture specify which architecture to use during a particular to use during a particular synthesis runsynthesis run

entity

architecture 1

architecture 2

configuration

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VHDL Program FileVHDL Program File

In the text file of a VHDL program:

the entity, architecture, and configuration declarations are all separated

not nested as the previous diagram may have implied

We will use white space to set them apart

mydesign.vhd

entity

architecture

configuration

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Entity DeclarationEntity Declaration

Specifies the name of the entitySpecifies the name of the entity

Lists the set of interface PORTSLists the set of interface PORTS

PORTSPORTS are SIGNALS are SIGNALS that enter or leave the entity that enter or leave the entity

This is the “black box,” or block diagram view This is the “black box,” or block diagram view

Half-AdderA

B

SUM

CARRY

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Entity DeclarationEntity Declaration

entity half_adder is port( A, B : in BIT; SUM, CARRY : out BIT);end half_adder;

entity half_adder is port( A, B : in BIT; SUM : out BIT; CARRY : out BIT );end entity half_adder;

no “;” after last signal

end of port statement

NAME

MODE

TYPE

optional words, but recommended

White space is ignored

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Entity DeclarationEntity Declaration

entity half_adder is port( A, B : in BIT; SUM, CARRY : out std_logic);end half_adder;

entity half_adder is port( A, B : in std_logic; SUM : out std_logic; CARRY : out std_logic );end entity half_adder;

Using IEEE 1164 standard signals and data types:

TYPE

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VHDL Signal ModesVHDL Signal Modes

inin – means means input-ONLY, input-ONLY, you cannot use a you cannot use a mode mode inin signal on the signal on the LEFTLEFT side of an equation (that is, you can’t side of an equation (that is, you can’t assign a new value to inputs)assign a new value to inputs)outout – means means output-ONLY, output-ONLY, you cannot use a you cannot use a mode mode outout signal on the signal on the RIGHTRIGHT side of an equation (that is, you side of an equation (that is, you can’t “use” the outputs)can’t “use” the outputs)inoutinout – means means bi-directional, bi-directional, like a three-state bus, for like a three-state bus, for example. example. This mode is typically used for three-state input/output pins on PLDsbuffer – means the signal is an output of the entity, and its value can also be read inside the entity’s architecture

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Example: LogicFcnExample: LogicFcn

entity architecture

A

B

C Y

ports

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Entity Declaration for LogicFcnEntity Declaration for LogicFcn

library IEEE;

use IEEE.std_logic_1164.all;

 

entity LogicFcn is

port (

A: in std_logic;

B: in std_logic;

C: in std_logic;

Y: out std_logic

);

end entity LogicFcn;

 

ABC

Y

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Architecture BodyArchitecture Body

Specifies the internal circuitry of an entity, using any Specifies the internal circuitry of an entity, using any one of the following modeling styles:one of the following modeling styles:

1.1. As a set of interconnected components, as wired As a set of interconnected components, as wired (called (called structuralstructural modeling) modeling)

2.2. As a set of concurrent signal assignment As a set of concurrent signal assignment statements (called statements (called dataflowdataflow modeling) modeling)

3.3. As a set of sequential assignment statements, As a set of sequential assignment statements, i.e., a “process” (called i.e., a “process” (called behavioralbehavioral modeling) modeling)

4.4. As any combination of the above (called As any combination of the above (called mixedmixed modeling)modeling)

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Parts of Architecture BodyParts of Architecture Body

architecture ARCH_NAME of ENTITY_NAME is

<declarative section : list internal signals, variables, and components here. For each component used show the port map, (unless port map defined is in a “package”) >

begin

<statement section : all concurrent statements and components and processes in this section execute at the same time, NOT sequentially>

end ARCH_NAME;

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Architecture Body (Dataflow)Architecture Body (Dataflow)

 

architecture dataflow of LogicFcn is

begin

Y <= (not A and not B) or C;

end dataflow;

With a signal assignment statement:

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Architecture Body (Dataflow)Architecture Body (Dataflow)

 

architecture dataflow of LogicFcn is

begin

Y <= '1' when (A = '0' AND B = '0') OR

(C = '1')

else '0';

end dataflow;

With a conditional signal assignment statement:

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Architecture Body (Behavioral)Architecture Body (Behavioral)architecture behavioral of LogicFcn is

begin

fcn: process (A,B,C)

begin

wait on A,B,C;

if (A = '0' and B = '0') then

Y <= '1';

elsif C = '1' then

Y <= '1';

else

Y <= '0';

end if;

end process;

end behavioral;

“Label:”Name of process

Sensitivity List - The Process will be executed anytime there is an EVENT (change of state) on one of these signals.

WAIT ON statement - has same effect as sensitivity list. CANNOT USE BOTH. Processes with WAIT statements cannot have sensitivity lists !!

Statements within Processes are executed sequentially. (This is a single IF statement)The process, however, executes concurrently with other processes and concurrent statements in the architecture.

process

Values are assigned to signals when process suspends

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Architecture Body (Structural)Architecture Body (Structural)

A

B

C Y

entity architecture

Internal signals are LOCAL to the Architecture, and Internal signals are LOCAL to the Architecture, and cannot cannot be seen outside itbe seen outside it ! !

notA

notB

andSignal

signals

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Architecture Body (Structural)Architecture Body (Structural)architecture structural of LogicFcn is

signal notA, notB, andSignal: std_logic;

begin

i1: inverter port map (i => A,

o => notA);

i2: inverter port map (i => B,

o => notB);

a1: and2 port map (i1 => notA,

i2 => notB,

y => andSignal);

o1: or2 port map (i1 => andSignal,

i2 => C,

y => Y);

end structural;

LOCAL SIGNALS are declared within the architecture and they have no MODE (IN, OUT, etc.)

COMPONENT declarations may go here

These are COMPONENT INSTANTIATIONS

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Components for Structural ModelComponents for Structural Modellibrary IEEE;

use IEEE.std_logic_1164.all;

package primitive is

component AND2 port (

i1: in std_logic;

i2: in std_logic;

y: out std_logic

);

end component; 

component OR2 port (

i1: in std_logic;

i2: in std_logic;

y: out std_logic

);

end component;

component INVERTER port (

i: in std_logic;

o: out std_logic

);

end component;

end primitive;

these are component declarations