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11/27/2010
1
Dr. Ahmed H. Madian-VLSI
Very Large Scale Integration (VLSI)
Dr. Ahmed H. [email protected]
Lecture 7
Dr. Ahmed H. Madian-VLSI
Content
Revision on Dynamic logic
Dynamic CVSL
Clock strategies Single-phase
Pulse mode
Edge mode
2-phase clock strategy
4-phase clock strategy
Clock skew solution
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Dr. Ahmed H. Madian-VLSI
Why dynamic circuits?
Ratioed logic reduce the input capacitance by replacing the pMOS transistors connected to the inputs with a single resistive pull-up.
The draw back that statice power dissipation, slow rising transition and a non-zero VOL.
Dynamic circuit solved this problems by using a clocked pull-up and foot transistors rather than a pMOS that is always ON.
Dr. Ahmed H. Madian-VLSI
Why dynamic circuits? (cont.)
Dynamic circuit is divided into two modes Pre-charge
The clock is low „L‟ so the pMOS is ON and initialize the output high.
EvaluateThe clock is „H‟ and the pMOS is OFF
Dynamic circuits are the fastest commonly used circuit family because they have lower input capacitance, no connection during switching and no static power dissipation.
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Dr. Ahmed H. Madian-VLSI
Input can make only single H-to-L transition during the evaluate phase
Dr. Ahmed H. Madian-VLSI
Domino logic cascading
AX
Y
Precharge Evaluate
X
Precharge
A = 1
Y should rise but cannot
Y
X monotonically falls during evaluation
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Dr. Ahmed H. Madian-VLSI
Dr. Ahmed H. Madian-VLSI
Dynamic Cascade voltage switch logic (CVSL)
Domino only performs noninverting functions:
AND, OR but not NAND, NOR, or XOR
Dynamic CVSL solve this problem
Y
f
inputs
Y
f
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Dr. Ahmed H. Madian-VLSI
Dynamic CVSL
Example: AND/NAND
Y_h
f
inputs
Y_l
f
Dr. Ahmed H. Madian-VLSI
Dynamic CVSL
Y
Y
A
B
= A xor B
B
AAA= A xnor B
Sometimes it‟s possible to share transistors
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Dr. Ahmed H. Madian-VLSI
Charge Sharing
Dynamic gates suffer from charge sharing
B = 0
A
Y
x
Cx
CY
A
x
Y
Charge sharing noise
Yx Y DD
x Y
CV V V
C C
Dr. Ahmed H. Madian-VLSI
Secondary pre-charge transistor
Extra transistor added for pre-charge internal nodes.
Rule of thumb is to pre-charge every other level of the N-tree.
Extra pre-charge transistor added more diffusion capacitance with N-tree slowing performance
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Dr. Ahmed H. Madian-VLSI
CLA using Multi-Out Domino Logic
Dr. Ahmed H. Madian-VLSI
Leakage
Dynamic node floats high during evaluation
Transistors are leaky (IOFF 0)
Dynamic value will leak away over time
Use keeper to hold dynamic node
Must be weak enough not to fight evaluation
A
H
2
2
1 kX
Y
weak keeper
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Dr. Ahmed H. Madian-VLSI
Charge sharing in Dynamic CVSL
The cross-coupled pfets serve as “keepers”
both keepers are off; during the evaluate phase, the output that goes low switches on the keeper for the output that is staying high. Really solves capacitive coupling problems with dynamic logic.
Dr. Ahmed H. Madian-VLSI
Split keepers
Keeper gate load now reduced on gate output
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Dr. Ahmed H. Madian-VLSI
Self resetting domino
f
A
Y
Time
chainreset
reset
A
Y
reset
Dr. Ahmed H. Madian-VLSI
Domino Summary
Domino logic is attractive for high-speed circuits
1.5 – 2x faster than static CMOS
But many challenges:
Monotonicity
Leakage
Charge sharing
Noise
Widely used in high-performance microprocessors
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Dr. Ahmed H. Madian-VLSI
Clocking strategy Choosing the right clocking scheme affects the
functionality, speed, and power of a circuit
Two phase clocking + robust and conceptually simple
- need to generate and route two clock signals
- have to design to accommodate possible skew between the
Single phase clocking (Pulse mode clocking& Edge
triggered clocking)
+ only need to generate and route one clock signal
+ supported by most automated design methodologies
+ don’t have to worry about skew between the two clocks
- have to have guaranteed slopes on the clock edges
Latch timing parameter
Dr. Ahmed H. Madian-VLSI
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Flip-flop timing parameter
Dr. Ahmed H. Madian-VLSI
Pulse Latch system (pulsed Latches) with Static CMOS
Dr. Ahmed H. Madian-VLSI
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Dr. Ahmed H. Madian-VLSI
Edge DFF system with static CMOS
Single-phase clock strategy Simplest clocking methodology is to use a single clock in
conjunction with a register. Clocks are generated with global clock buffers.
Used in many ASIC designs (Gate Arrays and Std Cells) Clock skew problem presents
Sources of Clock Skew and Jitter
Dr. Ahmed H. Madian-VLSI
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Dr. Ahmed H. Madian-VLSI
Clock Skew
If a clock net is heavily loaded, there might be a race between clock and data -> clock skew
Two methods to avoid clock skew:
Dr. Ahmed H. Madian-VLSI
Two phase overlapping Domino
a problem in single phase clocked systems is the generation and distribution of nearly perfect overlapping clocks.
in two-phase clocked systems this is solved by non-overlapping clocks
1
2
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Dr. Ahmed H. Madian-VLSI
Two-phase pipelined latch system with static CMOS
Using transparent latches for pipelined, the clock skew doesn‟t affect the performance
The transparent latch are skew tolerant Using alternating positive and negative dynamic latches with a single
clock gives great speed and small area, but… lots of worries about clock skew must balance logic delays to minimize wastage
Mealy and MOORE FSM
Dr. Ahmed H. Madian-VLSI
11/27/2010
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Dr. Ahmed H. Madian-VLSI
Two phase clock generation skew-tolerant
Clock choppers is used to delay the falling edge to provide the required overlap
Dr. Ahmed H. Madian-VLSI
Domino logic + FF system
Poor match as we are wasting time in doing pre-charge
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Dr. Ahmed H. Madian-VLSI
Domino logic + Latch system
Delay improved but it become like static CMOS system but we have two problems
1. The first domino gates cannot evaluate until the rising edge of the clock
2. The result must setup at latch input before the falling edge of the clock.
Dr. Ahmed H. Madian-VLSI
How to improve this?Remove Latches & FFs
Toverlap-a needs to be long enough for 1
blocks to hand off results to 2 blocks and also to hide skew.
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Clock Distribution
Dr. Ahmed H. Madian-VLSI
a Distributed clock tree paths
a Balanced H tree paths
Dr. Ahmed H. Madian-VLSI
Example: ALUUsing two-phase clock
strategy
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Dr. Ahmed H. Madian-VLSI
solution
Dr. Ahmed H. Madian-VLSI
comments on ALU design
Any net connections show going from 1 to 2
(and vice versa) must have logic on it, even if it is a buffer, to prevent shortest path problems.
ALU 2nd stage is 1 and it must drive the 1
logic blocks of the decode stage for bypass to work correctly.
The registered output of the ALU is 2 logic of the decode stage.
![> plot(cos(x) + sin(x), x=0..Pi); plot(tan(x), x=-Pi..Pi ... · > plot3d({sin(x*y), x + 2*y},x=-Pi..Pi,y=-Pi..Pi); ↵ c1:= [cos(x)-2*cos(0.4*y),sin(x)-2*sin(0.4*y),y]: ↵ c2:= [cos(x)+2*cos(0.4*y),sin(x)+2*sin(0.4*y),y]:](https://img.pdfslide.us/doc/110x75/5e87f19cd4429b02985e2e8b/-plotcosx-sinx-x0pi-plottanx-x-pipi-plot3dsinxy.jpg)
