UG119 Virtex-II Pro Memory Board Toolkit€¦ · Memory Board, which connects a Virtex-II Pro FPGA to Quad Data Rate (QDR) memories. Guide Contents This manual contains the following

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ML365 Virtex-II Pro QDR II SRAM (200 MHz)Memory Board User Guide

UG066 (v1.0) June 29, 2004

Product Not Recommended for New Designs

ML365 Virtex-II Pro QDR II SRAM Mem. Board www.xilinx.com UG066 (v1.0) June 29, 20041-800-255-7778

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ML365 Virtex-II Pro QDR II SRAM Memory Board User Guide UG066 (v1.0) June 29, 2004)

The following table shows the revision history for this document.

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Version Revision

06/29/04 1.0 Initial Xilinx Release


ML365 Virtex-II Pro QDR II SRAM Mem. Board www.xilinx.com 3UG066 (v1.0) June 29, 2004 1-800-255-7778

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Preface

About This Guide

This document describes the design of the ML365 Virtex-II Pro™ QDR II SRAM (200 MHz) Memory Board, which connects a Virtex-II Pro FPGA to Quad Data Rate (QDR) memories.

Guide ContentsThis manual contains the following chapters:

• Chapter 1, “Introduction,” describes the purpose of the ML365 board and provides its key features.

• Chapter 2, “Architecture,” provides a block diagram of the memory board and describes the key components.

• Chapter 3, “Electrical Requirements,” lists the electrical specifications for the memory board.

• Chapter 4, “Signal Integrity Recommendations and Simulations,” provides information on termination, transmission lines, and duty cycles. It also gives the results of several IBIS simulations.

• Chapter 5, “Board Layout Guidelines,” provides information on decoupling capacitors, ground signals, and PCB layout.

• Appendix 1, “Related Documentation,” lists data sheet and external website references specific to the ML365 components.

• Appendix 2, “FPGA Pinout,” provides the pinout of the Virtex-II Pro FPGA.

• Appendix 3, “Memory Board Schematics and Characterization Results” shows the schematics for the board.

Additional ResourcesFor additional information, go to http://support.xilinx.com. The following table lists some of the resources you can access from this website. You can also directly access these resources using the provided URLs.

Resource Description/URL

Tutorials Tutorials covering Xilinx design flows, from design entry to verification and debugging:

http://support.xilinx.com/support/techsup/tutorials/index.htm

Answer Browser Database of Xilinx solution records:

http://support.xilinx.com/xlnx/xil_ans_browser.jsp


http://support.xilinx.com

http://support.xilinx.com/support/techsup/tutorials/index.htm

http://www.support.xilinx.com/xlnx/xil_ans_browser.jsp


ConventionsThis document uses the following conventions. An example illustrates each convention.

TypographicalThe following typographical conventions are used in this document:

Online DocumentThe following conventions are used in this document:

Application Notes Descriptions of device-specific design techniques and approaches:

http://support.xilinx.com/apps/appsweb.htm

Data Sheets Device-specific information on Xilinx device characteristics, including readback, boundary scan, configuration, length count, and debugging:

http://support.xilinx.com/xlnx/xweb/xil_publications_index.jsp

Problem Solvers Interactive tools that allow you to troubleshoot your design issues:

http://support.xilinx.com/support/troubleshoot/psolvers.htm

Tech Tips Latest news, design tips, and patch information for the Xilinx design environment:

http://www.support.xilinx.com/xlnx/xil_tt_home.jsp

Resource Description/URL

Convention Meaning or Use Example

Italic font

References to other manualsSee the Development System Reference Guide for more information.

Emphasis in textIf a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected.

Convention Meaning or Use Example

Blue textCross-reference link to a location in the current document

See the section “Additional Resources” for details.

Refer to “Title Formats” in Chapter 1 for details.

Blue, underlined text Hyperlink to a website (URL) Go to http://www.xilinx.com for the latest speed files.


http://www.support.xilinx.com/support/troubleshoot/psolvers.htm

http://support.xilinx.com/apps/appsweb.htm

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Preface: About This GuideGuide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Typographical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Schedule of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Schedule of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chapter 1: IntroductionOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Chapter 2: ArchitectureML365 Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Block Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

QDR II SRAM (U5, Banks 6 and 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14QDR II SRAM (U11, Banks 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14QDR II SRAM (U12, Banks 0 and 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

RS232 (J5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

200 MHz LVPECL Clock (Y1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14250 MHz LVPECL Clock (Y2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14SMA Clock Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

User I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15GPIO (P19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15DIP Switch (SW3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Push Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Rotary Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Power On or Off Slide Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Jumper Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Grounded I/Os. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Liquid Crystal Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Write Cycle for the LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Display Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233.3 V Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table of Contents


6 www.xilinx.com ML365 Virtex-II Pro QDR II SRAM Mem. Board1-800-255-7778 UG066 (v1.0) June 29, 2004

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2.5 V Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231.8 V Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231.5 V Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

FPGA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Selecting the Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Serial Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Master Serial Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Slave Serial Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

SystemAce Configuration (Default Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25SelectMap Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25JTAG Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Chapter 3: Electrical RequirementsPower Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29FPGA Internal Power Budget . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Chapter 4: Signal Integrity Recommendations and SimulationsTermination and Transmission Line Summaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Terminations and Transmission Lines for QDR Components . . . . . . . . . . . . . . . . 34

Data and Clock Signals (D, Q, CQ, CQ, and CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Address and Control Signals (A, R, W, BW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

IBIS Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Notes on the Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Data Signal Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Data Signals from the FPGA to the Memory (HSTL_18_C2 at FPGA) . . . . . . . . . . . . 37Data Signals from the QDR II SRAM, Component U11 to the FPGA Measured at the FPGA39Eye Diagram for the Component U11, Bit 4 Signal Measured at the FPGA . . . . . . . . 40

Clock Signal Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Typical, Slow, and Fast Cases for Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Address and Control Signal Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Typical Case Simulation at All Memory Components . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Chapter 5: Board Layout GuidelinesDecoupling Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Providing Additional Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Board Stackup Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Appendix 1: Related Documentation

Appendix 2: FPGA Pinout

Appendix 3: Memory Board Schematics and Characterization ResultsSchematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Characterization Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Long-Term Runs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104Corners Results Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104



Chapter 1: IntroductionFigure 1-1: Simplified Block Diagram of Memory Board Interface . . . . . . . . . . . . . . . . . . 11

Chapter 2: ArchitectureFigure 2-1: ML365 Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Figure 2-2: LCD Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Figure 2-3: Display Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Figure 2-4: LCD Panel Character Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Figure 2-5: SelectMap Connectors P99 and P111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Figure 2-6: SystemAce and JTAG Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Figure 2-7: JTAG I/O Connector P103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Chapter 3: Electrical Requirements

Chapter 4: Signal Integrity Recommendations and SimulationsFigure 4-1: Signal Terminations for Transmitted and Received Data . . . . . . . . . . . . . . . . 36Figure 4-2: Data Signal Bit 4 from the FPGA to the Memory (Typical Case) . . . . . . . . . . 37Figure 4-3: Eye Diagram for Data Bit 4 from the FPGA to the QDR II SRAM, U11 . . . . 38Figure 4-4: Data Signals from the QDR II SRAM U11 at the FPGA (Typical,

Slow/Weak and Fast/Strong Cases) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Figure 4-5: Eye Diagram for Data Bit 4 at the FPGA from Component U11 . . . . . . . . . . . 40Figure 4-6: Clock Signal Terminations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Figure 4-7: Clock K Signal from the FPGA to the QDR II SRAM, Component U11 . . . 42Figure 4-8: Clock CQ Signal from the FPGA to the QDR II SRAM Component U11 . . 43Figure 4-9: Address and Control Signal Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Figure 4-10: Address/Control Signals for the QDR II SRAM, Component U11, Bit 4 . . 45

Chapter 5: Board Layout GuidelinesFigure 5-1: Picture of the Top Layer of the ML365 Revision 1.0b Board . . . . . . . . . . . . . . 50Figure 5-2: Picture of the Bottom Layer of the ML365 Revision 1.0b Board . . . . . . . . . . . 51


Appendix 2: FPGA Pinout

Appendix 3: Memory Board Schematics and Characterization Results

Schedule of Figures



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Chapter 1: Introduction

Chapter 2: ArchitectureTable 2-1: GPIO Header Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Table 2-2: DIP Switch Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Table 2-3: Power-On Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Table 2-4: FPGA Configuration Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Table 2-5: SystemAce Configuration Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Table 2-6: Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Table 2-7: LCD Pin Descriptions and PFGA Connections . . . . . . . . . . . . . . . . . . . . . . . . . . 18Table 2-8: LCD Write Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Table 2-9: Instruction Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Table 2-10: Configuration Modes Supported on the QDR II SRAM Demonstration Board 24Table 2-11: Jumper Positions for SystemAce Configuration . . . . . . . . . . . . . . . . . . . . . . . . 25Table 2-12: JTAG Connector Pins (P1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Chapter 3: Electrical RequirementsTable 3-1: ML365 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Table 3-2: XC2VP20FF1152 Estimated Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . 30Table 3-3: XC2VP20FF1152 Temperature Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Table 3-4: Device Quiescent Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Table 3-5: CLB Logic Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Table 3-6: Digital Clock Manager Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Table 3-7: Input/Output Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Chapter 4: Signal Integrity Recommendations and SimulationsTable 4-1: QDR SRAM Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Chapter 5: Board Layout GuidelinesTable 5-1: Decoupling Capacitor Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Table 5-2: Suggested Stackup for a 12-layer board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49


Appendix 2: FPGA PinoutTable 2-1: FPGA Pin Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Appendix 3: Memory Board Schematics and Characterization ResultsTable 3-1: Corners Results Measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Schedule of Tables



R



R

Chapter 1

Introduction

OverviewThe ML365 Virtex-II Pro QDR II SRAM Memory Board provides a communications platform between a Virtex-II Pro FPGA and high-speed, quad data-rate (QDR) memories with operating speeds up to 200 MHz. The ML365 has three major functions:

• Test and verify the interoperability of Virtex-II Pro devices with high-speed QDR II SRAM memories

• Serve as a development platform for Xilinx and its customers to use for building memory interfaces

• Provide a means by which Xilinx can demonstrate high-speed QDR II SRAM memory interoperability

This document describes the functional blocks within the ML365. It also provides various recommendations and requirements for usage of the board, including electrical requirements, logic analyzer requirements, and signal integrity issues. Simulation results using IBIS also are included.

Figure 1-1 shows a simplified block diagram of the ML365 memory interfaces.

Figure 1-1: Simplified Block Diagram of Memory Board Interface

ug124_01_062204

QDR II SRAM1M x 36

FBGA 1654-Word Burst

QDR II SRAM1M x 36


Virtex-II Pro FPGAXC2VP20FF1152-6

QDR II SRAM1M x 36


D(36-bits)

Q(36-bits)

Addr,Ctrl

Q (36-bits)

D (36-bits)

K, K

C, C

CQ, CQ

Addr, Ctrl

Q (36-bits)

D (36-bits)

K, K

C, C

CQ, CQ

Addr, Ctrl

C,C

K,K

CQ,CQ



The ML365 demonstrates a 36-bit interface to a 36 MByte, 200 MHz QDR II SRAM component. There are three independent 36-bit interfaces on the board; one on the left side of the FPGA, the second on the right side of the FPGA, and the third on top of the FPGA.

FeaturesThe key features of the ML365 are summarized as follows:

• One Virtex-II Pro FPGA (XC2VP20FF1152)

• Three QDR II SRAM Components (Samsung K7R323684M or NEC UPD44165364F5)

♦ 18 MBytes

♦ 36-bit Data interface

• Three separate controllers for each 36-bit memory interface

• Characterized 200 MHz clock operation for interfaces A (interface to the FPGA on the right side, U5) and B (interface to the FPGA on the left side, U11)

• One additional memory interface on the top banks of the FPGA (interface C, U12)



R

Chapter 2

Architecture

This chapter provides functional descriptions of the major blocks within the ML365 board design. For additional detailed information on the design, refer to the schematics, which are located at http://www.xilinx.com/bvdocs/userguides/ug066.zip.

ML365 Board Block DiagramFigure 2-1 shows a block diagram of the ML365 board. Refer to “Block Descriptions” for additional information on the major blocks.

Figure 2-1: ML365 Board Block Diagram

ug066_c2_01_060804

FPGAReset

PROG

Mode

DIPSW

QDR II SRAM1M x 36

QDR II SRAM1M x 36

QDR II SRAM1M x 36

USER2Switch

USER1Switch

USER2LED

USER1LED

SystemAceReset

JTAGHeader

JTAGParallelPC-IVPortJTAG

Jumpers

SystemAceFile SelectRotary Switch

SYSTEM ACEControllerTQFP144

SEIKO 1X16LCD DisplayL167100J000

XC2VP20FF1152C

SelectMapHeader

Clock250 MHz

Clock200 MHz

RS-232SerialPort

GPIO Header

TPS548101.8V, 8ARegulator

PT5501N3.3V, 3ARegulator



On / OffSwitch

DC 5VInput Jack

SMA SMAXCONFIG

Header


http://www.xilinx.com/bvdocs/userguides/ug066.zip


Chapter 2: ArchitectureR

Block DescriptionsThis section describes the major blocks of the ML365 board.

FPGAThe ML365 uses a Xilinx XC2VP20FF1152C-6 Virtex-II Pro device. This device is packaged in a 1152-pin BGA package with a -6 speed grade. Refer to Appendix 2, “FPGA Pinout,”for a complete pinout of the Virtex-II Pro device.

MemoriesThe ML365 board supports three types of memories in two speed grades.

QDR II SRAM (U5, Banks 6 and 7)

The QDR II SRAM component connected to FPGA I/O banks 6 and 7 is a 165-pin, 200 MHz Samsung K7R323684M or NEC UPD44165364F5 SRAM in a Ball Grid Array package. This component has a 36-bit wide data interface.


The QDR II SRAM component connected to FPGA I/O banks 2 and 3 is a 165-pin, 200 MHz Samsung K7R323684M or NEC UPD44165364F5 SRAM. This component has a 36-bit wide data interface.


The QDR II SRAM component connected to FPGA I/O banks 0 and 1 is a 165-pin, 250 MHz Samsung K7R323684M or NEC UPD44165364F5 SRAM. This component has a 36-bit wide data interface.

RS232 (J5)The ML365 board provides an RS232 serial interface using a Maxim MAX3316ECUP device. The maximum speed of this device is 460 Kb/s. The RS232 interface is accessible through a male DB9 serial connector.

ClocksThe ML365 board has 200 MHz and 250 MHz LVPECL (2.5 V) clock oscillators on board. It also has two SMA connectors for external differential clock inputs.

200 MHz LVPECL Clock (Y1)

The LVPECL clock is an Epson EG-2121CA-200 MHz oscillator with a differential output. The oscillator runs at 200 MHz ± 100 PPM with an operating voltage of 2.5 V ± 5%. It is terminated at the FPGA with a 50 ohm resistor. FPGA pins AH17 and AJ17 in Bank 4 serve as the OSC_200M_N and OSC_200M_P inputs, respectively.

250 MHz LVPECL Clock (Y2)

The LVPECL clock is an Epson EG-2121CA-250 MHz clock oscillator with a differential output. This oscillator runs at 250 MHz ± 100 PPM with an operating voltage of 2.5 V ± 5%.



Block DescriptionsR

FPGA pins AK17 and AL17 in Bank 4 serve as the OSC_250M_N and OSC_250M_P inputs, respectively.

SMA Clock Connectors

Two SMA connectors are provided for the input of an off-board differential clock. The traces from the SMAs are run as a pair to the FPGA where they are terminated with a 50 ohm resistor. AK18 serves as the EXTCLK1_P input, and AL18 serves as the EXTCLK1_N input for the SMA connector pair.

User I/OsThis subsection describes the devices that connect to the User I/Os of the ML365 board.

GPIO (P19)

The ML365 board contains 16 General-Purpose I/Os (GPIOs) that are accessible through a 2 x 16 .100" pin header (P19). The odd-numbered pins on each header are connected to an FPGA pin, and the even-numbered pins on each header are connected to GND (refer to Table 2-1). The GPIO header pins are accessed through I/Os in Bank 0. The header pins each have a pull-down resistor of 51 ohms.

Table 2-1: GPIO Header Pins

GPIO Header Pin # FPGA I/O PinGPIO Header Pin #

Ground Connections

G1 AL13 G2

G3 AL12 G4

G5 AD16 G6

G7 AE16 G8

G9 AM14 G10

G11 AM13 G12

G13 AF16 G14

G15 AG16 G16

G17 AH15 G18

G19 AJ15 G20

G21 AD17 G22

G23 AE17 G24

G25 AH16 G26

G27 AJ16 G28

G29 AK16 G30

G31 AF17 G32




DIP Switch (SW3)

One 3-position DIP switch (SW3) is connected to the FPGA I/O as shown in Table 2-2. These switches are used to set the FPGA configuration mode pins M0, M1, and M2.

LEDs

Eleven surface-mounted blue LEDs are installed as status indicators. Refer to Table 2-3, Table 2-4, and Table 2-5.

Table 2-2: DIP Switch Connections

DIP Switch Input FPGA I/O Pin #

DIP1 AF26 (M0)

DIP2 AE26 (M1)

DIP3 AE25 (M2)

Table 2-3: Power-On Status

Status Indication FPGA I/O Pin #

5.0V on D9

2.5V on D7

3.3V on D5

1.8V on D8

1.5V on D6

Table 2-4: FPGA Configuration Status

Configuration INIT D3

Configuration DONE D4

Table 2-5: SystemAce Configuration Status

System Ace LEDsError D2

Status D1

User LEDsUSER1 AF15

USER2 AE15



Block DescriptionsR

Push Buttons

The ML365 board contains five momentary push buttons. Their functions are as follows:

• Program the FPGA

• Reset FPGA

• Reset SystemAce

• USER1

• USER2

Rotary Switch

The ML365 board contains one eight-position rotary switch used to select the SystemAce file address. One of eight configuration file images is loaded from the Compact Flash card present in the socket.

Power On or Off Slide Switch

The power on or off slide switch is a DPST slide switch used to apply 5V input power to the board.

Jumper Settings

Table 2-6 lists the jumper settings for the complete PCB.

Grounded I/Os

Unused I/Os are connected to GND in all FPGA banks. This was done to improve power dissipation and SSO ground bounce. Users must not drive any unused I/Os that are connected to GND.

Table 2-6: Jumper Settings

Pin # PurposeJumper Position

1 - 2 2 - 3

P6 QDR II U5 DLL enable DLL enable DLL bypass

P7 QDR II U5 ZQ select Minimum Z mode 0.2RQ = 50 ohm





P2 System Ace On = Disable after resetOff = Enable after reset




Liquid Crystal DisplayThe Seiko L167100J000 Liquid Crystal Display (LCD) is a 5V, 1-line X16 character display without a backlight. The LCD is connected to the PCB using two rows of 1 x 16 pin SIP headers placed 31 mm. apart. The LCD interfaces uses bank 5 of the FPGA. The LCD pin descriptions and FPGA pinouts are listed in Table 2-7.

The information needed to control the LCD panel is provided in the following figures and tables. Figure 2-2 shows the LCD write timing diagram, and Table 2-8 lists the LCD write timing parameters.

Table 2-9 shows the instruction codes for the LCD. Figure 2-3 shows the Display Initialization Sequence, and Figure 2-7, the LCD panel character set. For complete information, refer to the manufacturer’s data sheet.

Write Cycle for the LCD

Reading from the LCD panel memory is not implemented on this demonstration board.

Table 2-7: LCD Pin Descriptions and PFGA Connections

Symbol Function FPGA Pin #

VSS Power supply (GND) N/A

VDD Power supply (+5V) N/A

VO Contrast adjustment N/A

RS Register selection AF22

R/W Read / Write selection AG22

E Read / Write enable AE22

DB (0-7) Data bus AF25 (DB0), AL28, AM28, AE24, AF24, AG25, AH25, AK27 (DB7)

Figure 2-2: LCD Write Timing Diagram

RS

R / W

E

DB[7:0]

tAS

tER tEFtDSW tH

tCYCE

tAH

PWEH

ug066_c2_02_060704



Block DescriptionsR

Display Commands

Table 2-9 provides display commands or instruction code for the LCD. Refer to the Table Notes for additional information.

Table 2-8: LCD Write Timing Parameters

Item SymbolStandard

UnitMinimum Maximum

Enable cycle time tCYCE 500 ns

Enable pause width / High Level PWEH 230 ns

Enable rise and fall time tER, tEF 20 ns

Address setup time / RS, R/W - E tAS 40 ns

Address hold time tAH 10 ns

Data setup time tDSW 80 ns

Data hold time tH 10 ns

Table 2-9: Instruction Code

InstructionCode Description

(Notes 2 and 3)

MaximumExecution

Time (Note 1)

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

ClearDisplay

0 0 0 0 0 0 0 0 0 1 Clears entire display and sets Data Display RAM (DDR) address 0 in the address counter.

82 µs -1.64 ms

ReturnHome

0 0 0 0 0 0 0 0 1 * Sets DDR address 0 in the address counter. Also returns display being shifted to original position. DDR contents remain unchanged.

40 µs -1.6 ms

EntryModeSet

0 0 0 0 0 0 0 1 I/D S Sets cursor move direction and specifies shift of display. These operations are performed during data write and read.

40 µs – 1.64 ms

DisplayOn/OffControl

0 0 0 0 0 0 1 D C B Sets ON/OFF of entire display (D), cursor ON/OFF (C), and blink of cursor position character (B).

40 µs




*Not applicable

Notes:1.Maximum execution time is when fcp or fosc is 250 kHz. Execution time changes when frequency changes.2.DD RAM: Display data RAMCG RAM: Character generator RAMACG: CG RAM addressADD: DDR address - corresponds to cursor addressAC: Address counter used for both DDR and CG RAM addressI/D = 1: Increment or I/D = 0: DecrementS = 1: Display shift or S = 0: No Display shiftD = 1: Display ON or D = 0: Display OFFC = 1: Cursor ON or C = 0: Cursor OFFB = 1: Blink ON or B = 0: Blink OFFS/C = 1: Display shift or S/C = 0: Cursor moveR/L = 1: Shift to the right or R/L = 0: Shift to the leftDL = 1: 8 bits or DL = 0: 4 bitsN = 1: 2 linesF = 0: 5 x 7 dotsBF = 1: Internally operating or BF = 0: Can accept instruction

Cursor orDisplay

Shift

0 0 0 0 0 1 S/C R/L * * Moves cursor and shifts display without changing DDR contents.

40 µs

FunctionSet

0 0 0 0 1 DL N F * * Sets interface data length (DL), number of display lines (L), and character fonts (F).

40 µs

Set CG RAM Address

0 0 0 1 ACC Sets Character Generator RAM (CGR) address. CGR data is sent and received after this setting.

40 µs

Set DD RAM Address

0 0 1 ADD Sets DDR address. CGR data is sent and received after this setting.

40 µs

Read Busy Flag

and Address

0 1 BF AC Reads Busy flag (BF) indicating internal operation is being performed and reads address counter contents.

1 µs

Write Datato CG

or DDR

1 0 Write Data Writes data into DDR or CGR. 40 µs

Table 2-9: Instruction Code

InstructionCode Description

(Notes 2 and 3)

MaximumExecution

Time (Note 1)

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0



Block DescriptionsR

Figure 2-3: Display Initialization Sequence

ug066_c2_03_060804

Hex Code D7 D6 D5 D4 D3 D2 D1 D0

(1)

(2)

(3)

(4)

(5)80 (Hex)

01 (Hex)

0E (Hex)

06 (Hex)

38 (Hex) 0 10 1 1 0 0 0

0 0 0 0 110 0

0 0 0 0 0 0 0 1

1 0 0 0 0 0 0 0

10 1 1 0000

RESET

SEQUENCE

Function Set

8-bit Data Length2 Line

5 x 7 Dot Format

InitializationFlow Chart

≥ 15 mS

Power On

≥ 1.64 uS

End ofInitialization

01 (Hex)

≥ 4.1 mS

38 (Hex)

≥ 100 uS

38 (Hex)

≥ 40 uS

38 (Hex)

≥ 40 uS

38 (Hex)

≥ 40 uS

06 (Hex)

≥ 40 uS

0E (Hex)

≥ 40 uS

80 (Hex)

Entry Mode SetIncrement One

No Shift

Display On/Off Control

Display OnCursor On

Blink Off

Display Clear

DD RAM Address Set1st Digit

(5)

(4)

(3)

(2)

(1)




Figure 2-4: LCD Panel Character Set

ug066_c2_04_060704



PowerR

Power

Power Distribution

The ML365 board uses a 5V +/- 10% input voltage source to generate all the on-board voltages (1.5V, 1.8V, 2.5V, and 3.3V).

Input Voltage

The input voltage is specified at 5 V @ 6.5 A. The recommended power supply is a CUI Inc. DTS050650UTC-PSP-SZ. The jack used is a 2 mm. barrel jack. The slide switch turns the power on or off. Four regulators on the board provide different voltages required by various components on the board.

3.3 V Generation

The Texas Instruments PT5501N voltage regulator generates the 3.3 V @ 3 A power. This power regulator is packaged in a 5-pin, thermally-efficient copper case that is solderable, and provides the auxiliary supply for some of the FPGA I/Os (VCCO).

2.5 V Generation

The Texas Instruments PT5502N voltage regulator generates the 2.5 V @ 3 A power. This power regulator is packaged in a 5-pin, thermally-efficient copper case that is solderable. It supplies the clock oscillators, System Ace device, LCD Display unit, and for some of the FPGA I/Os (VCCAUX).

1.8 V Generation

The Texas Instruments TSP54810 voltage regulator generates the 1.8 V @ 8 A power. This power regulator has a thermally-enhanced 28-pin TSSOP package, and supplies the memory devices.

1.5 V Generation

The Texas Instruments PT5505N voltage regulator generates the 1.5 V @ 3 A power. This power regulator is packaged in a 5-pin, thermally-efficient copper case that is solderable, and provides the core voltage to the FPGA (VCCINT).




FPGA ConfigurationThe demonstration board FPGA programming options are very flexible (refer to the following five configuration modes). For a detailed explanation of the basic Virtex-II configurations, refer to the Virtex-II Platform FPGA User Guide. The five Virtex-II configuration modes are:

• Master Serial mode (not used on QDR II Demo Board)

• Slave Serial / SystemAce mode (QDR II Demo Board default)

• Master SelectMap mode

• Slave SelectMap mode

• JTAG mode

Selecting the Configuration ModeThe FPGA programming modes are set with the mode lines (M0, M1, M2) by means of the 3-pole DIP switch (SW5). Table 2-10 shows the programming modes.

1. Not used on QDR II Demonstration Board.2. SystemAce is a Slave Serial configuration mode, and is the default for the QDR II Demonstration Board.

An LED on the Done pin adds a visual aid to detect a good FPGA configuration. If the LED is “on”, the FPGA configuration is complete.

Serial ConfigurationThe Virtex-II is programmable in serial mode in one of two ways:

Master Serial Mode

This mode is not used in the QDR II Demonstration Board.

Slave Serial Mode

In Slave Serial Mode, the FPGA CCLK pin is driven by an external source. The FPGA is configured by loading one bit per CCLK cycle in the DIN pin.

Table 2-10: Configuration Modes Supported on the QDR II SRAM Demonstration Board

Mode M2 M1 M0 CCLK Data Width Data DOUT

Master Serial(1) 0 0 0 Out 1 Yes

Slave Serial 1 1 1 In 1 Yes

SystemAce(2) 1 1 1 N/A N/A N/A

Master SelectMap 0 1 1 Out 8 No

Slave SelectMap 1 1 0 In 8 No

JTAG 1 0 1 N/A 1 No



FPGA ConfigurationR

SystemAce Configuration (Default Mode)SystemAce is a Slave Serial configuration mode, and is the default mode for the QDR II Demonstration Board.

If the SystemAce Controller (U2) detects a Compact Flash card present in socket P2, it attempts to load a configuration file from the Compact Flash card into the FPGA. Table 2-11 shows the allowable correct jumper positions.

1. Recommended SW5 switch setting for the SystemAce mode is 111; refer to Table 2-10.

SelectMap ConfigurationThe Virtex-II FPGA is programmable using SelectMap, a parallel configuration mode. In this mode, two possibilities of programming exist:

• Master Mode: FPGA delivers the CCLK download clock

• Slave Mode: FPGA must receive the CCLK clock from the external device

The demonstration board can be programmed in both modes using the SelectMap connectors; P99 and P111. The FPGA on the demonstration board can be programmed in slave mode using a MultiLINX cable, or in Master mode when an external device is plugged into these connectors.

The SelectMap connector P99 carries FPGA bits [7:0]. When SelectMap is not used, the SelectMap connector pins can also be used as normal I/O.

Figure 2-5 shows the layout of the SelectMap connectors P99 and P111.

Table 2-11: Jumper Positions for SystemAce Configuration

Pins Jumpered Function

P1.4 to P113 TCK from SystemAce connected to TCK input of the FPGA

P1.7 to P114 TMS from SystemAce connected to TMS input of the FPGA

P1.5 to P1.6 SystemAce TDO connected to the TDI input of the FPGA




Figure 2-5: SelectMap Connectors P99 and P111

ug066_c2_05_060804

FPGA CS#

FPGA RFWR#

FPGA BUSY

FPGA D0

FPGA D1

FPGA D2

FPGA D3

FPGA D4

FPGA D5

FPGA D6

FPGA D7

P99

1 2

3 4

5 6

7

10

8

9

11 12

13 14

15 16

17 18

SelectMAP Header

1

2

3

4

5

6

7

P111

9

8

5V

GND

CCLK

DONE

DIN

PROG

INIT

Header 9



FPGA ConfigurationR

JTAG ConfigurationThe Virtex-II FPGA is programmable in JTAG mode. The JTAG chain contains two on-board devices (FPGA and SystemAce).

The JTAG input connector is P103, wired to the TSTCFG pins of the SystemAce Controller U2. The JTAG input connector is the start of the JTAG chain. The configuration output port of the SystemAce Controller is wired to the FPGA via P1, P113, and P114 pins as shown in Table 2-11. The FPGA can be isolated from the JTAG chain by removing the jumper blocks from the P1 pins as specified in Table 2-11. Figure 2-6 shows how to build the JTAG chain, and Table 2-12 shows the connections for the JTAG connector P1.

Figure 2-6: SystemAce and JTAG Connectors

1

PushbuttonSW6

+3.3 V

+5 V +2.5 V

P26

P111

10KResistors (4)

DIP SwitchSW5

SYSACE_CFGPROG#SYSACE_CFGINIT#

CCLKPROG_BIO_L01P_4/INIT_BDONEM0M1M2HSWAP_ENTCK

CCLKPROG_B

DINPROG

INIT

123456789

SYSACE_TDOTCKTMS

FPGA_TDO

FPGA_TDOFPGA_TDIC31

D5F6AK6F28G27C4G8

AH8D30AL5AJ7

AH27AJ28AK29

F29F7

TDITDOTMS

PWRDWN_BDXNDXP

VBATTRSVD

XC2V3000

U1I P1

+3.3 V

7654321

TMS

TDOTCK

ug066_c2_06_062804

Table 2-12: JTAG Connector Pins (P1)

PinNumber

Function

1 3.3 Volts

2 GND

3 N/C

4 TCK

5 TDO

6 FPGA_TDI

7 TMS




Figure 2-7 shows the JTAG connector P103.

Figure 2-7: JTAG I/O Connector P103

ug124_07_0603_04

1

2

3

4

5

6

7

9

8

3.3V

GND

TCK

TDO

TDI

TMS

NC

NC

NC

P103



R

Chapter 3

Electrical Requirements

Power ConsumptionTable 3-1 lists the operating voltages, maximum currents, and power consumption used by the ML365 board devices. Refer to Appendix 1, “Related Documentation,” for more information on the source material.

1. The resistor count is distributed as follows per devices, and multiplied by the number of devices (3): - data bus D: 36 (x2 (split termination)) - clocks: CQ, C, K: 6 (x2 (split termination)) - address bus A: 18 (x2 (split termination)) - R_n_int: 1 (x2 (split termination)) - Control signals: 6 (x2 (split termination))

Table 3-1: ML365 Power Consumption

Device QuantityVoltage

(V)Current

(mA)Power

(W) Source

Total Available Power

Power Supply 1 5 6500 32.5

FPGA Power (Based on Design)

FPGA (XC2VP20-6 FF1152) 1 6.87 Power Estimator Tool

Board Power

Static Power-on Termination Resistors (Split 100 ohms)

402 1 1.8 7236 13 Virtex-II Pro User Guide

QDR SRAM (108-bit interface) 3 1.8 800 4.32 Samsung QDR SRAM Data Sheet

200 MHz LVPECL Clock Oscillator

2 4 80 0.64 EPSON EG2121CA Data Sheet

16-pin GPIO Header 2 2.6 160 .42 Average 10 mA * 16 pins

LEDs 11 — — 0.5 LED Circuits

DIP Switch 1 — — .06 Eight 3.3 kohm pullups

RS232 Serial Port 1 3.3 40 0.13 Maxim MAX3316ECUP Data Sheet

LCD — 2.5/3.3 100 0.33 LCD Datasheet

System Ace Compact Flash — 2.5/3.3 150 .049 SystemACE Datasheet

Worst Case Power Consumption: 23.0



FPGA Internal Power BudgetThe following tables show the power consumption values inside the FPGA based on the complete QDR design. These results are derived using the Xilinx Power Estimator tool. Block Select RAM, Block Multiplier, Processor, and MGT Power tables are not included in this section as they are not used in this application.

• Table 3-2, “XC2VP20FF1152 Estimated Power Consumption,” page 30

• Table 3-3, “XC2VP20FF1152 Temperature Specifications,” page 30

• Table 3-4, “Device Quiescent Power,” page 30

• Table 3-5, “CLB Logic Power,” page 31

• Table 3-6, “Digital Clock Manager Power,” page 31

• Table 3-7, “Input/Output Power,” page 31

Table 3-2: XC2VP20FF1152 Estimated Power Consumption

Parameter Value Units

Total Estimated Design Power 6500 mW

Estimated Design VCCINT 1.5 V Power 3500 mW

Estimated Design VCCAUX 2.5 V Power 417 mW

Estimated Design VCCO 3.3 V Power 100 mW


Estimated Design VCCO 1.8V Power 7859 mW



Table 3-3: XC2VP20FF1152 Temperature Specifications

Parameter Value Units

Ambient Temperature 25 °C

Air Flow 0 LFM

Junction Temperature 107 °C

Table 3-4: Device Quiescent Power

VCCINT Subtotal (mW) VCCAUX Subtotal (mW)

450 417



Table 3-5: CLB Logic Power

NameFrequency

(MHz)

Total Number of CLB Slices

Total Number of Flip/Flop or

Latches

Total Number of Shift Register

LUTs

Total Number of Select RAM

LUTs

Average Toggle Rate

%

Amount of Routing

Used

VCCINT Subtotal

(mW)

User Module 1 200 1299 1302 0 544 40% High 1220

User Module 2 0 0 0 0 0 0% Low 0

Total 1220

Table 3-6: Digital Clock Manager Power

NameClock Input Frequency

(MHz)DCM Frequency Mode VCCINT Subtotal (mW)

User DCM 1 200 Low 6

User DCM 2 200 Low 6

Total 12

Table 3-7: Input/Output Power

NameFrequency

(MHz)I/O Standard

Type

TotalNumber

of Inputs

TotalNumber

ofOutputs

AverageIOB

ToggleRate

%

AverageOutputEnableRate

%

AverageOutputLoad (pF)

IOBRegisters

VCCINTSubtotal

(mW)

VCCOSubtotal

(mW)

CLK200 200 LVDS_25 1 0 100% 100% 15 DDR 2 8

CLK200_N 200 LVDS_25 1 0 100% 100% 35 DDR 2 8

GPIO 200 LVDCI_25 (50) 0 16 10% 100% 35 DDR 14 157

D/mem_R_n_ext 200 HSTL_II (1.8v) 0 111 25% 100% 35 DDR 11 752

Q/mem_R_n_int 200 HSTL_II_DCI (1.8v) 111 0 25% 0% 35 DDR 258 3662

Mem Addr/Control 200 HSTL_II_DCI (1.8v) 0 66 10% 100% 35 SDR 18 2431

Mem K/C 200 HSTL_II_DCI (1.8v) 0 12 25% 100% 35 DDR 13 536

Mem CQ 200 HSTL_II_DCI (1.8v) 6 0 25% 0% 35 DDR 25 260

A_R/W, C_R/W 200 HSTL_II (1.8v) 0 12 10% 100% 35 SDR 1 41

Total 344 7859





Termination and Transmission Line SummariesR

Chapter 4

Signal Integrity Recommendations and Simulations

This chapter provides the following information:

• Summary of the termination schemes for various signals (refer to “Termination and Transmission Line Summaries,” page 33).

• IBIS simulations and duty cycle measurements (refer to “IBIS Simulations,” page 35).

Termination and Transmission Line SummariesTable 4-1 summarizes the terminations for the three QDR II SRAM components for both the FPGA and memory.

Table 4-1: QDR SRAM Terminations

Number Signal Drivers at the FPGA Termination at FPGA Termination at Memory

1 Data (D) HSTL_18_C2_DCI No termination 50 ohm pull-up to 0.9 V

2 Data (Q) HSTL_18_C1 No termination No termination

3 Data Strobe (CQ, CQ) HSTL_18_C2 50 ohm pull-up to 1.3V 50 ohm pull-up to 0.9 V

4 Clock (K, K) HSTL_18_C2 50 ohm pull-up to 1.3V No termination

5Address (A) HSTL_18_C2 No termination 100 ohm parallel split

termination pull-up to 1.8 V

6Control (R, W, BW) HSTL_18_C2 No termination 100 ohm parallel split

termination pull-up to 1.8 V



Chapter 4: Signal Integrity Recommendations and SimulationsR

Terminations and Transmission Lines for QDR Components

Data and Clock Signals (D, Q, CQ, CQ, and CLK) For the QDR signals included in the data bus D, the terminations consist of a 50 ohm parallel termination pulled-up to 0.9 Volts. As DCI is used in the FPGA, no termination is required.

Use 50 ohm transmission lines with less than ±1% tolerance on the transmission line impedance. The recommendations for the transmission line lengths are:

• All the data and clock signals are point-to-point from the FPGA to each QDR component. The flight time of the signals going to one individual QDR II SRAM component need to be matched with respect to the other signals with a ±2% tolerance.

• All signals going to the memory component have been matched within a 200 ps. window. This timing requirement includes the FPGA internal package skew (available in Appendix 2, “FPGA Pinout”) and the skew between the ball of the FPGA to the resistor pack as well as the length of the actual trace.

• The IBIS simulation provided in “IBIS Simulations,” page 35 have been processed using the actual PCB characteristics, from the PCB layout tool and the memory and FPGA driver IBIS models.

Address and Control Signals (A, R, W, BW)For the address and control signals, no termination is required at the FPGA. At memory, a 50 ohm resistor pulled up to 0.9 V is used to terminate the transmission line.

Use 50 ohm transmission lines with ± 5% tolerance from the FPGA to all the memory components. The recommendations for the transmission line lengths are as follows:

• All the data and clock signals are point-to-point from the FPGA to each QDR component. The flight time of the signals going to one individual QDR II SRAM component need to be matched with respect to to the other signals with a ± 2% tolerance.

• All signals going to the memory component have been matched within a 200 ps. window. This timing requirement includes the FPGA internal package skew (available in Appendix 2, “FPGA Pinout”) and the skew between the ball of the FPGA to the resistor pack as well as the length of the actual trace.

• The IBIS simulation provided in “IBIS Simulations,” page 35 have been processed using the actual PCB characteristics, from the PCB layout tool and the memory and FPGA driver IBIS models.



IBIS SimulationsR

IBIS SimulationsThis section summarizes the various simulations run on the ML365 Board using IBIS. The simulations have been completed using the Cadence SPECCTRAQuest tool. These simulations account for specific PCB characteristics, ensuring high fidelity waveforms. For each waveform presented in this section, the results of the test conditions are provided.

The simulations have been divided into the following categories:

Data Signal Simulations

♦ Data signals from the FPGA to the QDR II SRAM, U11, Component B, Data D, Bit 4

- Typical Case

- Slow Weak Case

- Fast Strong Case

- Eye Diagram

♦ Data signals from the QDR II SRAM to the FPGA, U11, Component B, Data Q, Bit 4

- Typical Case

- Slow Weak Case

- Fast Strong Case

- Eye Diagram

Clock Signal Simulations

♦ Clock signals from the FPGA to the QDR II SRAM, U11, Component B

- Typical Case

- Slow Weak Case

- Fast Strong Case

Address and Control Signal Simulations

♦ Address and control signals from the FPGA to the QDR II SRAM Memory Component

- QDR II SRAM, U11, Component B, Address Bit 4 (Typical, Slow/Weak, and Fast/Strong Cases)

Notes on the Simulation ResultsThe provided waveforms show the results of each simulation. The signals in these waveforms are color-coded:

• Purple signal: Typical driver

• Green signal: Fast/strong driver

• Blue signal: Slow/weak driver

For the eye diagram, the typical drivers are used.




Data Signal SimulationsAll of the data signal simulation use the following test conditions for typical, slow/weak, and fast/strong cases:

• Topology for data signals: 50-ohm transmission lines

• Transmit:

♦ At the memory: 100-ohm parallel split termination pulled-up to Vdd = 1.8 V (equivalent to a 50-ohm termination pulled up to Vref = 0.9V)

♦ At the FPGA: HSTL_18_C2 drivers

• Receive:

♦ At the FPGA: HSTL_18_C1_DCI receivers (internal termination, VRP, and VRN pins connected to reference resistors)

Figure 4-1 shows signal terminations for transmitted and received data.

Figure 4-1: Signal Terminations for Transmitted and Received Data

ml365_01_061504

Vdd

QDR II SRAM

QDR II SRAMFPGA

FPGA



IBIS SimulationsR

Data Signals from the FPGA to the Memory (HSTL_18_C2 at FPGA)The simulations in this subsection test the data signals from the FPGA to the memory. Simulations were performed for the following cases: typical, slow/weak, and fast/strong (refer to Figure 4-2).

An eye diagram is provided as well (refer to Figure 4-3).

Figure 4-2: Data Signal Bit 4 from the FPGA to the Memory (Typical Case)




Figure 4-3: Eye Diagram for Data Bit 4 from the FPGA to the QDR II SRAM, U11



IBIS SimulationsR

Data Signals from the QDR II SRAM, Component U11 to the FPGA Measured at the FPGA

The simulations in this subsection test the data signals from the last memory component to the FPGA. Simulations were performed for the following cases: typical, slow/weak, and fast/strong. An eye diagram is provided as well (refer to Figure 4-5).

Figure 4-4 shows the simulation waveforms for this case.

Figure 4-4: Data Signals from the QDR II SRAM U11 at the FPGA (Typical,Slow/Weak and Fast/Strong Cases)




Eye Diagram for the Component U11, Bit 4 Signal Measured at the FPGAFigure 4-5 shows the eye diagram for the data signals from the FPGA to the last memory component.

Figure 4-5: Eye Diagram for Data Bit 4 at the FPGA from Component U11



Clock Signal SimulationsR

Clock Signal SimulationsThe simulations in this subsection test the uni-directional Clock K signal from the FPGA to the QDR II SRAM, Component B. Simulations were performed for the following cases: typical, slow/weak, and fast/strong. All of the clock signal simulations use the following test conditions for typical, slow/weak, and fast/strong cases (refer to Figure 4-6).

• Topology for clock signals: 50-ohm transmission lines

• Clock K

♦ At the memory: 100-ohm parallel split termination pulled-up to Vdd = 1.8 V (equivalent to a 50-ohm termination pulled up to Vref = 0.9V)

♦ At the FPGA: HSTL_18_C2 drivers

• CQ Clock

♦ At the FPGA: HSTL_18_C1 receivers, 100-ohm parallel split termination pulled-up to Vdd = 1.8 V (equivalent to a 50-ohm termination pulled up to Vref = 0.9V)

Figure 4-6: Clock Signal Terminations

ml365_02_062804

QDR II SRAM

QDR II SRAMFPGA

FPGA

Vdd

Vdd

CQ Clock

K Clock




Typical, Slow, and Fast Cases for Clock SignalsFigure 4-7 shows the simulation waveforms for this case.

Figure 4-8 shows the simulation waveforms for the Clock K Signal from the FPGA to the QDR II SRAM, Component U11.

Figure 4-7: Clock K Signal from the FPGA to the QDR II SRAM, Component U11



Clock Signal SimulationsR

Figure 4-8: Clock CQ Signal from the FPGA to the QDR II SRAM Component U11




Address and Control Signal SimulationsThe simulations in this subsection test the uni-directional address and control signals from the FPGA to the QDR II SRAM, Component B, U11, Bit 4. Simulations were performed for typical, slow/weak, and fast/strong driver cases.

All of the clock signal simulations use the following test conditions for typical, slow weak, and fast strong cases

• Topology for data signals: 50-ohm Transmission lines

• At the memory: 100-ohm parallel split termination pulled up to Vdd = 1.8 V (equivalent to 50-ohm termination pulled up to Vref = 0.9V)

• At the FPGA: HSTL_18_C2 drivers

Figure 4-9 shows address and control signal terminations.

Typical Case Simulation at All Memory ComponentsFigure 4-10 shows the typical case simulation waveforms for the QDR II SRAM, Component B, Bit 4.

Figure 4-9: Address and Control Signal Terminations

ml365_03_061504

QDR II SRAMFPGA

Vdd



Address and Control Signal SimulationsR

Figure 4-10: Address/Control Signals for the QDR II SRAM, Component U11, Bit 4






R

Chapter 5

Board Layout Guidelines

This chapter provides information on decoupling capacitors, ground signals, and PCB layout.

Decoupling GuidelinesThis section lists the decoupling capacitors used with the major components of the ML365 board. Refer to the board schematics for the exact placement.

Table 5-1 lists the decoupling capacitors for the Virtex-II Pro FPGA and the QDR II SRAM. VAUX and VDD are common to these two devices. Refer to the Xilinx application note XAPP623 for the implementation methodology. A balanced decoupling network is implemented for each bank, VCCINT, VAUX, and VREF.

Table 5-1: Decoupling Capacitor Recommendations

Decoupling Capacitors

Pin(s) Capacitor Value Distribution

VCC 5V

LCD, RS232

0.01µF ceramic capacitor, X7R, C0402 8

0.047µF ceramic capacitor, X7R , C0603 4


33µF ceramic capacitor, 10V, C7343 0

330µF solid tantalum capacitor, 10V, C7343 3

3.3V

System ACE








Chapter 5: Board Layout GuidelinesR

Providing Additional Ground Pins Unused and No Connect pinscan be connected to ground to improve the thermal dissipation through the metal planes in the Printed Circuit Board. Since DCI can be used in the FPGA, the heat resulting from its use can be significant.

VAUX 2.5V

1 capacitor per pin, in a balanced decoupling network.






VCCO 1.8V

HSTL 1.8V electrical standard






VCCINT 1.5V

1 capacitor per pin, in a balanced decoupling network.






VTT 0.9V

HSTL 1.8V/2 for FPGA Vref inputs






VTT 0.9V

HSTL 1.8V/2 for memory Vref inputs






Table 5-1: Decoupling Capacitor Recommendations

Decoupling Capacitors

Pin(s) Capacitor Value Distribution



Board Stackup GuidelinesR

Board Stackup Guidelines Table 5-2 shows a suggested stackup for a 12-layer board (4 signal layers, 6 dedicated planes, 2 layers with both signals and ground planes). Figure 5-1 shows the top layer of the ML365 (Revision 1.0b) board, and Figure 5-2 shows the bottom layer of the board.

Table 5-2: Suggested Stackup for a 12-layer board

12-Layer Board

Stackup# Type Layer Trace / Spacing Comments

1 Plane GND Gnd 1 / Sig 1 Ground plane, some memory traces

2 Plane +2.5V/ +5V Pwr 1 Carve out two power planes on this layer

3 Signal +1.8V/ +2.5V Sig 2 Some HSTL traces to the memory on this layer


5 Plane GND Gnd 2 Ground plane

6 Plane +1.5V Pwr 2 1.5V power plane

7 Plane +0.9V Pwr 3 0.9V reference plane

8 Plane GND Gnd 3 Ground plane


10 Signal GND Sig 5 Ground plane

11 Plane +1.8V & +3.3V Pwr 4 Carve out two power planes on this layer

12 Plane GND Gnd 4 / Sig 6 Ground plane, some memory traces




Figure 5-1: Picture of the Top Layer of the ML365 Revision 1.0b Board



Board Stackup GuidelinesR

Figure 5-2: Picture of the Bottom Layer of the ML365 Revision 1.0b Board






R

Appendix 1

Related Documentation

This appendix provides references to documents and web pages for components on the ML365 board.

• Xilinx, Inc.

♦ Virtex-II Pro X™ Platform FPGAs

http://www.xilinx.com/bvdocs/publications/ds083.pdf

♦ System ACE CompactFlash Solutionhttp://direct.xilinx.com/bvdocs/publications/ds080.pdf

• Texas Instruments

♦ TI PT5505N 1.5Vout 3Amp 3.3V/5V-Input Adjustable Step-Down ISRhttp://focus.ti.com/docs/prod/folders/print/pt5505.html

♦ TI PT5502N 2.5Vout 3Amp 3.3V/5V-Input Adjustable Step-Down ISRhttp://focus.ti.com/docs/prod/folders/print/pt5502.html

♦ TI PT5501A 3.3Vout 3Amp 5V-Input Adjustable Step-Down ISRhttp://focus.ti.com/docs/prod/folders/print/pt5501.html

♦ TPS54810PWP 5V Input 8A Synchronous Buck Converter with Adjustable Output Voltage (1.8V) http://focus.ti.com/docs/prod/folders/print/tps54810.html

♦ Maxim MAX3316ECUP RS232 Interface

http://pdfserv.maxim-ic.com/en/ds/MAX3316E-MAX3319E.pdf

• Samsung

♦ Samsung QDR II SRAM Componentshttp://www.samsung.com/Products/Semiconductor/SRAM/SyncSRAM/QDRI_II/36Mbit/K7R323684M/ds_k7r323684m.pdf

• Epson

♦ Epson EG-2121CA 2.5V PECL Osc., EG2121CA-200.0000M-PHPABEpson EG-2121CA 2.5V PECL Osc., EG2121CA-250.0000M-PHPABhttp://www.epson-ed.info/FOE2003/e_prdct/EG2121CA.html

• Agilent Technologies

♦ Logic Analyzer: Agilent Technologies 16753/54/55/56 Logic Analyzer

http://cp.literature.agilent.com/litweb/pdf/5988-9043EN.pdf

♦ Logic Analyzer Probes: Agilent Technologies Connector-based Probes

http://cp.literature.agilent.com/litweb/pdf/16760-97012.pdf


http://focus.ti.com/docs/prod/folders/print/pt5505.html


http://www.xilinx.com/bvdocs/publications/ds083.pdf

http://pdfserv.maxim-ic.com/en/ds/MAX3316E-MAX3319E.pdf

http://www.samsung.com/Products/Semiconductor/SRAM/SyncSRAM/QDRI_II/36Mbit/K7R323684M/ds_k7r323684m.pdf

http://www.epson-ed.info/FOE2003/e_prdct/EG2121CA.html

http://cp.literature.agilent.com/litweb/pdf/5988-9043EN.pdf

http://cp.literature.agilent.com/litweb/pdf/16760-97012.pdf


http://focus.ti.com/docs/prod/folders/print/tps54810.html


Appendix 1: Related DocumentationR



R

Appendix 2

FPGA Pinout

Table 2-1 summarizes the pinout of the XC2VP20FF1152-6 FPGA in the ML365 board.

I/O pin names marked as GND refer to unused I/Os that are directly connected to GND. I/O pin names marked as PULLDOWN refer to unused I/Os that are connected to GND through a zero ohm resistor. The zero ohm resistor can be removed to use the corresponding I/O for any test purposes.

Table 2-1: FPGA Pin Out

SliceCoordinates

PinNumbers

Virtex-II ProBank

Number

PackageFunctional

Name

I/OPin

Names

PackageFlightTimes

(In Microns)

X1Y111 E29 0 IO_L01N_0/VRP_0 R114/C430 11097.26

X1Y111 E28 0 IO_L01P_0/VRN_0 R117/C370 10150.32

X1Y111 H26 0 IO_L02N_0 QDR_DREAD_C0 6327.18

X1Y111 G26 0 IO_L02P_0 QDR_DREAD_C1 7905.95


X3Y111 G25 0 IO_L03P_0/VREF_0 Vref(0.9V) 6996.94

X5Y111 J25 0 IO_L05_0/No_Pair QDR_DREAD_C3 5273.75

X5Y111 K24 0 IO_L06N_0 QDR_DREAD_C4 3344.34

X5Y111 J24 0 IO_L06P_0 QDR_DREAD_C5 4601.94

X7Y111 F26 0 IO_L07N_0 QDR_DREAD_C6 9207.2

X7Y111 E26 0 IO_L07P_0 QDR_DREAD_C7 10718.03

X7Y111 D30 0 IO_L08N_0 QDR_DREAD_C8 15834.96

X7Y111 D29 0 IO_L08P_0 QDR_DREAD_C9 14848.81


X9Y111 J23 0 IO_L09P_0/VREF_0 Vref(0.9V) 4323.64


X11Y111 G22 0 IO_L37P_0 QDR_DREAD_C12 5923


X11Y111 C26 0 IO_L38P_0 QDR_DREAD_C14 15469.57





Appendix 2: FPGA PinoutR



X19Y111 E25 0 IO_L44N_0 QDR_DREAD_C19 12735.3



X21Y111 G21 0 IO_L45P_0/VREF_0 Vref(0.9V) 7704.24




X23Y111 C24 0 IO_L47P_0 QDR_DREAD_C25 13516.13





X27Y111 C21 0 IO_L50_0/No_Pair QDR_DREAD_C30 13499.9

X29Y111 C22 0 IO_L53_0/No_Pair QDR_DREAD_C31 15061.08

X29Y111 L19 0 IO_L54N_0 QDR_DREAD_C32 2263.39

X29Y111 K19 0 IO_L54P_0 QDR_DREAD_C33 3226.4

X31Y111 G20 0 IO_L55N_0 QDR_DREAD_C34 6227.05

X31Y111 F20 0 IO_L55P_0 QDR_DREAD_C35 7549.54

X31Y111 D21 0 IO_L56N_0 R_n_int_C 10983.43

X31Y111 D20 0 IO_L56P_0 GND 10275.3

X33Y111 J19 0 IO_L57N_0 GND 3969.14

X33Y111 H19 0 IO_L57P_0/VREF_0 Vref(0.9V) 5173.85

X35Y111 G19 0 IO_L67N_0 GND 6064.32

X35Y111 F19 0 IO_L67P_0 GND 8063.93

X35Y111 E19 0 IO_L68N_0 GND 9549.27

X35Y111 D19 0 IO_L68P_0 GND 10957.97

X37Y111 L18 0 IO_L69N_0 GND 2444

X37Y111 K18 0 IO_L69P_0/VREF_0 Vref(0.9V) 3320.11

X43Y111 G18 0 IO_L73N_0 GND 5890.16

X43Y111 F18 0 IO_L73P_0 GND 7223.69

X45Y111 E18 0 IO_L74N_0/GCLK7P QDR_CQ_C 8692.96

X45Y111 D18 0 IO_L74P_0/GCLK6S QDR_CQ_n_C 9819.09


SliceCoordinates

PinNumbers

Virtex-II ProBank

Number

PackageFunctional

Name

I/OPin

Names

PackageFlightTimes

(In Microns)



R

X45Y111 J18 0 IO_L75N_0/GCLK5P GND 3858.95

X45Y111 H18 0 IO_L75P_0/GCLK4S GND 5131.43

X47Y111 H17 1 IO_L75N_1/GCLK3P GND 5131.43

X47Y111 J17 1 IO_L75P_1/GCLK2S GND 3858.95

X47Y111 D17 1 IO_L74N_1/GCLK1P GND 10242.07

X47Y111 E17 1 IO_L74P_1/GCLK0S GND 8752.34

X49Y111 F17 1 IO_L73N_1 GND 7223.69

X49Y111 G17 1 IO_L73P_1 GND 5890.16

X55Y111 K17 1 IO_L69N_1/VREF_1 Vref(0.9V) 3320.11

X55Y111 L17 1 IO_L69P_1 QDR_DWRITE_C0 2444

X57Y111 D16 1 IO_L68N_1 QDR_DWRITE_C1 10931.46

X57Y111 E16 1 IO_L68P_1 QDR_DWRITE_C2 9549.27

X57Y111 F16 1 IO_L67N_1 QDR_DWRITE_C3 8063.93

X57Y111 G16 1 IO_L67P_1 QDR_DWRITE_C4 6064.32

X59Y111 H16 1 IO_L57N_1/VREF_1 Vref(0.9V) 5173.85

X59Y111 J16 1 IO_L57P_1 QDR_DWRITE_C5 3969.14


X61Y111 D14 1 IO_L56P_1 QDR_DWRITE_C7 10983.43

X61Y111 F15 1 IO_L55N_1 QDR_DWRITE_C8 7549.54

X61Y111 G15 1 IO_L55P_1 QDR_DWRITE_C9 6227.05

X63Y111 K16 1 IO_L54N_1 QDR_DWRITE_C10 3226.4

X63Y111 L16 1 IO_L54P_1 QDR_DWRITE_C11 2263.39

X63Y111 C13 1 IO_L53_1/No_Pair QDR_DWRITE_C12 15102.5

X65Y111 C14 1 IO_L50_1/No_Pair QDR_DWRITE_C13 13541.32

X65Y111 E14 1 IO_L49N_1 QDR_DWRITE_C14 8634.04

X65Y111 F14 1 IO_L49P_1 QDR_DWRITE_C15 7682.05

X67Y111 J15 1 IO_L48N_1 QDR_DWRITE_C16 4150.17

X67Y111 K15 1 IO_L48P_1 QDR_DWRITE_C17 3084.88

X69Y111 C11 1 IO_L47N_1 QDR_DWRITE_C18 13513.12




X71Y111 G14 1 IO_L45N_1/VREF_1 Vref(0.9V) 7704.24


SliceCoordinates

PinNumbers

Virtex-II ProBank

Number

PackageFunctional

Name

I/OPin

Names

PackageFlightTimes

(In Microns)




X71Y111 H14 1 IO_L45P_1 QDR_DWRITE_C22 6364.26


X73Y111 E10 1 IO_L44P_1 QDR_DWRITE_C24 12296.5

X73Y111 E13 1 IO_L43N_1 QDR_DWRITE_C25 8910.89

X73Y111 F13 1 IO_L43P_1 QDR_DWRITE_C26 7591.45

X79Y111 J14 1 IO_L39N_1 QDR_DWRITE_C27 4903.25


X81Y111 C9 1 IO_L38N_1 QDR_DWRITE_C29 15339.71


X81Y111 G13 1 IO_L37N_1 QDR_DWRITE_C31 5923

X81Y111 H13 1 IO_L37P_1 QDR_DWRITE_C32 4727.82

X83Y111 J12 1 IO_L09N_1/VREF_1 Vref(0.9V) 4323.64




X85Y111 E9 1 IO_L07N_1 QDR_C_n_C 10718.03

X85Y111 F9 1 IO_L07P_1 QDR_C_C 9223.77

X87Y111 J11 1 IO_L06N_1 QDR_K_n_C 4601.94

X87Y111 K11 1 IO_L06P_1 QDR_K_C 3344.34

X87Y111 J10 1 IO_L05_1/No_Pair QDR_W_n_C 5273.75

X89Y111 G10 1 IO_L03N_1/VREF_1 Vref(0.9V) 6996.94

X89Y111 H10 1 IO_L03P_1 QDR_R_n_C 5691.71

X91Y111 G9 1 IO_L02N_1 R_n_ext_C 7905.95

X91Y111 H9 1 IO_L02P_1 6327.18

X91Y111 E7 1 IO_L01N_1/VRP_1 R116/C431 10150.32

X91Y111 E6 1 IO_L01P_1/VRN_1 R115/C371 11097.26

X91Y111 D2 2 IO_L01N_2/VRP_2 R119/C432 7113.13

X91Y110 D1 2 IO_L01P_2/VRN_2 R118/C375 4624.16

X90Y111 F8 2 IO_L02N_2 QDR_SA_C0 3390.64

X90Y110 F7 2 IO_L02P_2 QDR_SA_C1 5566.52

X90Y109 E4 2 IO_L03N_2 QDR_SA_C2 6738.57

X90Y108 E3 2 IO_L03P_2 QDR_SA_C3 14050.12

X91Y107 E2 2 IO_L04N_2/VREF_2 Vref(0.9V) 15547.77


SliceCoordinates

PinNumbers

Virtex-II ProBank

Number

PackageFunctional

Name

I/OPin

Names

PackageFlightTimes

(In Microns)



R

X91Y106 E1 2 IO_L04P_2 QDR_SA_C4 15132.61

X90Y107 J8 2 IO_L05N_2 QDR_SA_C5 6469.14

X90Y106 J7 2 IO_L05P_2 QDR_SA_C6 7292.33

X90Y105 F5 2 IO_L06N_2 QDR_SA_C7 10666.81

X90Y104 F4 2 IO_L06P_2 QDR_SA_C8 11858.77

X91Y103 H2 2 IO_L31N_2 QDR_SA_C9 12137.04

X91Y102 H1 2 IO_L31P_2 QDR_SA_C10 13451.41

X90Y103 M10 2 IO_L32N_2 QDR_SA_C11 3062.48

X90Y102 M9 2 IO_L32P_2 QDR_SA_C12 4123.3

X90Y101 K5 2 IO_L33N_2 QDR_SA_C13 8267.43

X90Y100 K4 2 IO_L33P_2 QDR_SA_C14 9537.04


X91Y98 K2 2 IO_L34P_2 QDR_SA_C15 11352.59

X90Y99 L8 2 IO_L35N_2 QDR_SA_C16 5592.79

X90Y98 L7 2 IO_L35P_2 QDR_SA_C17 6793.53

X90Y97 L6 2 IO_L36N_2 GND 7367.37

X90Y96 L5 2 IO_L36P_2 GND 8143.52

X91Y95 K1 2 IO_L37N_2 QDR_BW_n_C0 12423.45

X91Y94 L1 2 IO_L37P_2 QDR_BW_n_C1 12451.17

X90Y95 N10 2 IO_L38N_2 QDR_BW_n_C2 2788.42

X90Y94 N9 2 IO_L38P_2 QDR_BW_n_C3 3972.59

X90Y93 M7 2 IO_L39N_2 GND 5610.09

X90Y92 M6 2 IO_L39P_2 GND 6975.04

X91Y91 L2 2 IO_L40N_2/VREF_2 Vref(0.9V) 11195.56

X91Y90 M2 2 IO_L40P_2 R_n_int_B 12186.54

X90Y91 N8 2 IO_L41N_2 QDR_DREAD_B0 4920.17

X90Y90 N7 2 IO_L41P_2 QDR_DREAD_B1 6104.35

X90Y89 L4 2 IO_L42N_2 QDR_DREAD_B2 9001.57

X90Y88 L3 2 IO_L42P_2 QDR_DREAD_B3 10259.17

X91Y87 M4 2 IO_L43N_2 QDR_DREAD_B4 8536.05

X91Y86 M3 2 IO_L43P_2 QDR_DREAD_B5 9772.91

X90Y87 P10 2 IO_L44N_2 QDR_DREAD_B6 2638.82

X90Y86 P9 2 IO_L44P_2 QDR_DREAD_B7 3823



SliceCoordinates

PinNumbers

Virtex-II ProBank

Number

PackageFunctional

Name

I/OPin

Names

PackageFlightTimes

(In Microns)




X90Y84 N5 2 IO_L45P_2 QDR_DREAD_B9 7563.61

X91Y83 M1 2 IO_L46N_2/VREF_2 Vref(0.9V) 11667.8

X91Y82 N1 2 IO_L46P_2 QDR_CQ_n_B 11804.99

X90Y83 P8 2 IO_L47N_2 GND 4770.58

X90Y82 P7 2 IO_L47P_2 GND 5954.75

X90Y81 N4 2 IO_L48N_2 GND 8437.77

X90Y80 N3 2 IO_L48P_2 GND 9778.21


X91Y78 P2 2 IO_L49P_2 QDR_DREAD_B11 10530.82

X90Y79 R10 2 IO_L50N_2 QDR_DREAD_B12 2488.12

X90Y78 R9 2 IO_L50P_2 QDR_DREAD_B13 3672.29


X90Y76 P5 2 IO_L51P_2 QDR_DREAD_B15 7603.44

X91Y75 P4 2 IO_L52N_2/VREF_2 Vref(0.9V) 8102.88

X91Y74 P3 2 IO_L52P_2 GND 9339.48

X90Y75 T11 2 IO_L53N_2 QDR_DREAD_B16 1247.81

X90Y74 U11 2 IO_L53P_2 QDR_DREAD_B17 1919.47






X90Y70 T9 2 IO_L56P_2 QDR_DREAD_B23 3871.63



X91Y67 R2 2 IO_L58N_2/VREF_2 Vref(0.9V) 9961.47

X91Y66 T2 2 IO_L58P_2 QDR_CQ_B 10173.21

X90Y67 T8 2 IO_L59N_2 GND 4753.73

X90Y66 T7 2 IO_L59P_2 GND 5872.43

X90Y65 T6 2 IO_L60N_2 GND 6031.43

X90Y64 T5 2 IO_L60P_2 GND 7055.3


X91Y62 T3 2 IO_L85P_2 QDR_DREAD_B27 9056.44

X90Y63 U10 2 IO_L86N_2 QDR_DREAD_B28 2340.31


SliceCoordinates

PinNumbers

Virtex-II ProBank

Number

PackageFunctional

Name

I/OPin

Names

PackageFlightTimes

(In Microns)



R




X91Y59 U2 2 IO_L88N_2/VREF_2 Vref(0.9V) 9665.64

X91Y58 V2 2 IO_L88P_2 GND 10394.2





X91Y55 V3 3 IO_L90N_3 QDR_DWRITE_B0 8537.7

X91Y54 V4 3 IO_L90P_3 QDR_DWRITE_B1 7799.59





X91Y51 W2 3 IO_L87N_3/VREF_3 Vref(0.9V) 9812.03

X91Y50 Y2 3 IO_L87P_3 QDR_DWRITE_B6 10611.96



X90Y49 W3 3 IO_L85N_3 QDR_DWRITE_B9 8919.9

X90Y48 W4 3 IO_L85P_3 QDR_DWRITE_B10 8159.47

X91Y47 Y1 3 IO_L60N_3 QDR_DWRITE_B11 11148.48

X91Y46 AA1 3 IO_L60P_3 QDR_DWRITE_B12 11691.6





X91Y43 Y3 3 IO_L57N_3/VREF_3 Vref(0.9V) 8909.69




X90Y41 Y6 3 IO_L55N_3 QDR_DWRITE_B20 5961.45



SliceCoordinates

PinNumbers

Virtex-II ProBank

Number

PackageFunctional

Name

I/OPin

Names

PackageFlightTimes

(In Microns)




X91Y39 AA2 3 IO_L54N_3 QDR_DWRITE_B22 10317.88

X91Y38 AB2 3 IO_L54P_3 QDR_DWRITE_B23 11488.21





X91Y35 AB1 3 IO_L51N_3/VREF_3 Vref(0.9V) 12006.27

X91Y34 AC1 3 IO_L51P_3 QDR_DWRITE_B28 12342.28

X91Y33 Y9 3 IO_L50N_3 QDR_DWRITE_B29 3554




X91Y31 AB3 3 IO_L48N_3 QDR_DWRITE_B33 9319.47

X91Y30 AB4 3 IO_L48P_3 QDR_DWRITE_B34 8556.07


X91Y28 AA8 3 IO_L47P_3 4888.88

X90Y29 AB5 3 IO_L46N_3 QDR_SA_B0 7371.9

X90Y28 AB6 3 IO_L46P_3 QDR_SA_B1 6629.5

X91Y27 AC2 3 IO_L45N_3/VREF_3 Vref(0.9V) 10601.93

X91Y26 AD2 3 IO_L45P_3 QDR_SA_B2 11866.32

X91Y25 AA9 3 IO_L44N_3 QDR_SA_B3 3704.71

X91Y24 AA10 3 IO_L44P_3 QDR_SA_B4 2717.14

X90Y25 AC3 3 IO_L43N_3 QDR_SA_B5 9702.33

X90Y24 AC4 3 IO_L43P_3 QDR_SA_B6 8911.96

X91Y23 AD1 3 IO_L42N_3 QDR_SA_B7 12256.07

X91Y22 AE1 3 IO_L42P_3 QDR_SA_B8 12534.09

X91Y21 AB7 3 IO_L41N_3 QDR_SA_B9 5986.05

X91Y20 AB8 3 IO_L41P_3 QDR_SA_B10 5038.48

X90Y21 AC6 3 IO_L40N_3 QDR_SA_B11 6521.49

X90Y20 AC7 3 IO_L40P_3 QDR_SA_B12 5779.09

X91Y19 AD3 3 IO_L39N_3/VREF_3 Vref(0.9V) 9751.53

X91Y18 AD4 3 IO_L39P_3 QDR_SA_B13 9046.71

X91Y17 AB9 3 IO_L38N_3 QDR_SA_B14 3854.3

X91Y16 AB10 3 IO_L38P_3 QDR_SA_B15 2906.72


SliceCoordinates

PinNumbers

Virtex-II ProBank

Number

PackageFunctional

Name

I/OPin

Names

PackageFlightTimes

(In Microns)



R

X90Y17 AD5 3 IO_L37N_3 QDR_SA_B16 8126.55

X90Y16 AD6 3 IO_L37P_3 QDR_SA_B17 8070.54

X91Y15 AE2 3 IO_L36N_3 QDR_BW_n_B0 11537.91

X91Y14 AF2 3 IO_L36P_3 QDR_BW_n_B1 11948.48

X91Y13 AD7 3 IO_L35N_3 QDR_BW_n_B2 6675.24

X91Y12 AD8 3 IO_L35P_3 QDR_BW_n_B3 5651.11

X90Y13 AE4 3 IO_L34N_3 QDR_K_B 9342.05

X90Y12 AE5 3 IO_L34P_3 QDR_K_n_B 8811.79

X91Y11 AG1 3 IO_L33N_3/VREF_3 Vref(0.9V) 12986.31

X91Y10 AG2 3 IO_L33P_3 R_n_ext_B 12391.44

X91Y9 AC9 3 IO_L32N_3 QDR_R_n_B 4005.01

X91Y8 AC10 3 IO_L32P_3 QDR_W_n_B 3336.69

X90Y9 AF3 3 IO_L31N_3 QDR_C_B 10624.52

X90Y8 AF4 3 IO_L31P_3 QDR_C_n_B 10021.36

X91Y7 AL1 3 IO_L06N_3 GND 15821.97

X91Y6 AL2 3 IO_L06P_3 GND 15583.83

X91Y5 AG7 3 IO_L05N_3 GND 9638.17

X91Y4 AH8 3 IO_L05P_3 DONE 9015.73

X90Y5 AH5 3 IO_L04N_3 GND 9452.34

X90Y4 AH6 3 IO_L04P_3 GND 9308.27

X91Y3 AK3 3 IO_L03N_3/VREF_3 Vref(0.9V) 12802.28

X91Y2 AK4 3 IO_L03P_3 GND 12761.57

X91Y1 AJ7 3 IO_L02N_3 GND 12205.75

X91Y0 AJ8 3 IO_L02P_3 GND 10415.12

X90Y1 AJ4 3 IO_L01N_3/VRP_3 R120/C433 11311.2

X90Y0 AJ5 3 IO_L01P_3/VRN_3 R121/C372 10985.88

X90Y0 AL5 4 IO_L01N_4/DOUT FPGA_BUSY 13235.56

X90Y0 AL6 4 IO_L01P_4/INIT_B INIT_B 12205.78

X90Y0 AG9 4 IO_L02N_4/D0 FPGA_DO 6285.75

X90Y0 AH9 4 IO_L02P_4/D1 FPGA_D1 7853.38

X88Y0 AK6 4 IO_L03N_4/D2 FPGA_D2 11359.7

X88Y0 AK7 4 IO_L03P_4/D3 FPGA_D3 11413.02

X86Y0 AF10 4 IO_l05_4/No_Pair GND 5273.75


SliceCoordinates

PinNumbers

Virtex-II ProBank

Number

PackageFunctional

Name

I/OPin

Names

PackageFlightTimes

(In Microns)




X86Y0 AL7 4 IO_L06N_4/VRP_4 GND 12583.91

X86Y0 AM7 4 IO_L06P_4/VRN_4 GND 13750.42

X84Y0 AE11 4 IO_L07N_4 GND 3596.07

X84Y0 AF11 4 IO_L07P_4/VREF_4 GND 4532.67

X84Y0 AG10 4 IO_L08N_4 RS232_R1OUT 7946.43

X84Y0 AH10 4 IO_L08P_4 RS232_T1IN 8820.26

X82Y0 AK8 4 IO_L09N_4 GND 11291.37

X82Y0 AL8 4 IO_L09P_4/VREF_4 GND 11372.97

X80Y0 AE13 4 IO_L37N_4 GND 2723.68

X80Y0 AF13 4 IO_L37P_4 GND 3918.86

X80Y0 AG13 4 IO_L38N_4 USER1_PB 8007.13

X80Y0 AH13 4 IO_L38P_4 GND 8774.61

X78Y0 AJ11 4 IO_L39N_4 GND 8630.23

X78Y0 AK11 4 IO_L39P_4 GND 9736.03

X72Y0 AE14 4 IO_L43N_4 GND 3696.3

X72Y0 AF14 4 IO_L43P_4 USER2_PB 5289.64

X72Y0 AJ13 4 IO_L44N_4 GND 9198.92

X72Y0 AK13 4 IO_L44P_4 GND 10605.95

X70Y0 AL11 4 IO_L45N_4 GND 10900.17

X70Y0 AM11 4 IO_L45P_4/VREF_4 GND 12224.04

X68Y0 AE15 4 IO_L46N_4 USER2_LED 3132.45

X68Y0 AF15 4 IO_L46P_4 USER1_LED 3969.05

X68Y0 AG14 4 IO_L47N_4 GND 8129.77

X68Y0 AH14 4 IO_L47P_4 GND 9100.75

X66Y0 AL13 4 IO_L48N_4 BANK4_LA1 9870.11

X66Y0 AL12 4 IO_L48P_4 BANK4_LA2 11409.38

X64Y0 AD16 4 IO_L49N_4 BANK4_LA3 2710.75

X64Y0 AE16 4 IO_L49P_4 BANK4_LA4 3442.92

X64Y0 AJ14 4 IO_L50_4/No_Pair GND 8953.05

X62Y0 AK14 4 IO_L53_4/No_Pair GND 9556.17

X62Y0 AM14 4 IO_L54N_4 BANK4_LA5 12003.32

X62Y0 AM13 4 IO_L54P_4 BANK4_LA6 12348.43

X60Y0 AF16 4 IO_L55N_4 BANK4_LA7 3887.4

X60Y0 AG16 4 IO_L55P_4 BANK4_LA8 4909.89


SliceCoordinates

PinNumbers

Virtex-II ProBank

Number

PackageFunctional

Name

I/OPin

Names

PackageFlightTimes

(In Microns)



R

X60Y0 AH15 4 IO_L56N_4 BANK4_LA9 7000

X60Y0 AJ15 4 IO_L56P_4 BANK4_LA10 8217.31

X58Y0 AL14 4 IO_L57N_4 GND 10563


X56Y0 AD17 4 IO_L67N_4 BANK4_LA11 2503.07

X56Y0 AE17 4 IO_L67P_4 BANK4_LA12 3464.19

X56Y0 AH16 4 IO_L68N_4 BANK4_LA13 7362.9

X56Y0 AJ16 4 IO_L68P_4 BANK4_LA14 9128.85

X54Y0 AK16 4 IO_L69N_4 BANK4_LA15 9447.56


X48Y0 AF17 4 IO_L73N_4 BANK4_LA16

X48Y0 AG17 4 IO_L73P_4 BANK4_LACLK

X46Y0 AH17 4 IO_L74N_4/GCLK3S OSC_200M_N

X46Y0 AJ17 4 IO_L74P_4/GCLK2P OSC_200M_P

X46Y0 AK17 4 IO_L75N_4/GCLK1S OSC_250M_N

X46Y0 AL17 4 IO_L75P_4/GCLK0P OSC_250M_P

X44Y0 AL18 5 IO_L75N_5/GCLK7S EXTCLK1_N

X44Y0 AK18 5 IO_L75P_5/GCLK6P EXTCLK1_P

X44Y0 AJ18 5 IO_L74N_5/GCLK5S GND

X44Y0 AH18 5 IO_L74P_5/GCLK4P GND

X42Y0 AG18 5 IO_L73N_5 TRST#

X42Y0 AF18 5 IO_L73P_5 HALT#

X36Y0 AL19 5 IO_L69N_5/VREF_5 GND

X36Y0 AK19 5 IO_L69P_5 SYSACE_MPCE#

X34Y0 AJ19 5 IO_L68N_5 SYSACE_MPOE#

X34Y0 AH19 5 IO_L68P_5 SYSACE_MPBIRQ

X34Y0 AE18 5 IO_L67N_5 SYSACE_MPWE#

X34Y0 AD18 5 IO_L67P_5 SYSACE_MPBRDY

X32Y0 AL20 5 IO_L57N_5/VREF_5 SYSACE_CLK

X32Y0 AL21 5 IO_L57P_5 SYSACE_MPA6

X30Y0 AJ20 5 IO_L56N_5 SYSACE_MPA5

X30Y0 AH20 5 IO_L56P_5 SYSACE_MPA4

X30Y0 AG19 5 IO_L55N_5 SYSACE_MPA3


SliceCoordinates

PinNumbers

Virtex-II ProBank

Number

PackageFunctional

Name

I/OPin

Names

PackageFlightTimes

(In Microns)




X30Y0 AF19 5 IO_L55P_5 SYSACE_MPA2

X28Y0 AM22 5 IO_L54N_5 SYSACE_MPA1

X28Y0 AM21 5 IO_L54P_5 SYSACE_MPA0

X28Y0 AK21 5 IO_L53_5/No_Pair SYSACE_MPD7

X26Y0 AJ21 5 IO_L50_5/No_Pair SYSACE_MPD6

X26Y0 AE19 5 IO_L49N_5 SYSACE_MPD5

X26Y0 AD19 5 IO_L49P_5 SYSACE_MPD4

X24Y0 AL23 5 IO_L48N_5 SYSACE_MPD3 11409.38

X24Y0 AL22 5 IO_L48P_5 SYSACE_MPD2 9870.11

X22Y0 AH21 5 IO_L47N_5 SYSACE_MPD1 9029.19

X22Y0 AG21 5 IO_L47P_5 SYSACE_MPD0 8186.49

X22Y0 AF20 5 IO_L46N_5 GND 3969.05

X22Y0 AE20 5 IO_L46P_5 GND 3132.45

X20Y0 AM24 5 IO_L45N_5/VREF_5 GND 12224.04

X20Y0 AL24 5 IO_L45P_5 GND 10900.17

X18Y0 AK22 5 IO_L44N_5 GND 10795.23

X18Y0 AJ22 5 IO_L44P_5 GND 9429.62

X18Y0 AF21 5 IO_L43N_5 GND 5289.64

X18Y0 AE21 5 IO_L43P_5 MASTER_RESET# 3696.3

X12Y0 AK24 5 IO_L39N_5 GND 9736.03

X12Y0 AJ24 5 IO_L39P_5 GND 8630.23

X10Y0 AH22 5 IO_L38N_5 GND 8786.32

X10Y0 AG22 5 IO_L38P_5 LCD_R_W# 8056.83

X10Y0 AF22 5 IO_L37N_5 LCD_RS 3918.86

X10Y0 AE22 5 IO_L37P_5 LCD_E 2723.68

X8Y0 AL27 5 IO_L09N_5/VREF_5 GND 11372.97

X8Y0 AK27 5 IO_L09P_5 LCD_DB7 11420.7

X6Y0 AH25 5 IO_L08N_5 LCD_DB6 8344.01

X6Y0 AG25 5 IO_L08P_5 LCD_DB5 7652.81

X6Y0 AF24 5 IO_L07N_5/VREF_5 LCD_DB4 4532.67

X6Y0 AE24 5 IO_L07P_5 LCD_DB3 3596.07

X4Y0 AM28 5 IO_L06N_5/VRP_5 LCD_DB2 13858.11

X4Y0 AL28 5 IO_L06P_5/VRN_5 LCD_DB1 12527.75

X4Y0 AF25 5 IO_L05_5/No_Pair LCD_DB0


SliceCoordinates

PinNumbers

Virtex-II ProBank

Number

PackageFunctional

Name

I/OPin

Names

PackageFlightTimes

(In Microns)



R

X2Y0 AK28 5 IO_L03N_5/D4 FPGA_D4

X2Y0 AK29 5 IO_L03P_5/D5 FPGA_D5

X0Y0 AH26 5 IO_L02N_5/D6 FPGA_D6

X0Y0 AG26 5 IO_L02P_5/D7 FPGA_D7

X0Y0 AL29 5 IO_L01N_5/RDWR_B FPGA_RDWR#

X0Y0 AL30 5 IO_L01P_5/CS_B FPGA_CS#

X0Y0 AJ30 6 IO_L01P_6/VRN_6 R122/C373 10985.88

X0Y1 AJ31 6 IO_L01N_6/VRP_6 R97/C434 11321.01

X1Y0 AJ27 6 IO_L02P_6 QDR_K_n_A 10529.58

X1Y1 AJ28 6 IO_L02N_6 QDR_K_A 11720.34

X1Y2 AK31 6 IO_L03P_6 R_n_ext_A 12761.57

X1Y3 AK32 6 IO_L03N_6/VREF_6 Vref(0.9V) 12802.28

X0Y4 AH29 6 IO_L04P_6 QDR_BW_n_A0 9308.27

X0Y5 AH30 6 IO_L04N_6 QDR_BW_n_A1 9452.34

X1Y4 AH27 6 IO_L05P_6 QDR_BW_n_A2 8891.47

X1Y5 AG28 6 IO_L05N_6 QDR_BW_n_A3 9638.17

X1Y6 AL33 6 IO_L06P_6 QDR_C_n_A 15583.83

X1Y7 AL34 6 IO_L06N_6 QDR_C_A 15821.97

X0Y8 AF31 6 IO_L31P_6 QDR_W_n_A 10021.36

X0Y9 AF32 6 IO_L31N_6 QDR_R_n_A 10624.52

X1Y8 AC25 6 IO_L32P_6 GND 3336.69

X1Y9 AC26 6 IO_L32N_6 GND 4005.01

X1Y10 AG33 6 IO_L33P_6 GND 12391.44

X1Y11 AG34 6 IO_L33N_6/VREF_6 Vref(0.9V) 12986.31

X0Y12 AE30 6 IO_L34P_6 GND 8811.79

X0Y13 AE31 6 IO_L34N_6 GND 9342.05

X1Y12 AD27 6 IO_L35P_6 GND 5651.11

X1Y13 AD28 6 IO_L35N_6 QDR_DWRITE_A35 6675.24

X1Y14 AF33 6 IO_L36P_6 QDR_DWRITE_A34 11948.48

X1Y15 AE33 6 IO_L36N_6 QDR_DWRITE_A33 11537.91

X0Y16 AD29 6 IO_L37P_6 QDR_DWRITE_A32 8070.54


X1Y16 AB25 6 IO_L38P_6 QDR_DWRITE_A30 2906.72


SliceCoordinates

PinNumbers

Virtex-II ProBank

Number

PackageFunctional

Name

I/OPin

Names

PackageFlightTimes

(In Microns)




X1Y17 AB26 6 IO_L38N_6 QDR_DWRITE_A29 3854.3


X1Y19 AD32 6 IO_L39N_6/VREF_6 Vref(0.9V) 9751.53

X0Y20 AC28 6 IO_L40P_6 QDR_DWRITE_A27 5779.09

X0Y21 AC29 6 IO_L40N_6 QDR_DWRITE_A26 6521.49



X1Y22 AE34 6 IO_L42P_6 QDR_DWRITE_A23 12534.09



X0Y25 AC32 6 IO_L43N_6 QDR_DWRITE_A20 9702.33

X1Y24 AA25 6 IO_L44P_6 QDR_DWRITE_A19 2717.14

X1Y25 AA26 6 IO_L44N_6 QDR_DWRITE_A18 3704.71


X1Y27 AC33 6 IO_L45N_6/VREF_6 Vref(0.9V) 10601.93









X1Y32 Y25 6 IO_L50P_6 QDR_DWRITE_A8 2606.42

X1Y33 Y26 6 IO_L50N_6 QDR_DWRITE_A7 3554


X1Y35 AB34 6 IO_L51N_6/VREF_6 Vref(0.9V) 12006.27



X1Y36 W25 6 IO_L53P_6 QDR_DWRITE_A3 2590.48

X1Y37 W26 6 IO_L53N_6 QDR_DWRITE_A2 3619.48



X0Y40 Y28 6 IO_L55P_6 GND 5219.05


SliceCoordinates

PinNumbers

Virtex-II ProBank

Number

PackageFunctional

Name

I/OPin

Names

PackageFlightTimes

(In Microns)



R

X0Y41 Y29 6 IO_L55N_6 GND 5961.45

X1Y40 W27 6 IO_L56P_6 GND 4826.38

X1Y41 W28 6 IO_L56N_6 GND 5773.96

X1Y42 Y31 6 IO_L57P_6 QDR_SA_A17 8145.63

X1Y43 Y32 6 IO_L57N_6/VREF_6 Vref(0.9V) 8909.69

X0Y44 W29 6 IO_L58P_6 QDR_SA_A16 5936.59

X0Y45 W30 6 IO_L58N_6 QDR_SA_A15 6678.99

X1Y44 W24 6 IO_L59P_6 QDR_SA_A14 1610.19

X1Y45 V24 6 IO_L59N_6 QDR_SA_A13 1638.53

X1Y46 AA34 6 IO_L60P_6 QDR_SA_A12 11691.6

X1Y47 Y34 6 IO_L60N_6 QDR_SA_A11 11148.48

X0Y48 W31 6 IO_L85P_6 QDR_SA_A10 8159.47

X0Y49 W32 6 IO_L85N_6 QDR_SA_A9 8919.9

X1Y48 V25 6 IO_L86P_6 QDR_SA_A8 2405.17

X1Y49 V26 6 IO_L86N_6 QDR_SA_A7 3327.27

X1Y50 Y33 6 IO_L87P_6 QDR_SA_A6 10611.96

X1Y51 W33 6 IO_L87N_6/VREF_6 Vref(0.9V) 9812.03

X0Y52 V29 6 IO_L88P_6 QDR_SA_A5 5998.02

X0Y53 V30 6 IO_L88N_6 QDR_SA_A4 6547.9

X1Y52 V27 6 IO_L89P_6 QDR_SA_A3 4483.54

X1Y53 V28 6 IO_L89N_6 QDR_SA_A2 5407.06

X1Y54 V31 6 IO_L90P_6 QDR_SA_A1 7799.59

X1Y55 V32 6 IO_L90N_6 QDR_SA_A0 8537.7

X0Y56 U32 7 IO_L90P_7 GND 8839.91

X0Y57 U31 7 IO_L90N_7 GND 7626.14

X0Y58 U28 7 IO_L89P_7 QDR_DREAD_A0 5511.92

X0Y59 U27 7 IO_L89N_7 QDR_DREAD_A1 4393.22

X1Y58 V33 7 IO_L88P_7 GND 10394.2

X1Y59 U33 7 IO_L88N_7/VREF_7 Vref(0.9V) 9665.64






SliceCoordinates

PinNumbers

Virtex-II ProBank

Number

PackageFunctional

Name

I/OPin

Names

PackageFlightTimes

(In Microns)




X1Y62 T32 7 IO_L85P_7 QDR_DREAD_A6 9056.44

X1Y63 T31 7 IO_L85N_7 QDR_DREAD_A7 7724.5

X0Y64 T30 7 IO_L60P_7 GND 7055.3

X0Y65 T29 7 IO_L60N_7 GND 6031.43

X0Y66 T28 7 IO_L59P_7 GND 5872.43

X0Y67 T27 7 IO_L59N_7 GND 4753.73

X1Y66 T33 7 IO_L58P_7 QDR_CQ_A 10173.21

X1Y67 R33 7 IO_L58N_7/VREF_7 Vref(0.9V) 9961.47

X0Y68 R32 7 IO_L57P_7 QDR_DREAD_A8 9271.49

X0Y69 R31 7 IO_L57N_7 QDR_DREAD_A9 8013.89

X0Y70 T26 7 IO_L56P_7 QDR_DREAD_A10 3871.63



X1Y71 P34 7 IO_L55N_7 QDR_DREAD_A13 11291.77





X1Y74 P32 7 IO_L52P_7 GND 9339.48

X1Y75 P31 7 IO_L52N_7/VREF_7 Vref(0.9V) 8102.88

X0Y76 P30 7 IO_L51P_7 GND 7603.44

X0Y77 P29 7 IO_L51N_7 GND 6499.99



X1Y78 P33 7 IO_L49P_7 QDR_DREAD_A20 10530.82

X1Y79 N33 7 IO_L49N_7 QDR_DREAD_A21 10426.76

X0Y80 N32 7 IO_L48P_7 QDR_DREAD_A22 9778.21


X0Y82 P28 7 IO_L47P_7 QDR_DREAD_A24 5954.75

X0Y83 P27 7 IO_L47N_7 QDR_DREAD_A25 4770.58

X1Y82 N34 7 IO_L46P_7 GND 11804.99

X1Y83 M34 7 IO_L46N_7/VREF_7 Vref(0.9V) 11667.8

X0Y84 N30 7 IO_L45P_7 GND 7563.61

X0Y85 N29 7 IO_L45N_7 GND 6306.01


SliceCoordinates

PinNumbers

Virtex-II ProBank

Number

PackageFunctional

Name

I/OPin

Names

PackageFlightTimes

(In Microns)



R

X0Y86 P26 7 IO_L44P_7 GND 3823

X0Y87 P25 7 IO_L44N_7 GND 2638.82

X1Y86 M32 7 IO_L43P_7 QDR_CQ_n_A 9772.91

X1Y87 M31 7 IO_L43N_7 GND 8536.05

X0Y88 L32 7 IO_L42P_7 QDR_DREAD_A26 10259.17

X0Y89 L31 7 IO_L42N_7 QDR_DREAD_A27 9001.57



X1Y90 M33 7 IO_L40P_7 GND 12186.54

X1Y91 L33 7 IO_L40N_7/VREF_7 Vref(0.9V) 11195.56

X0Y92 M29 7 IO_L39P_7 QDR_DREAD_A30 6975.04

X0Y93 M28 7 IO_L39N_7 QDR_DREAD_A31 5610.09



X1Y94 L34 7 IO_L37P_7 QDR_DREAD_A34 12451.17

X1Y95 K34 7 IO_L37N_7 QDR_DREAD_A35 12423.45

X0Y96 L30 7 IO_L36P_7 GND 8143.52

X0Y97 L29 7 IO_L36N_7 R_n_int_A 7340.48

X0Y98 L28 7 IO_L35P_7 GND 6793.53

X0Y99 L27 7 IO_L35N_7 GND 5592.79

X1Y98 K33 7 IO_L34P_7 GND 11352.59


X0Y100 K31 7 IO_L33P_7 GND 9537.04

X0Y101 K30 7 IO_L33N_7 GND 8267.43

X0Y102 M26 7 IO_L32P_7 GND 4123.3

X0Y103 M25 7 IO_L32N_7 GND 3062.48

X1Y102 H34 7 IO_L31P_7 GND 13451.41

X1Y103 H33 7 IO_L31N_7 GND 12137.04

X0Y104 F31 7 IO_L06P_7 GND 11858.77

X0Y105 F30 7 IO_L06N_7 GND 10666.81

X0Y106 J28 7 IO_L05P_7 GND 7292.33

X0Y107 J27 7 IO_L05N_7 GND 6469.14

X1Y106 E34 7 IO_L04P_7 GND 15132.61

X1Y107 E33 7 IO_L04N_7/VREF_7 Vref(0.9V) 13663.12


SliceCoordinates

PinNumbers

Virtex-II ProBank

Number

PackageFunctional

Name

I/OPin

Names

PackageFlightTimes

(In Microns)




X0Y108 E32 7 IO_L03P_7 GND 13396.34

X0Y109 E31 7 IO_L03N_7 GND 11802.85

X0Y110 F28 7 IO_L02P_7 GND 11146.23

X0Y111 F27 7 IO_L02N_7 GND 12438.46

X1Y110 D34 7 IO_L01P_7/VRN_7 R98/C374 15547.77

X1Y111 D33 7 IO_L01N_7/VRP_7 R99/C435 14050.12

J26 PROG_B PROG_B

K25 HSWAP_EN HSWAP

K26 DXP

G27 DXN

G8 RSVD

K9 VBATT GND

K10 TMS JTAG_TMS

J9 TCK JTAG_TCK

H7 DO FPGA_TDO

AE9 CCLK FPGA_CCLK

AF9 PWRDWN_B PWRDWN

AE10 DONE FPGA_DONE

AE25 M2 M2

AF26 M0 M0

AE26 M1 M1

H28 TDI FPGA_TDI

A29 TXNPAD4

A28 TXPPAD4

A27 RXPPAD4

A26 RXNPAD4

A21 TXNPAD6

A20 TXPPAD6

A19 RXPPAD6

A18 RXNPAD6

A17 TXNPAD7

A16 TXPPAD7

A15 RXPPAD7


SliceCoordinates

PinNumbers

Virtex-II ProBank

Number

PackageFunctional

Name

I/OPin

Names

PackageFlightTimes

(In Microns)



R

A14 RXNPAD7

A9 TXNPAD9

A8 TXPPAD9

A7 RXPPAD9

A6 RXNPAD9

AP6 RXNPAD16

AP7 RXPPAD16

AP8 TXPPAD16

AP9 TXNPAD16

AP14 RXNPAD18

AP15 RXPPAD18

AP16 TXPPAD18

AP17 TXNPAD18

AP18 RXNPAD19

AP19 RXPPAD19

AP20 TXPPAD19

AP21 TXNPAD19

AP26 RXNPAD21

AP27 RXPPAD21

AP28 TXPPAD21

AP29 TXNPAD21


SliceCoordinates

PinNumbers

Virtex-II ProBank

Number

PackageFunctional

Name

I/OPin

Names

PackageFlightTimes

(In Microns)






R

Appendix 3

Memory Board Schematics and Characterization Results

This section provides schematics for the ML365 Virtex II QDR SRAM Memory Demonstration Board, as well as characterization results.

SchematicsThe pages that follow show the schematics for the ML365 Memory board:



Appendix 3: Memory Board Schematics and Characterization ResultsR

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Title

Size

Document Number

Rev

Date:

Sheet

of

<Doc>

12

ML365 QD

R II SRAM Interface Board

B

128

05/17/04 1

0:25:18

Notes Page

Sheet# Rev# Description

2 0 Top Hierarchical Block Diagram

3 0 Clock Sources: Epson EC2121CA OSC, SMA’s

4 3 SystemAce Controller & CF Socket, JTAG Conn.

22 0 LCD I/F Connector, MC74LCX541D level shifters

24 0 Power: +5V, +3.3V, +2.5V, +1.5V

26 9 Decoupling Caps for FPGA and QDR

5 8 QDRII Samsung K7R323684M-FC20 SRAM 1 (A)

23 0 RS232 I/F MAX3316ECUP 2.5V & DB9F Serial Connector

11 11 XC2VP20 Bank 0 VCCo=+1.8V, VRef=+0.9V_FPGA

Highest Ref. Des. #:

Latest Schematic Rev.: 12, on Date 03/15/2004

27 10 Additional Decoupling Caps

Revision Notes are on Sheet 28

28 12 Rev. Notes

1 12 Notes Page

6 5 QDRII SRAM 1 Termination Resistors

8 5 QDRII SRAM 2 Termination Resistors placeholder

10 5 QDRII SRAM 3 Termination Resistors placeholder




15 12 XC2VP20 Bank 4 RS232 I/F & User PB/LED VCCo=+2.5V, VRef=None

16 5 XC2VP20 Bank 5 SystemACE I/F, LCD I/F, SelectMAP header VCCo=+2.5V, VRef=None

17 11 XC2VP20 Bank 6 QDRII SRAM 1 DWRITE & ADDRESS I/F VCCo=+1.8V, VRef=+0.9V_FPGA

18 11 XC2VP20 Bank 7 QDRII SRAM 1 DREAD I/F VCCo=+1.8V, Vref=+0.9V_FPGA

19 5 XC2VP20 Config Block, XCONFIG Conn., JTAG jumpers, VCCINT, VCCAUX, GND blocks

20 0 XC2VP20 MGT’s not used, wired to +2.5V

21 0 XC2VP20 No Connect blocks, wired to GND

R538

C435

L5J5 P47

U13

Q8 SW8

D11

Y3

7 8 QDRII Samsung K7R323684M-FC20 SRAM 2 (B)

9 8 QDRII Samsung K7R323684M-FC25 SRAM 3 (C)

25 5 Power: +1.8V, +0.9V_QDR, +0.9V_FPGA



SchematicsR

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

+3.3V

+5V

GND_SIGNAL

GND_SIGNAL

GND_SIGNAL

GND_SIGNAL

GND_SIGNAL

+3.3V

GND_SIGNAL

+1.8V

+1.5V

+0.9V_QDR

+5V

+0.9V_QDR

+1.8V

GND_SIGNAL

+2.5V

+2.5V

+0.9V_FPGA

+5V

+3.3V

+1.5V

+1.8V

+2.5V

+2.5V

+0.9v_FPGA

+2.5V

QDR_C_n_A

SYSACE_CFGPROG#

SYSACE_MPA[6:0]

QDR_W

_n_A

LCD_RS

QDR_CQ_n

_A

SYSACE_CFGINIT#

SYSACE_MPWE#

QDR_K_A

QDR_SA_A[17:0]

SYSACE_MPBIRQ

LCD_E

TMS

QDR_BW_n_A[3:0]

QDR_DREAD_A[35:0]

LCD_R_W#

QDR_DW

RITE_A[35:0]

FPGA_TDO

QDR_CQ_A

RS232_T1IN

QDR_C_A

SYSACE_MPOE#

RS232_R1OUT

SYSACE_TDO

SYSACE_MPD[7:0]

LCD_DB[7:0]

SYSACE_MPCE#

QDR_K_n_A

QDR_R_n_A

TCK

SYSACE_MPBRDY

TRST#HALT#

+3.3V

OSC_250M_N

OSC_250M_P

OSC_200M_N

OSC_200M_P

EXTCLK1_N

EXTCLK1_P

QDR_C_B

QDR_C_n_B

QDR_CQ_B

QDR_CQ_n

_B

QDR_K_n_B

QDR_K_B

QDR_R_n_B

QDR_W

_n_B

QDR_BW_n_B[3:0]

QDR_SA_B[17:0]

QDR_DW

RITE_B[35:0]

QDR_DREAD_B[35:0]

QDR_DREAD_C[35:0]QDR_DWRITE_C[35:0]QDR_SA_C[17:0]

QDR_BW_n_C[3:0]

QDR_CQ_n_CQDR_CQ_C

QDR_C_CQDR_C_n_C

QDR_K_n_CQDR_K_C

QDR_R_n_CQDR_W_n_C

+1.8V

GND_SIGNAL

+1.8V

+0.9V_QDR

GND_SIGNAL

+0.9V_QDR

Title

Size

Document Number

Rev

Date:

Sheet

of

<Doc>

0

ML365 QD


B

228

01/22/04 0

9:07:48

V2Pro QDR Board Top

Seiko L167100J000

Samsung K7R323684M-FC20

SystemAce



AB

C

QDR1

QDR_DREAD_A[35:0]

QDR_DWRITE_A[35:0]

QDR_SA_A[17:0]

QDR_W_n_A

QDR_R_n_A

QDR_CQ_n_AQDR_CQ_A

QDR_C_AQDR_C_n_A

QDR_K_A

QDR_K_n_A

GND_SIGNAL

+1.8V

+0.9V_QDR

QDR_BW_n_A[3:0]

CONFIG_EEPROM

SYSACE_MPD[7:0]SYSACE_MPA[6:0]SYSACE_MPWE#SYSACE_MPOE#SYSACE_MPCE#

SYSACE_TDO

TMSTCK

FPGA_TDO

SYSACE_CFGINIT#SYSACE_CFGPROG#

SYSACE_MPBIRQSYSACE_MPBRDY

+3.3V

GND_SIGNAL

SYSACE_CLK

+2.5V

TRST#HALT#

CLOCKS

+2.5V

GND_SIGNAL

EXTCLK1_PEXTCLK1_N

OSC_200M_POSC_200M_N

OSC_250M_POSC_250M_N

POWER_IF

+5V

+3.3V

+1.8V

GND_SIGNAL

+1.5V

+0.9V_FPGA

+0.9V_QDR

+2.5V

V2PRO_XC2VP20_FF1152

OSC_200M_P

OSC_200M_N

OSC_250M_P

OSC_250M_N

EXTCLK1_N

EXTCLK1_P

SYSACE_CLKSYSACE_MPD[7:0]SYSACE_MPA[6:0]SYSACE_MPWE#SYSACE_MPOE#SYSACE_MPCE#SYSACE_CFGINIT#SYSACE_CFGPROG#SYSACE_MPBIRQSYSACE_MPBRDY

SYSACE_TDO

TMSTCK

FPGA_TDO

RS232_T1INRS232_R1OUT

LCD_DB[7:0]LCD_ELCD_R_W#LCD_RS

QDR_DREAD_A[35:0]

QDR_DWRITE_A[35:0]

QDR_SA_A[17:0]

QDR_BW_n_A[3:0]

QDR_W_n_A

QDR_R_n_A

QDR_K_n_A

QDR_C_n_A

QDR_CQ_n_A

QDR_K_A

QDR_C_A

QDR_CQ_A

+2.5V

+1.5V

+1.8V

+5V

+3.3V

GND_SIGNAL

+0.9V_FPGA

TRST#HALT#

QDR_DREAD_B[35:0]

QDR_DWRITE_B[35:0]

QDR_SA_B[17:0]

QDR_BW_n_B[3:0]

QDR_W_n_B

QDR_R_n_B

QDR_K_B

QDR_K_n_B

QDR_C_B

QDR_C_n_B

QDR_CQ_n_B

QDR_CQ_B

QDR_DREAD_C[35:0]QDR_DWRITE_C[35:0]

QDR_SA_C[17:0]

QDR_BW_n_C[3:0]

QDR_C_CQDR_C_n_C

QDR_W_n_CQDR_R_n_C

QDR_K_n_CQDR_K_C

QDR_CQ_n_CQDR_CQ_C

LCD

LCD_RS

LCD_R_W#

LCD_E

LCD_DB[7:0]

+5V

GND_SIGNAL

+3.3V

RS232_DRIVER

RS232_T1IN

RS232_R1OUT

GND_SIGNAL

+2.5V

QDR2

QDR_DREAD_B[35:0]

QDR_DWRITE_B[35:0]

QDR_SA_B[17:0]

QDR_BW_n_B[3:0]

QDR_W_n_B

QDR_R_n_B

QDR_K_B

QDR_K_n_B

QDR_CQ_BQDR_CQ_n_B

QDR_C_n_BQDR_C_B

GND_SIGNAL+0.9V_QDR

+1.8V

QDR3

QDR_DREAD_C[35:0]

QDR_DWRITE_C[35:0]

QDR_SA_C[17:0]

QDR_BW_n_C[3:0]

QDR_CQ_C

QDR_CQ_n_C

QDR_W_n_C

QDR_R_n_C

QDR_K_C

QDR_K_n_C

QDR_C_n_C

QDR_C_C

+1.8V+0.9V_QDRGND_SIGNAL




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

OSC_200M_N

OSC_250M_P

OSC_250M_N

EXTCLK1_P

EXTCLK1_N

OSC_200M_P

+2.5V

GND_SIGNAL

EXTCLK1_P

EXTCLK1_N

OSC_200M_N

OSC_200M_P

OSC_250M_N

OSC_250M_P

+2.5V

+2.5V

+2.5V

Title

Size

Document Number

Rev

Date:

Sheet

of

<Doc>

0

ML365 QD


B

328

01/22/04 0

9:07:44

CLOCKS

Differential Inputs for Test Equip. clock

PECL

out

SMT

LCC

pack

age

EG21

21CA

200.

0000M-PHPAB

200M

Hz

PECL

out

SMT

LCC

pack

age

EG21

21CA

250.

0000M-PHPAB

250M

Hz

250M

Hz

50 ohm term. R’s at FPGA Bank4

50 ohm term. R’s at FPGA Bank5

C50.01uF

C60.01uF

R815

C1

0.1uF

C2

0.1uF

Y1

200.000MHz

OE

1

NC

2

GND

3OUT

4/OUT

5VCC

6

J2 CON_SMB_ST

2 3 4 5

1

Y2

250.000MHz

OE

1

NC

2

GND

3OUT

4/OUT

5VCC

6

C43.3uF

J1 CON_SMB_ST

2 3 4 5

1

C33.3uF

R24.7K

R14.7K

R715



SchematicsR

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

SYSACE_CLK

SYSACE_CLK

SYSACE_TDO

TMS

TCK

FPGA_TDO

SYSACE_MPD7

SYSACE_MPD6

SYSACE_MPD5

SYSACE_MPD4

SYSACE_MPD3

SYSACE_MPD2

SYSACE_MPD1

SYSACE_MPD0

SYSACE_MPD

[7:0]

SYSACE_MPA5

SYSACE_MPA6

SYSACE_MPA3

SYSACE_MPA4

SYSACE_MPA2

SYSACE_MPA0

SYSACE_MPA1

SYSACE_MPA[6:0]

SYSACE_MPBRDY

SYSACE_MPIRQ

SYSACE_MPWE#

SYSACE_MPO

E#

SYSACE_MPC

E#

SYSACE_TSTTDO

SYSACE_TSTTDI

SYSACE_TSTTDO

SYSACE_TSTTMS

SYSACE_TSTTCK

TRST#

POWER_IS_ON

HALT#

SYSACE_TSTTMS

SYSACE_TSTTCK

SYSACE_TSTTDI

+2.5V

SYSACE_MPWE#

SYSACE_MPO

E#

SYSACE_MPC

E#

SYSACE_MPD

[7:0]

SYSACE_MPBRDY

SYSACE_MPBIRQ

SYSACE_MPA[6:0]

FPGA_TDO

SYSACE_TDO

TMS

TCK

SYSACE_CFGPROG#

SYSACE_CFGINIT#

SYSACE_CLK

TRST#

HALT#

+3.3V

GND_SIGNAL

+2.5V

+3.3V

+3.3V

+2.5V

+3.3V

+2.5V

+2.5V

+2.5V

+3.3V

+3.3V

+3.3V

+2.5V

Title

Size

Document Number

Rev

Date:

Sheet

of

<Doc>

3

ML365 QD


B

428

01/22/04 0

9:07:46

CONFIG via SystemAce CF

SG-8

002C

A 3.

3V CMOS

16-bit mode not supported

CFPROG# goes to PROG_B

CFGINIT# comes from INIT_B

CFPROG = O.C. output

MOM.

PB

FOR

SysA

ce R

ESET

SYSA

CE_C

LK 2

.5V

sign

al excursion

cons

trai

nt R

’s (

copi

ed f

rom ML300 pcb)

Disable SysAce after RESET

R184.7K

R33

4.7K

R281K

+C7

3.3uF

1 2

R164.7K

P2

HEADER 1x21

2

R24

100

R31

4.7K

R114.7K

R194.7K

D1

RED

1 2

R26 15

R271K

R124.7K

R10

4.7K

P1

HEADER 8X22 4 6 8 10

12

14

16

1 3 5 7 911

13

15

SystemAce Controller

TQFP144

U1

SystemAce_Controller

VCCL110

VCCL215

VCCL325

VCCL457

VCCL584

VCCL694

VCCL799

VCCL8126

P91

P1017

P1137

P1255

P1373

P1492

P15109

P16128

RESET#33

POR_BYPASS108

POR_RESET72POR_TEST74

MPBRDY

39

MPIRQ

41

MPCE#

42

MPA04

45

MPA05

44

MPA06

43

MPD00

66

MPD01

65

MPD02

63

MPD03

62

MPD04

61

MPD05

60

MPD06

59

MPD07

58

MPD08

56

MPD09

53

MPD10

52

MPD11

51

MPD12

50

MPD13

49

MPD14

48

MPD15

47

MPA03

67

MPA02

68

MPA01

69

MPWE#

76

MPOE#

77

MPA00

70

CFCD2#

13

CFCD1#

103

CFD00

5CFD01

6CFD02

8CFD03

104

CFD04

106

CFD05

113

CFD06

115

CFD07

117

CFD08

7CFD09

11

CFD10

12

CFD11

105

CFD12

107

CFD13

114

CFD14

116

CFD15

118

CFA00

4CFA01

142

CFA02

141

CFA03

139

CFA04

137

CFA05

135

CFA06

134

CFA07

132

CFA08

130

CFA09

125

CFA10

121

CFCE2#

138

CFCE1#

119

CFREG#

3

CFWAIT#

140

CFGRSVD

133

CFWE#

131

CFOE#

123

CFGADDR0 86CFGADDR1 87CFGADDR2 88

CFGMODEPIN 89

TSTTDI 102TSTTCK 101TSTTMS 98TSTTDO 97

CFGTDO 82

CFGTMS 85

CFGTCK 80

CFGTDI 81

CFGPROG# 79CFGINIT# 78

GND1 9

GND2 18

GND3 26

GND4 35

GND5 46

GND6 54

GND7 64

GND8 75

GND10 91

GND13 111

GND9 83

GND11 100

GND12 110

GND14 112

GND15 120

GND16 129

GND17 136

GND18 144

NC1

2

NC2

14

NC3

16

NC4

19

NC5

20

NC6

21

NC7

22

NC8

23

NC9

24

NC10

27

NC11

28

NC12

29

NC13

30

NC19

143

NC20

127

NC21

124

NC22

122

NC23

90

NC24

71

NC25

40

NC18

38

NC17

36

NC16

34

NC15

32

NC14

31

ERRLED

96

STATLED

95

CLK

93

R134.7K

R204.7K

R32

4.7K

07

6 5

43

1 2

P1 P2 P4P8

SW2

SysAceAddr_RotarySW

2 51

634

R25

100

R291K

C80.1uF

C90.01uF

R15

1K

R14

1K

R224.7K

Y3

33.0000MHz

OE

1

GND

2OUT

3

VDD

4

P3

HDR_7x2_2MM

1 3 5 7 9

2 4 6 8 10

12

14

11

13

R17

4.7K

R230

J3

CF_Socket

CD2#

25

CD1#

26

CE1#

7CE2#

32

A09

10

A08

11

A07

12

A06

14

A05

15

A04

16

A03

17

A02

18

A01

19

A00

20

A10

8

D00

21

D01

22

D02

23

D03

2D04

3D05

4D06

5D07

6D08

47

D09

48

D10

49

D11

27

D12

28

D13

29

D14

30

D15

31

REG#

44

WAIT#

42

RDY/BSY#

37

WE#

36

OE#

9

VCC1

13

VCC2

38

IORD#

34

IOWR#

35

BVD2

45

BVD1

46

GND2

50

INPACK#

43

VS2#

40

VS1#

33

WP

24

GND1

1

CSEL#

39

RESET

41

MH1

51

MH2

52

MH3

53

MH4

54

MH5

55

MH6

56

MH7

57

MH8

58

MH9

59

MH10

60

R301K

D2

RED

1 2SW1

SW PUSHBUTTON

R94.7K

R214.7K




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

QDR_DREAD_A[35:0]

QDR_DR

EAD_A35

QDR_DR

EAD_A34

QDR_DR

EAD_A33

QDR_DR

EAD_A32

QDR_DR

EAD_A31

QDR_DR

EAD_A30

QDR_DR

EAD_A29

QDR_DR

EAD_A28

QDR_DR

EAD_A27

QDR_DR

EAD_A26

QDR_DR

EAD_A25

QDR_DR

EAD_A24

QDR_DR

EAD_A23

QDR_DR

EAD_A22

QDR_DR

EAD_A21

QDR_DR

EAD_A20

QDR_DR

EAD_A19

QDR_DR

EAD_A18

QDR_DR

EAD_A17

QDR_DR

EAD_A16

QDR_DR

EAD_A15

QDR_DR

EAD_A14

QDR_DR

EAD_A13

QDR_DR

EAD_A12

QDR_DR

EAD_A11

QDR_DR

EAD_A10

QDR_DREA

D_A9

QDR_DREA

D_A8

QDR_DREA

D_A7

QDR_DREA

D_A6

QDR_DREA

D_A5

QDR_DREA

D_A4

QDR_DREA

D_A3

QDR_DREA

D_A2

QDR_DREA

D_A1

QDR_DREA

D_A0

QDR_CQ_n

_A

QDR_CQ_A

QDR_A_DLL_n

QDR_A_ZQ

QDR_DWRITE_A5

QDR_DW

RITE_A29

QDR_DWRITE_A1

QDR_DWRITE_A8

QDR_DWRITE_A4

QDR_SA_A4

QDR_SA_A12

QDR_DWRITE_A0

QDR_DW

RITE_A28

QDR_DW

RITE_A25

QDR_SA_A8

QDR_DW

RITE_A24

QDR_DW

RITE_A34

QDR_DW

RITE_A14

QDR_SA_A17

QDR_DWRITE_A6

QDR_DW

RITE_A30

QDR_W

_n_A

QDR_DWRITE_A9

QDR_SA_A11

QDR_SA_A3

QDR_SA_A7

QDR_DW

RITE_A15

QDR_DW

RITE_A20

QDR_DW

RITE_A11

QDR_DW

RITE_A17

QDR_DW

RITE_A31

QDR_K_A

QDR_SA_A15

QDR_SA_A2

QDR_DW

RITE_A10

QDR_DWRITE_A2

QDR_DW

RITE_A35

QDR_SA_A6

QDR_SA_A0

QDR_DW

RITE_A26

QDR_DW

RITE_A16

QDR_SA_A10

QDR_DW

RITE_A18

QDR_DW

RITE_A32

QDR_DW

RITE_A12

QDR_DW

RITE_A19

QDR_R_n_A

QDR_SA_A16

QDR_SA_A13

QDR_SA_A1

QDR_DWRITE_A7

QDR_DWRITE_A3

QDR_DW

RITE_A22

QDR_SA_A5

QDR_DW

RITE_A27

QDR_SA_A9

QDR_SA_A[17:0]

QDR_DW

RITE_A13

QDR_DW

RITE_A33

QDR_DW

RITE_A21

QDR_DW

RITE_A23

QDR_K_n_A

QDR_SA_A14

QDR_C_A

QDR_C_n_A

QDR_BW_n_A0

QDR_BW_n_A1

QDR_BW_n_A2

QDR_BW_n_A3

QDR_BW_n_A[3:0]

QDR_BW_n_A0

QDR_BW_n_A1

QDR_BW_n_A2

QDR_BW_n_A3

QDR_DW

RITE_A[35:0]

QDR_SA_A[17:0]

QDR_DREAD_A[35:0]

QDR_DW

RITE_A[35:0]

QDR_R_n_A

QDR_K_A

QDR_K_n_A

QDR_W

_n_A

QDR_CQ_A

QDR_CQ_n

_A

+0.9V_QDR

+1.8V

GND_SIGNAL

QDR_C_A

QDR_C_n_A

QDR_BW_n_A[3:0]

+0.9V_QDR

+1.8V

+1.8V

+0.9V_QDR

+1.8V

+1.8V

+1.8V

+1.8V

+1.8V

QDR_SA_A[17:0]

+1.8V

QDR_WRITE_A[35:0]

Title

Size

Document Number

Rev

Date:

Sheet

of

<Doc>

8

ML365 QD


B

528

01/22/04 0

9:07:43

QDRII SRAM 1

ZQ i

mped

ance

"tu

ning

" set to 50 ohms

P6.1

to

P6.2

= D

LL e

nabl

edP6

.3 t

o P6

.2 =

DLL off

P7.1

to

P7.2

= min. Z

P7.3

to

P7.2

= 5

0 ohm Z

200MHz -FC20

C367

0.1uF

R471100

R42

1K

R465100

R39

0

P6

HEADER 3

1 2 3

R461100

R40 0

P7

HEADER 3

1 2 3

R467100

R472100

R460100

R462100R466100

R277100

R468100

R473100

R276100

R278100

R463100R279100

R469100

R470100

R280100R464100

R41 0

K7R3

2368

4MFBGA 165

1M x

36

4-wo

rd b

urst

U5

K7R323684M

TDO

R1

TDI

R11

TCK

R2

TMS

R10

/DoffH1

VREF1

H2

VDDQ1

H3

VDDQ2

E4

VDDQ3

F4

VDDQ4

G4

VDDQ5

H4

VDDQ6

J4

VDDQ7

K4

VDDQ9

E8

VDDQ10

F8

VDDQ11

G8

VDDQ12

H8

VDDQ13

J8

VDDQ14

K8

VDDQ15

L8

VDDQ16

H9

VDDQ8

L4

VREF2

H10

ZQ

H11

NC_SA_64Mb

A3

SA0

B4

SA2

C5

SA3

C7

SA1

B8

SA17

A9

SA11

R3

SA12

R4

SA7

P4

SA4

N5

SA8

P5

SA13

R5

SA5

N6

SA6

N7

SA9

P7

SA14

R7

SA15

R8

SA10

P8

CQ

A11

/CQ

A1

/K

A6

KB6

SA16

R9

CP6

/C

R6

/W

A4

/R

A8

D31

J1

D30

G1

Q30

F1

D23

J3

D21

F3

Q19

D3

D19

C3

Q23

K3

D25

M3

D12

J9

Q13

G9

D14

F9

Q15

E9

D16

C9

Q16

D9

D17

B9

NC1

C6

/BW3

B5

Q25

N3

Q32

K1

Q33

L1

D33

M1

D34

N1

Q35

P1

Q18

B2

Q28

C2

D29

E2

Q21

F2

Q31

J2

D32

K2

Q34

M2

D35

P2

D18

B3

D28

D1

D27

C1

Q27

B1

Q29

E1

Q12

K9

D11

L9

VDD1

F5

VDD2

G5

VDD3

H5

VDD4

J5

VDD5

K5

VDD6

F7

VDD7

G7

VDD8

H7

VDD9

J7

VDD10

K7

VSS25 N8VSS24 M8VSS23 D8VSS22 C8VSS21 M7

VSS16 L6

VSS17 M6

VSS18 D7

VSS19 E7

VSS20 L7

VSS11 F6

VSS12 G6

VSS13 H6

VSS14 J6

VSS15 K6

VSS6 E5

VSS7 L5

VSS8 M5

VSS9 D6

VSS10 E6

VSS1 C4

VSS3 M4

VSS4 N4

VSS5 D5

D2

M11

D4

J11

D6

E10

D8

C11

D20

D2

D22

G2

D24

L3

D26

N2

Q2

L11

Q4

J10

Q6

E11

Q8

B11

Q20

E3

Q22

G3

Q24

L2

Q26

P3

D10

M9

Q10

N9

Q9

P9

Q17

B10

Q7

C10

D15

D10

Q14

F10

D13

G10

D3

K10

Q11

L10

Q1

M10

D9

N10

D0

P10

D7

D11

Q5

F11

D5

G11

Q3

K11

D1

N11

Q0

P11

/BW0

B7

/BW2

A5

VSS_SA_128Mb

A10

VSS_SA_256Mb

A2

VSS2 D4

/BW1

A7

R38

249 1%

R281100



SchematicsR

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

QDR_DW

RITE_A28

QDR_DWRITE_A4

QDR_DWRITE_A0

QDR_DW

RITE_A34

QDR_DWRITE_A7

QDR_DW

RITE_A20

QDR_DWRITE_A5

QDR_DW

RITE_A30

QDR_DW

RITE_A[35:0]

QDR_DWRITE_A3

QDR_DW

RITE_A24

QDR_DW

RITE_A17

QDR_DW

RITE_A15

QDR_DWRITE_A2

QDR_DW

RITE_A35

QDR_DWRITE_A9

QDR_DW

RITE_A26

QDR_DW

RITE_A29

QDR_DW

RITE_A33

QDR_DW

RITE_A16

QDR_DW

RITE_A31

QDR_DW

RITE_A12

QDR_DW

RITE_A22

QDR_DW

RITE_A23

QDR_DW

RITE_A32

QDR_DW

RITE_A10

QDR_DWRITE_A6

QDR_DW

RITE_A11

QDR_DW

RITE_A14

QDR_DW

RITE_A27

QDR_DWRITE_A8

QDR_DW

RITE_A19

QDR_DWRITE_A1

QDR_DW

RITE_A25

QDR_DW

RITE_A13

QDR_DW

RITE_A18

QDR_DW

RITE_A21

QDR_SA_A13

QDR_SA_A[17:0]

QDR_SA_A14

QDR_SA_A3

QDR_SA_A15

QDR_SA_A11

QDR_SA_A4

QDR_SA_A10

QDR_SA_A2

QDR_SA_A8

QDR_SA_A6

QDR_SA_A9

QDR_SA_A12

QDR_SA_A0

QDR_SA_A5

QDR_SA_A16

QDR_SA_A17

QDR_SA_A7

QDR_SA_A1

+1.8V

+1.8V

+1.8V

QDR_WRITE_A[35:0]

QDR_SA_A[17:0]

+1.8V

GND_SIGNAL

Title

Size

Document Number

Rev

Date:

Sheet

of

<Doc>

5

ML365 QDR II SRAM Interface Board

B

628

01/22/04 09:07:

44

QDRII SRAM 1 Termination

R68100

R338100

R339100

R55100

R320100

R512100

R361100

R348100

R332100

R86100

R91100

R347100

R72100

R83100

R71100

R524100

R47100

R62100

R75100

R45100

R63100

R355100

R362100

R327100

R356100

R340100

R313100

R533100

R92100

R330100

R57100

R80100

R341100

R514100

R43100

R321100

R49100

R76100

R363100

R350100

R93100

R331100

R349100

R66100

R85100

R73100

R96100

R328100

R77100

R335100

R65100

R44100

R342100

R61100

R84100

R358100

R515100

R357100

R70100

R51100

R343100

R60100

R352100

R511100

R87100

R322100

R351100

R58100

R326100

R79100

R90100

R67100

R344100

R95100

R325100

R364100

R337100

R74100

R336100

R56100

R333100

R359100

R329100

R53100

R54100

R64100

R59100

R346100

R52100

R345100

R94100

R50100

R360100

R89100

R48100

R513100

R323100

R46100

R82100

R354100

R81100

R69100

R534100

R353100

R78100

R324100

R532100

R334100




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

QDR_B_DLL_n

QDR_B_ZQ

QDR_W

_n_B

QDR_R_n_B

QDR_K_B

QDR_K_n_B

QDR_C_B

QDR_C_n_B

QDR_DW

RITE_B[35:0]

QDR_SA_B[17:0]

QDR_DW

RITE_B35

QDR_DW

RITE_B34

QDR_DW

RITE_B33

QDR_DW

RITE_B32

QDR_DW

RITE_B31

QDR_DW

RITE_B30

QDR_DW

RITE_B29

QDR_DW

RITE_B28

QDR_DW

RITE_B27

QDR_DW

RITE_B26

QDR_DW

RITE_B25

QDR_DW

RITE_B24

QDR_DW

RITE_B23

QDR_DW

RITE_B22

QDR_DW

RITE_B21

QDR_DW

RITE_B20

QDR_DW

RITE_B14

QDR_DW

RITE_B13

QDR_DW

RITE_B12

QDR_DW

RITE_B11

QDR_DW

RITE_B10

QDR_DWRITE_B9

QDR_DWRITE_B8

QDR_DWRITE_B7

QDR_DWRITE_B6

QDR_DWRITE_B5

QDR_DWRITE_B4

QDR_DW

RITE_B19

QDR_DW

RITE_B18

QDR_DW

RITE_B17

QDR_DW

RITE_B16

QDR_DW

RITE_B15

QDR_SA_B7

QDR_SA_B8

QDR_SA_B9

QDR_SA_B10

QDR_SA_B11

QDR_SA_B12

QDR_SA_B13

QDR_SA_B14

QDR_SA_B15

QDR_SA_B16

QDR_SA_B17

QDR_SA_B2

QDR_SA_B3

QDR_SA_B4

QDR_SA_B5

QDR_SA_B6

QDR_BW_n_B0

QDR_BW_n_B2

QDR_SA_B0

QDR_SA_B1

QDR_DWRITE_B3

QDR_DWRITE_B2

QDR_DWRITE_B1

QDR_DWRITE_B0

QDR_DREAD_B20

QDR_DREAD_B27

QDR_DREAD_B19

QDR_CQ_B

QDR_DREA

D_B1

QDR_DREA

D_B9

QDR_DREAD_B15

QDR_DREAD_B12

QDR_CQ_n_B

QDR_DREAD_B28

QDR_DREAD_B31

QDR_DREAD_B22

QDR_DREA

D_B4

QDR_DREA

D_B2

QDR_DREAD_B10

QDR_DREAD_B16

QDR_DREAD_B13

QDR_DREA

D_B6

QDR_DREAD_B32

QDR_DREAD_B29

QDR_DREA

D_B5

QDR_DREAD_B17

QDR_DREAD_B25

QDR_DREA

D_B7

QDR_DREAD_B33

QDR_DREAD_B23

QDR_DREAD_B14

QDR_DREAD_B26

QDR_DREAD_B18

QDR_DREA

D_B0

QDR_DREA

D_B8

QDR_DREAD_B30

QDR_DREA

D_B3

QDR_DREAD_B11

QDR_DREAD_B35

QDR_DREAD_B34

QDR_DREAD_B21

QDR_DREAD_B24

QDR_DREAD_B[35:0]

QDR_BW_n_B[3:0]

QDR_BW_n_B0

QDR_BW_n_B1

QDR_BW_n_B2

QDR_BW_n_B3

QDR_BW_n_B1

QDR_BW_n_B3

QDR_BW_n_B0

QDR_BW_n_B1

QDR_BW_n_B2

QDR_BW_n_B3

+0.9V_QDR

+1.8V

GND_SIGNAL

QDR_R_n_B

QDR_K_B

QDR_K_n_B

QDR_W

_n_B

QDR_C_B

QDR_C_n_B

QDR_SA_B[17:0]

QDR_DW

RITE_B[35:0]

QDR_CQ_B

QDR_CQ_n_B

QDR_DREAD_B[35:0]

QDR_BW_n_B[3:0]

+1.8V

+1.8V

+0.9V_QDR

+1.8V

+1.8V

+0.9V_QDR

+1.8V

+1.8V

+1.8V

+1.8V

QDR_WRITE_B[35:0]

QDR_SA_B[17:0]

Title

Size

Document Number

Rev

Date:

Sheet

of

<Doc>

8


B

728

01/22/04 09:07:

45

QDRII SRAM 2

ZQ impedance "tuning" set to 50 ohms

P20.1 to P20.2 = DLL enabled

P20.3 to P20.2 = DLL off

P21.1 to P21.2 = min. Z

P21.3 to P21.2 = 50 ohm Z

200MHz -FC20

R482100

C368

0.1uF

R487100

R478100 R285

100

K7R323684M

FBGA 165

1M x 36

4-word burst

U11

K7R323684M

TDO

R1

TDI

R11

TCK

R2

TMS

R10

/DoffH1

VREF1

H2

VDDQ1

H3

VDDQ2

E4

VDDQ3

F4

VDDQ4

G4

VDDQ5

H4

VDDQ6

J4

VDDQ7

K4

VDDQ9

E8

VDDQ10

F8

VDDQ11

G8

VDDQ12

H8

VDDQ13

J8

VDDQ14

K8

VDDQ15

L8

VDDQ16

H9

VDDQ8

L4

VREF2

H10

ZQ

H11

NC_SA_64Mb

A3

SA0

B4

SA2

C5

SA3

C7

SA1

B8

SA17

A9

SA11

R3

SA12

R4

SA7

P4

SA4

N5

SA8

P5

SA13

R5

SA5

N6

SA6

N7

SA9

P7

SA14

R7

SA15

R8

SA10

P8

CQ

A11

/CQ

A1

/K

A6

KB6

SA16

R9

CP6

/C

R6

/W

A4

/R

A8

D31

J1

D30

G1

Q30

F1

D23

J3

D21

F3

Q19

D3

D19

C3

Q23

K3

D25

M3

D12

J9

Q13

G9

D14

F9

Q15

E9

D16

C9

Q16

D9

D17

B9

NC1

C6

/BW3

B5

Q25

N3

Q32

K1

Q33

L1

D33

M1

D34

N1

Q35

P1

Q18

B2

Q28

C2

D29

E2

Q21

F2

Q31

J2

D32

K2

Q34

M2

D35

P2

D18

B3

D28

D1

D27

C1

Q27

B1

Q29

E1

Q12

K9

D11

L9

VDD1

F5

VDD2

G5

VDD3

H5

VDD4

J5

VDD5

K5

VDD6

F7

VDD7

G7

VDD8

H7

VDD9

J7

VDD10

K7


VSS16 L6

VSS17 M6

VSS18 D7

VSS19 E7

VSS20 L7

VSS11 F6

VSS12 G6

VSS13 H6

VSS14 J6

VSS15 K6

VSS6 E5

VSS7 L5

VSS8 M5

VSS9 D6

VSS10 E6

VSS1 C4

VSS3 M4

VSS4 N4

VSS5 D5

D2

M11

D4

J11

D6

E10

D8

C11

D20

D2

D22

G2

D24

L3

D26

N2

Q2

L11

Q4

J10

Q6

E11

Q8

B11

Q20

E3

Q22

G3

Q24

L2

Q26

P3

D10

M9

Q10

N9

Q9

P9

Q17

B10

Q7

C10

D15

D10

Q14

F10

D13

G10

D3

K10

Q11

L10

Q1

M10

D9

N10

D0

P10

D7

D11

Q5

F11

D5

G11

Q3

K11

D1

N11

Q0

P11

/BW0

B7

/BW2

A5

VSS_SA_128Mb

A10

VSS_SA_256Mb

A2

VSS2 D4

/BW1

A7

R483100

R484100

P21

HEADER 3

1 2 3

R479100

P20

HEADER 3

1 2 3

R286

100

R475100 R282

100

R1580

R480100

R157

1K

R474100

R287

100

R485100

R159

0

R476100 R283

100

R156

0

R481100

R160

249 1%

R486100

R477100 R284

100



SchematicsR

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

QDR_SA_B[17:0]

QDR_SA_B13

QDR_SA_B14

QDR_SA_B15

QDR_SA_B16

QDR_SA_B0

QDR_SA_B17

QDR_SA_B3

QDR_SA_B2

QDR_SA_B1

QDR_SA_B4

QDR_SA_B6

QDR_SA_B5

QDR_SA_B8

QDR_SA_B7

QDR_SA_B11

QDR_SA_B10

QDR_SA_B9

QDR_SA_B12

QDR_DW

RITE_B35

QDR_DW

RITE_B34

QDR_DW

RITE_B31

QDR_DW

RITE_B30

QDR_DW

RITE_B29

QDR_DW

RITE_B28

QDR_DW

RITE_B26

QDR_DW

RITE_B25

QDR_DW

RITE_B23

QDR_DW

RITE_B21

QDR_DW

RITE_B20

QDR_DW

RITE_B19

QDR_DW

RITE_B18

QDR_DW

RITE_B17

QDR_DW

RITE_B16

QDR_DW

RITE_B13

QDR_DW

RITE_B12

QDR_DW

RITE_B11

QDR_DWRITE_B7

QDR_DWRITE_B5

QDR_DWRITE_B3

QDR_DWRITE_B2

QDR_DWRITE_B1

QDR_DWRITE_B0

QDR_DW

RITE_B[35:0]

QDR_DW

RITE_B33

QDR_DW

RITE_B32

QDR_DW

RITE_B27

QDR_DW

RITE_B24

QDR_DW

RITE_B22

QDR_DW

RITE_B15

QDR_DW

RITE_B14

QDR_DW

RITE_B10

QDR_DWRITE_B9

QDR_DWRITE_B8

QDR_DWRITE_B6

QDR_DWRITE_B4

+1.8V

+1.8V

+1.8V

QDR_SA_B[17:0]

+1.8V

GND_SIGNALQDR_WRITE_B[35:0]

Title

Size

Document Number

Rev

Date:

Sheet

of

<Doc>

5


B

828

01/22/04 09:07:

46


R405100

R378100

R399100

R212100

R371100

R372100

R175100

R184100

R207100

R402100

R190100

R396100

R366100

R191100

R411100

R194100

R186100

R172100

R374100

R383100

R168100

R163100

R518100

R202100

R178100

R162100

R185100

R390100 R391100

R410100

R393100

R195100

R177100

R375100

R407100

R367100

R198100

R209100

R169100

R373100

R404100

R201100

R401100

R380100

R384100

R208100

R398100

R193100

R385100

R377100

R517100

R381100

R196100

R520100

R192100

R187100

R174100

R214100

R167100

R395100

R376100

R179100

R161100

R197100

R392100

R211100

R171100

R166100

R406100

R203100

R182100

R409100

R204100

R386100

R210100

R180100

R387100

R403100

R519100

R368100

R527100

R400100

R170100

R397100

R382100

R199100

R365100

R213100

R189100

R173100

R165100

R205100

R188100

R394100

R379100

R200100

R176100

R408100

R183100

R370100

R521100

R388100

R164100

R516100

R389100

R369100

R181100

R206100




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

QDR_DREAD_C35

QDR_DREAD_C34

QDR_DREAD_C33

QDR_DREAD_C32

QDR_DREAD_C31

QDR_DREAD_C30

QDR_DREAD_C29

QDR_DREAD_C28

QDR_DREAD_C27

QDR_DREAD_C26

QDR_DREAD_C25

QDR_DREAD_C24

QDR_DREAD_C23

QDR_DREAD_C22

QDR_DREAD_C21

QDR_DREAD_C20

QDR_DREAD_C19

QDR_DREAD_C18

QDR_DREAD_C17

QDR_DREAD_C16

QDR_DREAD_C15

QDR_DREAD_C14

QDR_DREAD_C13

QDR_DREAD_C12

QDR_DREAD_C11

QDR_DREAD_C10

QDR_DREAD_C9

QDR_DREAD_C8

QDR_DREAD_C7

QDR_DREAD_C6

QDR_DREAD_C5

QDR_DREAD_C4

QDR_DREAD_C3

QDR_DREAD_C2

QDR_DREAD_C1

QDR_DREAD_C0

QDR_DREAD_C[35:0]

QDR_CQ_n_C

QDR_CQ_C

QDR_C_DLL_n

QDR_C_ZQ

QDR_W_n_C

QDR_R_n_C

QDR_K_C

QDR_K_n_C

QDR_C_C

QDR_C_n_C

QDR_SA_C0

QDR_SA_C1

QDR_SA_C2

QDR_SA_C3

QDR_SA_C4

QDR_SA_C5

QDR_SA_C12

QDR_SA_C13

QDR_SA_C14

QDR_SA_C15

QDR_SA_C16

QDR_SA_C17

QDR_SA_C6

QDR_SA_C7

QDR_SA_C8

QDR_SA_C9

QDR_SA_C10

QDR_SA_C11

QDR_DW

RITE_C[35:0]

QDR_SA_C[17:0]

QDR_DW

RITE_C35

QDR_DW

RITE_C34

QDR_DW

RITE_C33

QDR_DW

RITE_C32

QDR_DW

RITE_C31

QDR_DW

RITE_C30

QDR_DW

RITE_C29

QDR_DW

RITE_C28

QDR_DW

RITE_C27

QDR_DW

RITE_C26

QDR_DW

RITE_C25

QDR_DW

RITE_C24

QDR_DW

RITE_C23

QDR_DW

RITE_C22

QDR_DW

RITE_C21

QDR_DW

RITE_C20

QDR_DW

RITE_C19

QDR_DW

RITE_C18

QDR_DW

RITE_C17

QDR_DW

RITE_C16

QDR_DW

RITE_C15

QDR_DW

RITE_C14

QDR_DW

RITE_C13

QDR_DW

RITE_C12

QDR_DW

RITE_C11

QDR_DW

RITE_C10

QDR_DW

RITE_C9

QDR_DW

RITE_C8

QDR_DW

RITE_C7

QDR_DW

RITE_C6

QDR_DW

RITE_C5

QDR_DW

RITE_C4

QDR_DW

RITE_C3

QDR_DW

RITE_C2

QDR_DW

RITE_C1

QDR_DW

RITE_C0

QDR_BW

_n_C0

QDR_BW

_n_C1

QDR_BW

_n_C2

QDR_BW

_n_C3

QDR_BW

_n_C[3:0]

QDR_BW

_n_C0

QDR_BW

_n_C2

QDR_BW

_n_C0

QDR_BW

_n_C3

QDR_BW

_n_C1

QDR_BW

_n_C2

QDR_BW

_n_C1

QDR_BW

_n_C3

QDR_DREAD_C[35:0]

QDR_CQ_C

QDR_CQ_n_C

+0.9V_QDR

+1.8V

GND_SIGNAL

QDR_R_n_C

QDR_K_C

QDR_K_n_C

QDR_W_n_C

QDR_C_C

QDR_C_n_C

QDR_SA_C[17:0]

QDR_DW

RITE_C[35:0]

QDR_BW

_n_C[3:0]

+1.8V

+1.8V

+0.9V_QDR

+1.8V

+1.8V

+0.9V_QDR

+1.8V

+1.8V

+1.8V

+1.8V

QDR_W

RITE_C[35:0]

QDR_SA_C[17:0]

Title

Size

Document Number

Rev

Date:

Sheet

of

<Doc>

8


B

928

01/22/04 09:07:

47

QDRII SRAM 3

ZQ impedance "tuning" set to 50 ohms

P22.1 to P22.2 = DLL enabled

P22.3 to P22.2 = DLL off

P23.1 to P23.2 = min. Z

P23.3 to P23.2 = 50 ohm Z

250MHz -FC25

R497100

R219

249 1%

R292

100

P23

HEADER 3

1 2 3

R498100

R288

100

R488100

R490100

R216

1K

R494100

R2170

R293

100

R499100

R289

100

R491100

R218

0

R495100

K7R323684M

FBGA 165

1M x 36

4-word burst

U12

K7R323684M

TDO

R1

TDI

R11

TCK

R2

TMS

R10

/DoffH1

VREF1

H2

VDDQ1

H3

VDDQ2

E4

VDDQ3

F4

VDDQ4

G4

VDDQ5

H4

VDDQ6

J4

VDDQ7

K4

VDDQ9

E8

VDDQ10

F8

VDDQ11

G8

VDDQ12

H8

VDDQ13

J8

VDDQ14

K8

VDDQ15

L8

VDDQ16

H9

VDDQ8

L4

VREF2

H10

ZQ

H11

NC_SA_64Mb

A3

SA0

B4

SA2

C5

SA3

C7

SA1

B8

SA17

A9

SA11

R3

SA12

R4

SA7

P4

SA4

N5

SA8

P5

SA13

R5

SA5

N6

SA6

N7

SA9

P7

SA14

R7

SA15

R8

SA10

P8

CQ

A11

/CQ

A1

/K

A6

KB6

SA16

R9

CP6

/C

R6

/W

A4

/R

A8

D31

J1

D30

G1

Q30

F1

D23

J3

D21

F3

Q19

D3

D19

C3

Q23

K3

D25

M3

D12

J9

Q13

G9

D14

F9

Q15

E9

D16

C9

Q16

D9

D17

B9

NC1

C6

/BW3

B5

Q25

N3

Q32

K1

Q33

L1

D33

M1

D34

N1

Q35

P1

Q18

B2

Q28

C2

D29

E2

Q21

F2

Q31

J2

D32

K2

Q34

M2

D35

P2

D18

B3

D28

D1

D27

C1

Q27

B1

Q29

E1

Q12

K9

D11

L9

VDD1

F5

VDD2

G5

VDD3

H5

VDD4

J5

VDD5

K5

VDD6

F7

VDD7

G7

VDD8

H7

VDD9

J7

VDD10

K7


VSS16 L6

VSS17 M6

VSS18 D7

VSS19 E7

VSS20 L7

VSS11 F6

VSS12 G6

VSS13 H6

VSS14 J6

VSS15 K6

VSS6 E5

VSS7 L5

VSS8 M5

VSS9 D6

VSS10 E6

VSS1 C4

VSS3 M4

VSS4 N4

VSS5 D5

D2

M11

D4

J11

D6

E10

D8

C11

D20

D2

D22

G2

D24

L3

D26

N2

Q2

L11

Q4

J10

Q6

E11

Q8

B11

Q20

E3

Q22

G3

Q24

L2

Q26

P3

D10

M9

Q10

N9

Q9

P9

Q17

B10

Q7

C10

D15

D10

Q14

F10

D13

G10

D3

K10

Q11

L10

Q1

M10

D9

N10

D0

P10

D7

D11

Q5

F11

D5

G11

Q3

K11

D1

N11

Q0

P11

/BW0

B7

/BW2

A5

VSS_SA_128Mb

A10

VSS_SA_256Mb

A2

VSS2 D4

/BW1

A7

R500100

R290

100

R492100

R215

0

R496100

R501100

R291

100

R493100

R489100

P22

HEADER 3

1 2 3

C369

0.1uF



SchematicsR

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

QDR_DW

RITE_C[35:0]

QDR_DW

RITE_C33

QDR_DW

RITE_C29

QDR_DW

RITE_C28

QDR_DW

RITE_C23

QDR_DW

RITE_C20

QDR_DW

RITE_C19

QDR_DW

RITE_C18

QDR_DW

RITE_C17

QDR_DW

RITE_C15

QDR_DW

RITE_C14

QDR_DW

RITE_C13

QDR_DW

RITE_C12

QDR_DW

RITE_C8

QDR_DW

RITE_C5

QDR_DW

RITE_C4

QDR_DW

RITE_C1

QDR_SA_C2

QDR_SA_C9

QDR_SA_C17

QDR_SA_C[17:0]

QDR_DW

RITE_C0

QDR_DW

RITE_C2

QDR_DW

RITE_C3

QDR_DW

RITE_C6

QDR_DW

RITE_C7

QDR_DW

RITE_C9

QDR_DW

RITE_C10

QDR_DW

RITE_C11

QDR_DW

RITE_C16

QDR_DW

RITE_C21

QDR_DW

RITE_C22

QDR_DW

RITE_C24

QDR_DW

RITE_C25

QDR_DW

RITE_C26

QDR_DW

RITE_C27

QDR_DW

RITE_C30

QDR_DW

RITE_C31

QDR_DW

RITE_C32

QDR_DW

RITE_C34

QDR_DW

RITE_C35

QDR_SA_C16

QDR_SA_C15

QDR_SA_C14

QDR_SA_C13

QDR_SA_C12

QDR_SA_C11

QDR_SA_C10

QDR_SA_C8

QDR_SA_C7

QDR_SA_C6

QDR_SA_C5

QDR_SA_C4

QDR_SA_C3

QDR_SA_C1

QDR_SA_C0

+1.8V

+1.8V

+1.8V

QDR_W

RITE_C[35:0]

+1.8V

QDR_SA_C[17:0]

GND_SIGNAL

Title

Size

Document Number

Rev

Date:

Sheet

of

<Doc>

5


B

10

28

01/22/04 09:07:

47


R454100

R530100

R412100

R440100

R435100

R262100

R457100

R451100

R268100

R529100

R423100

R426100

R253100

R237100

R245100

R229100

R416100

R259100

R421100

R434100

R232100

R273100

R227100

R265100

R448100

R224100

R425100

R445100

R256100

R437100

R221100

R456100

R430100

R413100

R442100

R252100

R531100

R429100

R270100

R247100

R231100

R264100

R417100

R420100

R453100

R418100

R436100

R422100

R238100

R447100

R267100

R240100

R228100

R450100

R522100

R439100

R244100

R225100

R428100

R431100

R239100

R414100

R444100

R222100

R234100

R249100

R459100

R272100

R233100

R248100

R458100

R260100

R441100

R255100

R427100

R266100

R269100

R261100

R438100

R455100

R452100

R528100

R419100

R449100

R424100

R433100

R230100

R415100

R523100

R226100

R242100

R223100

R251100

R235100

R250100

R243100

R241100

R446100

R257100

R236100

R432100

R271100

R246100

R443100

R263100

R258100

R254100

R220100




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

QDR_DREAD_C35

QDR_DREAD_C34

QDR_DREAD_C33

QDR_DREAD_C32

QDR_DREAD_C31

QDR_DREAD_C30

QDR_DREAD_C29

QDR_DREAD_C28

QDR_DREAD_C27

QDR_DREAD_C26

QDR_DREAD_C25

QDR_DREAD_C24

QDR_DREAD_C23

QDR_DREAD_C22

QDR_DREAD_C21

QDR_DREAD_C20

QDR_DREAD_C19

QDR_DREAD_C18

QDR_DREAD_C17

QDR_DREAD_C16

QDR_DREAD_C15

QDR_DREAD_C14

QDR_DREAD_C13

QDR_DREAD_C12

QDR_DREAD_C11

QDR_DREAD_C10

QDR_DREAD_C9

QDR_DREAD_C8

QDR_DREAD_C7

QDR_DREAD_C6

QDR_DREAD_C5

QDR_DREAD_C4

QDR_DREAD_C3

QDR_DREAD_C2

QDR_DREAD_C1

QDR_DREAD_C0

QDR_DREAD_C[35:0]

QDR_CQ_C

QDR_CQ_n_C

R_n_int_C

+5V

+3.3V

+2.5V

+1.8V

+0.9V_FPGA

+1.5V

GND_SIGNAL

QDR_DREAD_C[35:0]

QDR_CQ_C

QDR_CQ_n_C

+0.9V_FPGA

+0.9V_FPGA

+1.8V

+1.8V

+1.5V

+0.9V_FPGA

+3.3V

+5V

+2.5V

+1.8V

+1.8V

+1.8V

+1.5V

+0.9V_FPGA

+5V

+3.3V

+2.5V

GND_SIGNAL

+1.8V

R_n_ext_C

Title

Size

Document Number

Rev

Date:

Sheet

of

<Doc>

11


B

11

28

03/15/04 08:49:

10

BANK0

QDRII SRAM 3 (QDR C) DREAD Interface

250MHz DCM driven

IN

R294100

R295100

R504100

C430

0.1uF

R503100

BANK0

U6A

XC2VP20

IO_L01N_0/VRP_0

E29

IO_L01P_0/VRN_0

E28

IO_L02N_0

H26

IO_L02P_0

G26

IO_L03N_0

H25

IO_L03P_0/VREF_0

G25

IO_L05_0/No_Pair

J25

IO_L06N_0

K24

IO_L06P_0

J24

IO_L37N_0

H22

IO_L37P_0

G22

IO_L38N_0

D26

IO_L38P_0

C26

IO_L39N_0

K21

IO_L39P_0

J21

IO_L43N_0

F22

IO_L43P_0

E22

IO_L44N_0

E25

IO_L44P_0

D25

IO_L45N_0

H21

IO_L45P_0/VREF_0

G21

IO_L46N_0

D22

IO_L46P_0

D23

IO_L49N_0

F21

IO_L49P_0

E21

IO_L50_0/No_PairC21

IO_L53_0/No_PairC22

IO_L54N_0

L19

IO_L54P_0

K19

IO_L67N_0

G19

IO_L67P_0

F19

IO_L68N_0

E19

IO_L68P_0

D19

IO_L69N_0

L18

IO_L69P_0/VREF_0

K18

IO_L73N_0

G18

IO_L73P_0

F18

IO_L74N_0/GCLK7P

E18

IO_L74P_0/GCLK6S

D18

IO_L75N_0/GCLK5P

J18

IO_L75P_0/GCLK4S

H18

VCCO_0_1

C29

VCCO_0_2

E20

VCCO_0_3

F25

VCCO_0_4

L20

VCCO_0_5

L21

VCCO_0_6

L22

VCCO_0_7

L23

VCCO_0_8

M18

VCCO_0_9

M19

VCCO_0_10

M20

VCCO_0_11

M21

VCCO_0_12

M22

IO_L07N_0

F26

IO_L07P_0

E26

IO_L08N_0

D30

IO_L08P_0

D29

IO_L09N_0

K23

IO_L09P_0/VREF_0

J23

IO_L47N_0

D24

IO_L47P_0

C24

IO_L48N_0

K20

IO_L48P_0

J20

IO_L55N_0

G20

IO_L55P_0

F20

IO_L56N_0

D21

IO_L56P_0

D20

IO_L57N_0

J19

IO_L57P_0/VREF_0

H19

R117

51

C370

0.1uF

R502100

R114

51

R3100



SchematicsR

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

QDR_DW

RITE_C26

QDR_DW

RITE_C25

QDR_DW

RITE_C24

QDR_DW

RITE_C23

QDR_DW

RITE_C22

QDR_DW

RITE_C21

QDR_DW

RITE_C20

QDR_DW

RITE_C19

QDR_DW

RITE_C18

QDR_DW

RITE_C17

QDR_DW

RITE_C16

QDR_DW

RITE_C15

QDR_DW

RITE_C14

QDR_DW

RITE_C13

QDR_DW

RITE_C12

QDR_DW

RITE_C11

QDR_DW

RITE_C10

QDR_DW

RITE_C9

QDR_DW

RITE_C8

QDR_DW

RITE_C7

QDR_DW

RITE_C6

QDR_DW

RITE_C5

QDR_DW

RITE_C4

QDR_DW

RITE_C3

QDR_DW

RITE_C2

QDR_DW

RITE_C1

QDR_DW

RITE_C0

QDR_DW

RITE_C30

QDR_DW

RITE_C29

QDR_DW

RITE_C28

QDR_DW

RITE_C27

QDR_DW

RITE_C[35:0]

QDR_DW

RITE_C35

QDR_DW

RITE_C34

QDR_DW

RITE_C33

QDR_DW

RITE_C32

QDR_DW

RITE_C31

QDR_C_n_C

QDR_C_C

QDR_W_n_C

QDR_R_n_C

QDR_K_n_C

QDR_K_C

R_n_ext_C

QDR_DW

RITE_C[35:0]

QDR_C_n_C

QDR_C_C

QDR_W_n_C

QDR_R_n_C

QDR_K_n_C

QDR_K_C

+0.9V_FPGA

+0.9V_FPGA

+1.8V

+1.8V

+0.9V_FPGA

+1.8V

+1.8V

GND_SIGNAL

+0.9V_FPGA

R_n_ext_C

Title

Size

Document Number

Rev

Date:

Sheet

of

<Doc>

11


B

12

28

03/15/04 08:49:

10

BANK1

QDRII SRAM 3 (QDR C) DWRITE Interface

250MHz DCM driven

OUT

R115

51

BANK1

U6B

XC2VP20

IO_L75N_1/GCLK3P

H17

IO_L75P_1/GCLK2S

J17

IO_L74N_1/GCLK1P

D17

IO_L74P_1/GCLK0S

E17

IO_L73N_1

F17

IO_L73P_1

G17

IO_L57N_1/VREF_1

H16

IO_L57P_1

J16

IO_L56N_1

D15

IO_L56P_1

D14

IO_L55N_1

F15

IO_L55P_1

G15

IO_L69N_1/VREF_1

K17

IO_L69P_1

L17

IO_L68N_1

D16

IO_L68P_1

E16

IO_L67N_1

F16

IO_L67P_1

G16

IO_L54N_1

K16

IO_L54P_1

L16

IO_L53_1/No_Pair

C13

IO_L50_1/No_Pair

C14

IO_L48N_1

J15

IO_L48P_1

K15

IO_L45N_1/VREF_1

G14

IO_L47P_1

D11

IO_L47N_1

C11

IO_L46P_1

D13

IO_L49N_1

E14

IO_L49P_1

F14

IO_L46N_1

D12

IO_L45P_1

H14

IO_L44N_1

D10

IO_L44P_1

E10

IO_L43N_1

E13

IO_L07N_1

E9

IO_L09N_1/VREF_1

J12

IO_L09P_1

K12

IO_L06N_1

J11

IO_L06P_1

K11

IO_L05_1/No_PairJ10

IO_L08P_1

D5

IO_L08N_1

D6

IO_L07P_1

F9

IO_L03N_1/VREF_1

G10

IO_L03P_1

H10

IO_L02N_1

G9

IO_L02P_1

H9

IO_L01N_1/VRP_1

E7

IO_L01P_1/VRN_1

E6

VCCO_1_1

C6

VCCO_1_2

E15

VCCO_1_3

F10

VCCO_1_4

L12

VCCO_1_5

L13

VCCO_1_6

L14

VCCO_1_7

L15

VCCO_1_12

M17

VCCO_1_11

M16

VCCO_1_10

M15

VCCO_1_9

M14

VCCO_1_8

M13

IO_L43P_1

F13

IO_L39N_1

J14

IO_L39P_1

K14

IO_L38N_1

C9

IO_L38P_1

D9

IO_L37N_1

G13

IO_L37P_1

H13

C431

0.1uF

C371

0.1uF

R116

51




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

QDR_DREA

D_B1

QDR_DREA

D_B6

QDR_DREA

D_B5

QDR_DREA

D_B0

QDR_DREA

D_B9

QDR_DREA

D_B3

QDR_DREA

D_B7

QDR_DREA

D_B2

QDR_DREA

D_B8

QDR_DREA

D_B4

R_n_int_B

QDR_BW

_n_C[3:0]

QDR_BW

_n_C0

QDR_BW

_n_C2

QDR_BW

_n_C1

QDR_BW

_n_C3

QDR_SA_C0

QDR_SA_C1

QDR_SA_C2

QDR_SA_C3

QDR_SA_C4

QDR_SA_C5

QDR_SA_C12

QDR_SA_C13

QDR_SA_C14

QDR_SA_C6

QDR_SA_C7

QDR_SA_C8

QDR_SA_C9

QDR_SA_C10

QDR_SA_C11

QDR_SA_C15

QDR_SA_C16

QDR_SA_C17

QDR_SA_C[17:0]

QDR_DREAD_B[35:0]

QDR_DREAD_B12

QDR_DREAD_B13

QDR_DREAD_B14

QDR_DREAD_B11

QDR_DREAD_B15

QDR_DREAD_B10

QDR_DREAD_B16

QDR_DREAD_B17

QDR_DREAD_B25

QDR_DREAD_B22

QDR_DREAD_B23

QDR_DREAD_B20

QDR_DREAD_B24

QDR_DREAD_B21

QDR_DREAD_B19

QDR_DREAD_B18

QDR_DREAD_B27

QDR_DREAD_B26

QDR_DREAD_B30

QDR_DREAD_B29

QDR_DREAD_B31

QDR_DREAD_B28

QDR_DREAD_B33

QDR_DREAD_B34

QDR_DREAD_B35

QDR_DREAD_B32

QDR_CQ_n_B

QDR_CQ_B

QDR_BW

_n_C[3:0]

QDR_SA_C[17:0]

QDR_DREAD_B[35:0]

QDR_CQ_B

QDR_CQ_n_B

+1.8V

+0.9V_FPGA

+0.9V_FPGA

+1.8V

+0.9V_FPGA

+1.8V

+1.8V

+1.8V

+1.8V

+1.8V

GND_SIGNAL

+0.9V_FPGA

R_n_ext_B

Title

Size

Document Number

Rev

Date:

Sheet

of

<Doc>

11


B

13

28

03/15/04 08:49:

10

BANK2QDRII SRAM 3 (QDR C) SA (address) Interface

QDRII SRAM 2 (QDR B) DREAD Interface

IN

BANK2

U6C

XC2VP20

IO_L01N_2/VRP_2

D2

IO_L01P_2/VRN_2

D1

IO_L02N_2

F8

IO_L02P_2

F7

IO_L03N_2

E4

IO_L03P_2

E3

IO_L04N_2/VREF_2

E2

IO_L04P_2

E1

IO_L05N_2

J8

IO_L05P_2

J7

IO_L06N_2

F5

IO_L06P_2

F4

IO_L31N_2

H2

IO_L31P_2

H1

IO_L32N_2

M10

IO_L32P_2

M9

IO_L33N_2

K5

IO_L33P_2

K4

IO_L34N_2/VREF_2

J2

IO_L34P_2

K2

IO_L35N_2

L8

IO_L35P_2

L7

IO_L36N_2

L6

IO_L36P_2

L5

IO_L37N_2

K1

IO_L37P_2

L1

IO_L38N_2

N10

IO_L38P_2

N9

IO_L39N_2

M7

IO_L39P_2

M6

IO_L40N_2/VREF_2

L2

IO_L40P_2

M2

IO_L41N_2

N8

IO_L41P_2

N7

IO_L42N_2

L4

IO_L42P_2

L3

IO_L43N_2

M4

IO_L43P_2

M3

IO_L44N_2

P10

IO_L44P_2

P9

IO_L45N_2

N6

IO_L45P_2

N5

IO_L46N_2/VREF_2

M1

IO_L46P_2

N1

IO_L47N_2

P8

IO_L47P_2

P7

IO_L48N_2

N4

IO_L48P_2

N3

IO_L49N_2

N2

IO_L49P_2

P2

IO_L50N_2

R10

IO_L50P_2

R9

IO_L51N_2

P6

IO_L51P_2

P5

IO_L52N_2/VREF_2

P4

IO_L52P_2

P3

IO_L53N_2

T11

IO_L53P_2

U11

IO_L54N_2

R7

IO_L54P_2

R6

IO_L55N_2

P1

IO_L55P_2

R1

IO_L56N_2

T10

IO_L56P_2

T9

IO_L57N_2

R4

IO_L57P_2

R3

IO_L58N_2/VREF_2

R2

IO_L58P_2

T2

IO_L59N_2

T8

IO_L59P_2

T7

IO_L60N_2

T6

IO_L60P_2

T5

IO_L85N_2

T4

IO_L85P_2

T3

IO_L86N_2

U10

IO_L86P_2

U9

IO_L87N_2

U6

IO_L87P_2

U5

IO_L88N_2/VREF_2

U2

IO_L88P_2

V2

IO_L89N_2

U8

IO_L89P_2

U7

IO_L90N_2

U4

IO_L90P_2

U3

VCCO_2_1

F3

VCCO_2_2

K6

VCCO_2_3

M11

VCCO_2_4

N11

VCCO_2_5

N12

VCCO_2_6

P11

VCCO_2_7

P12

VCCO_2_8

R5

VCCO_2_9

R11

VCCO_2_10

R12

VCCO_2_11

T12

VCCO_2_12

U12

R507100

R119

51

R505100

C375

0.1uF

R506100

R118

51

R525100

C432

0.1uF

R4100

R296100



SchematicsR

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

QDR_DW

RITE_B[35:0]

QDR_DW

RITE_B21

QDR_DW

RITE_B13

QDR_DW

RITE_B14

QDR_DW

RITE_B11

QDR_DWRITE_B9

QDR_DW

RITE_B18

QDR_DW

RITE_B16

QDR_DW

RITE_B15

QDR_DW

RITE_B17

QDR_DWRITE_B3

QDR_DWRITE_B0

QDR_DWRITE_B2

QDR_DWRITE_B7

QDR_DW

RITE_B29

QDR_DW

RITE_B34

QDR_DWRITE_B1

QDR_DWRITE_B4

QDR_DWRITE_B5

QDR_DWRITE_B6

QDR_DWRITE_B8

QDR_DW

RITE_B10

QDR_DW

RITE_B12

QDR_DW

RITE_B19

QDR_DW

RITE_B20

QDR_DW

RITE_B22

QDR_DW

RITE_B23

QDR_DW

RITE_B24

QDR_DW

RITE_B25

QDR_DW

RITE_B26

QDR_DW

RITE_B27

QDR_DW

RITE_B28

QDR_DW

RITE_B30

QDR_DW

RITE_B31

QDR_DW

RITE_B32

QDR_DW

RITE_B33

QDR_DW

RITE_B35

QDR_SA_B11

QDR_SA_B4

QDR_SA_B5

QDR_SA_B6

QDR_SA_B[17:0]

QDR_SA_B0

QDR_SA_B1

QDR_SA_B13

QDR_SA_B15

QDR_SA_B17

QDR_SA_B2

QDR_SA_B3

QDR_SA_B7

QDR_SA_B8

QDR_SA_B9

QDR_SA_B10

QDR_SA_B12

QDR_SA_B14

QDR_SA_B16

QDR_BW_n_B0

QDR_BW_n_B1

QDR_BW_n_B3

QDR_BW_n_B[3:0]

QDR_BW_n_B2

QDR_W

_n_B

QDR_R_n_B

QDR_K_B

QDR_K_n_B

QDR_C_B

QDR_C_n_B

R_n_ext_B

DONE

QDR_DW

RITE_B[35:0]

QDR_SA_B[17:0]

QDR_BW_n_B[3:0]

QDR_K_B

QDR_K_n_B

QDR_R_n_B

QDR_W

_n_B

QDR_C_n_B

QDR_C_B

+0.9V_FPGA

+1.8V

+0.9V_FPGA

+1.8V

+0.9V_FPGA

+1.8V

+1.8V

GND_SIGNAL

+0.9V_FPGA

R_n_ext_B

DONE

Title

Size

Document Number

Rev

Date:

Sheet

of

<Doc>

11


B

14

28

03/15/04 08:49:

10

BANK3

QDRII SRAM 2 (QDR B) DWRITE & SA (Address) Interfaces

OUT

R121

51

R120

51

C433

0.1uF

BANK3

U6D

XC2VP20

IO_L90N_3

V3

IO_L90P_3

V4

IO_L89N_3

V7

IO_L89P_3

V8

IO_L88N_3

V5

IO_L88P_3

V6

IO_L87N_3/VREF_3

W2

IO_L87P_3

Y2

IO_L86N_3

V9

IO_L86P_3

V10

IO_L85N_3

W3

IO_L85P_3

W4

IO_L60N_3

Y1

IO_L60P_3

AA1

IO_L59N_3

V11

IO_L59P_3

W11

IO_L58N_3

W5

IO_L58P_3

W6

IO_L57N_3/VREF_3

Y3

IO_L57P_3

Y4

IO_L56N_3

W7

IO_L56P_3

W8

IO_L55N_3

Y6

IO_L55P_3

Y7

IO_L54N_3

AA2

IO_L54P_3

AB2

IO_L53N_3

W9

IO_L53P_3

W10

IO_L52N_3

AA3

IO_L52P_3

AA4

IO_L51N_3/VREF_3

AB1

IO_L51P_3

AC1

IO_L50N_3

Y9

IO_L50P_3

Y10

IO_L49N_3

AA5

IO_L49P_3

AA6

IO_L48N_3

AB3

IO_L48P_3

AB4

IO_L47N_3

AA7

IO_L47P_3

AA8

IO_L46N_3

AB5

IO_L46P_3

AB6

IO_L45N_3/VREF_3

AC2

IO_L45P_3

AD2

IO_L44N_3

AA9

IO_L44P_3

AA10

IO_L43N_3

AC3

IO_L43P_3

AC4

IO_L42N_3

AD1

IO_L42P_3

AE1

IO_L41N_3

AB7

IO_L41P_3

AB8

IO_L40N_3

AC6

IO_L40P_3

AC7

IO_L39N_3/VREF_3

AD3

IO_L39P_3

AD4

IO_L38N_3

AB9

IO_L38P_3

AB10

IO_L37N_3

AD5

IO_L37P_3

AD6

IO_L36N_3

AE2

IO_L36P_3

AF2

IO_L35N_3

AD7

IO_L35P_3

AD8

IO_L34N_3

AE4

IO_L34P_3

AE5

IO_L33N_3/VREF_3

AG1

IO_L33P_3

AG2

IO_L32N_3

AC9

IO_L32P_3

AC10

IO_L31N_3

AF3

IO_L31P_3

AF4

IO_L06N_3

AL1

IO_L06P_3

AL2

IO_L05N_3

AG7

IO_L05P_3

AH8

IO_L04N_3

AH5

IO_L04P_3

AH6

IO_L03N_3/VREF_3

AK3

IO_L03P_3

AK4

IO_L02N_3

AJ7

IO_L02P_3

AJ8

IO_L01N_3/VRP_3

AJ4

IO_L01P_3/VRN_3

AJ5

VCCO_3_1

V12

VCCO_3_2

W12

VCCO_3_3

Y5

VCCO_3_4

Y11

VCCO_3_5

Y12

VCCO_3_6

AA11

VCCO_3_7

AA12

VCCO_3_8

AB11

VCCO_3_9

AB12

VCCO_3_10

AC11

VCCO_3_11

AE6

VCCO_3_12

AJ3

C372

0.1uF




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

BANK4_LA15

BANK4_LA14

BANK4_LA12

BANK4_LA16

BANK4_LA11

FPGA_D1

FPGA_D2

FPGA_BUSY

RS232_R1OUT

FPGA_D0

RS232_T1IN

FPGA_D3

BANK4_LA1

BANK4_LA2

BANK4_LA3

BANK4_LA4

BANK4_LA5

BANK4_LA6

BANK4_LA7

BANK4_LA8

BANK4_LA9

BANK4_LA10

BANK4_LA11

BANK4_LA12

BANK4_LA13

BANK4_LA14

OSC_250M_P

OSC_250M_N

OSC_200M_P

OSC_200M_N

BANK4_LA13

BANK4_LA2

BANK4_LA3

BANK4_LA4

BANK4_LA5

BANK4_LA6

BANK4_LA7

BANK4_LA8

BANK4_LA9

BANK4_LA10

BANK4_LA1

BANK4_LACLK

BANK4_LA15

BANK4_LA16

BANK4_LACLK

RS232_T1IN

RS232_R1OUT

OSC_200M_P

OSC_200M_N

OSC_250M_P

OSC_250M_N

+2.5V

+3.3V

+3.3V

+3.3V

+2.5V

+2.5V

GND_SIGNAL

+3.3V

FPGA_BUSY

FPGA_D1

FPGA_D0

FPGA_D2

FPGA_D3

Title

Size

Document Number

Rev

Date:

Sheet

of

<Doc>

12


B

15

28

03/15/04 08:49:

11

BANK4

Vfwd=1.9V, Ifwd=20mA

User 1


User 2

Logic Analyzer Header

Vref not requiredRS-232 Interface

User PB’s and LED’s

User 2

User 1

P47

HEADER 1x2

12

R14451

P19

HEADER 16X2

2 4 6 810

12

14

16

18

20

22

24

26

28

30

32

1 3 5 7 9 11

13

15

17

19

21

23

25

27

29

31

R137

270

R30151

R537

4.7K

R15351

R8851

SW7

SW PUSHBUTTON

R139

270

R14951

R14551

R136

10K

R29851

R15451

R538

4.7K

R138

10K

R15051

R14051

R14651

R29951

R14251

G

SDQ7

BSS138

R15551

BANK4

U6E

XC2VP20

IO_L01N_4/DOUT

AL5

IO_L02N_4/D0

AG9

IO_L02P_4/D1

AH9

IO_L03N_4/D2

AK6

IO_L03P_4/D3

AK7

IO_L07P_4/VREF_4

AF11

IO_L07N_4

AE11

IO_L05_4/No_Pair

AF10

IO_L06N_4/VRP_4

AL7

IO_L06P_4/VRN_4

AM7

IO_L08N_4

AG10

IO_L08P_4

AH10

IO_L09N_4

AK8

IO_L09P_4/VREF_4

AL8

IO_L37N_4

AE13

IO_L37P_4

AF13

IO_L38N_4

AG13

IO_L38P_4

AH13

IO_L39N_4

AJ11

IO_L39P_4

AK11

IO_L43N_4

AE14

IO_L43P_4

AF14

IO_L44N_4

AJ13

IO_L44P_4

AK13

IO_L45N_4

AL11

IO_L45P_4/VREF_4

AM11

IO_L46N_4

AE15

IO_L46P_4

AF15

IO_L47N_4

AG14

IO_L47P_4

AH14

IO_L48N_4

AL13

IO_L48P_4

AL12

IO_L49N_4

AD16

IO_L49P_4

AE16

IO_L50_4/No_PairAJ14

IO_L53_4/No_PairAK14

IO_L54N_4

AM14

IO_L54P_4

AM13

IO_L67N_4

AD17

IO_L67P_4

AE17

IO_L68N_4

AH16

IO_L68P_4

AJ16

IO_L69N_4

AK16

IO_L69P_4/VREF_4

AL16

IO_L73N_4

AF17

IO_L73P_4

AG17

IO_L74N_4/GCLK3S

AH17

IO_L74P_4/GCLK2P

AJ17

IO_L75N_4/GCLK1S

AK17

IO_L75P_4/GCLK0P

AL17

VCCO_4_1

AC13

VCCO_4_2

AC14

VCCO_4_3

AC15

VCCO_4_4

AC16

VCCO_4_5

AC17

VCCO_4_6

AD12

VCCO_4_7

AD13

VCCO_4_8

AD14

VCCO_4_9

AD15

VCCO_4_10

AJ10

VCCO_4_11

AK15

VCCO_4_12

AM6

IO_L55N_4

AF16

IO_L55P_4

AG16

IO_L57N_4

AL14

IO_L57P_4/VREF_4

AL15

IO_L56N_4

AH15

IO_L56P_4

AJ15

R15151

G

SDQ8

BSS138

R14151

R14751

R14351

R30051

D10

RED

12

SW6

SW PUSHBUTTON

R15251

D11

RED

12

R14851



SchematicsR

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

FPGA_D7

FPGA_D6

FPGA_D5

FPGA_D4

FPGA_D3

FPGA_D2

FPGA_D1

FPGA_D0

FPGA_CS#

FPGA_RDW

R#

FPGA_BUSY

SYSACE_MPA[6:0]

SYSACE_MPD[7:0]

SYSACE_MPD0

SYSACE_MPD1

SYSACE_MPD2

SYSACE_MPA0

SYSACE_MPA1

SYSACE_MPA4

SYSACE_MPA6

SYSACE_MPA5

SYSACE_MPA3

SYSACE_MPA2

SYSACE_MPD4

SYSACE_MPD6

SYSACE_MPD5

SYSACE_MPD7

SYSACE_MPD3

EXTCLK1_N

EXTCLK1_P

SYSACE_CLK

SYSACE_MPBRDY

SYSACE_MPCE#

SYSACE_MPOE#

SYSACE_MPBIRQ

SYSACE_MPWE#

LCD_DB5

LCD_DB6

LCD_DB4

LCD_DB[7:0]

LCD_DB7

LCD_DB0

LCD_DB1

LCD_DB2

LCD_DB3

LCD_E

LCD_RS

LCD_R_W

#

TRST#

HALT#

SYSACE_MPA[6:0]

SYSACE_CLK

SYSACE_MPBRDY

SYSACE_MPCE#

SYSACE_MPOE#

SYSACE_MPWE#

SYSACE_MPBIRQ

LCD_E

LCD_RS

LCD_R_W

#

EXTCLK1_P

EXTCLK1_N

SYSACE_MPD[7:0]

LCD_DB[7:0]

HALT#

TRST#

+2.5V

+2.5V

+2.5V

FPGA_D0

FPGA_D1

FPGA_D2

FPGA_D3

FPGA_BUSY

+2.5V

GND_SIGNAL

Title

Size

Document Number

Rev

Date:

Sheet

of

<Doc>

5


B

16

28

03/15/04 08:49:

11

BANK5

SelectMAP Header

DOUT

SystemAce and LCD Interfaces Master Reset switch (N.O.)

R106

10K

R275

51

P12

12

34

56

78

910

11

12

13

14

15

16

17

18

SW5

SW PUSHBUTTON

R274

51

BANK5

U6F

XC2VP20

IO_L75N_5/GCLK7S

AL18

IO_L75P_5/GCLK6P

AK18

IO_L74N_5/GCLK5S

AJ18

IO_L74P_5/GCLK4P

AH18

IO_L73N_5

AG18

IO_L73P_5

AF18

IO_L69N_5/VREF_5

AL19

IO_L69P_5

AK19

IO_L68N_5

AJ19

IO_L68P_5

AH19

IO_L67N_5

AE18

IO_L67P_5

AD18

IO_L56N_5

AJ20

IO_L56P_5

AH20

IO_L55N_5

AG19

IO_L55P_5

AF19

IO_L54N_5

AM22

IO_L54P_5

AM21

IO_L53_5/No_Pair

AK21

IO_L50_5/No_Pair

AJ21

IO_L49N_5

AE19

IO_L49P_5

AD19

IO_L48N_5

AL23

IO_L48P_5

AL22

IO_L47N_5

AH21

IO_L47P_5

AG21

IO_L46N_5

AF20

IO_L46P_5

AE20

IO_L45N_5/VREF_5

AM24

IO_L45P_5

AL24

IO_L44N_5

AK22

IO_L44P_5

AJ22

IO_L43N_5

AF21

IO_L43P_5

AE21

IO_L39N_5

AK24

IO_L57P_5

AL21

IO_L57N_5/VREF_5

AL20

IO_L39P_5

AJ24

IO_L38N_5

AH22

IO_L38P_5

AG22

IO_L06N_5/VRP_5

AM28

IO_L06P_5/VRN_5

AL28

IO_L05_5/No_PairAF25

IO_L03N_5/D4

AK28

IO_L03P_5/D5

AK29

IO_L02N_5/D6

AH26

IO_L02P_5/D7

AG26

IO_L01N_5/RDWR_5

AL29

IO_L01P_5/CS_B

AL30

IO_L09N_5/VREF_5

AL27

IO_L09P_5

AK27

IO_L08N_5

AH25

IO_L08P_5

AG25

IO_L37N_5

AF22

IO_L37P_5

AE22

IO_L07N_5/VREF_5

AF24

IO_L07P_5

AE24

VCCO_5_1

AC18

VCCO_5_2

AC19

VCCO_5_3

AC20

VCCO_5_4

AC21

VCCO_5_5

AC22

VCCO_5_6

AD20

VCCO_5_7

AD21

VCCO_5_8

AD22

VCCO_5_9

AD23

VCCO_5_10

AJ25

VCCO_5_11

AK20

VCCO_5_12

AM29




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

QDR_SA_A0

QDR_SA_A1

QDR_SA_A2

QDR_SA_A3

QDR_SA_A4

QDR_SA_A5

QDR_SA_A6

QDR_SA_A7

QDR_SA_A8

QDR_SA_A9

QDR_SA_A10

QDR_SA_A11

QDR_SA_A12

QDR_SA_A13

QDR_SA_A14

QDR_SA_A15

QDR_SA_A16

QDR_SA_A17

QDR_DW

RITE_A19

QDR_DW

RITE_A22

QDR_DW

RITE_A23

QDR_DW

RITE_A33

QDR_DW

RITE_A10

QDR_DW

RITE_A15

QDR_DW

RITE_A17

QDR_DWRITE_A4

QDR_DW

RITE_A21

QDR_DW

RITE_A32

QDR_DW

RITE_A[35:0]

QDR_DW

RITE_A28

QDR_DW

RITE_A30

QDR_DW

RITE_A27

QDR_DW

RITE_A14

QDR_DWRITE_A6

QDR_DWRITE_A0

QDR_DW

RITE_A18

QDR_DWRITE_A1

QDR_DWRITE_A8

QDR_DW

RITE_A35

QDR_DWRITE_A9

QDR_DW

RITE_A16

QDR_DWRITE_A5

QDR_DW

RITE_A31

QDR_DW

RITE_A12

QDR_DW

RITE_A11

QDR_DW

RITE_A25

QDR_DW

RITE_A20

QDR_DW

RITE_A24

QDR_DWRITE_A7

QDR_DW

RITE_A13

QDR_DW

RITE_A26

QDR_DW

RITE_A29

QDR_DWRITE_A2

QDR_DWRITE_A3

QDR_DW

RITE_A34

QDR_SA_A[17:0]

QDR_K_n_A

QDR_K_A

QDR_BW_n_A0

QDR_BW_n_A1

QDR_BW_n_A2

QDR_BW_n_A3

QDR_R_n_A

QDR_W

_n_A

QDR_C_n_A

QDR_C_A

QDR_BW_n_A[3:0]

R_n_ext_A

QDR_SA_A[17:0]

QDR_DW

RITE_A[35:0]

QDR_K_n_A

QDR_K_A

QDR_R_n_A

QDR_W

_n_A

QDR_C_A

QDR_C_n_A

QDR_BW_n_A[3:0]

+0.9V_FPGA

+0.9V_FPGA

+1.8V +1.8V

+1.8V

+0.9V_FPGA +1.8V

GND_SIGNAL

+0.9V_FPGA

R_n_ext_A

Title

Size

Document Number

Rev

Date:

Sheet

of

<Doc>

11


B

17

28

03/15/04 08:49:

11

BANK6

QDRII SRAM 1 Memory Interface 36 bit

QDR_DWRITE_A[35:0] and QDR_SA_A[17:0]

OUT

C373

0.1uF

R122

51

BANK6

U6G

XC2VP20

IO_L01P_6/VRN_6

AJ30

IO_L01N_6/VRP_6

AJ31

IO_L02P_6

AJ27

IO_L02N_6

AJ28

IO_L03P_6

AK31

IO_L03N_6/VREF_6

AK32

IO_L04P_6

AH29

IO_L04N_6

AH30

IO_L05P_6

AH27

IO_L05N_6

AG28

IO_L06P_6

AL33

IO_L06N_6

AL34

IO_L31P_6

AF31

IO_L31N_6

AF32

IO_L32P_6

AC25

IO_L32N_6

AC26

IO_L33P_6

AG33

IO_L33N_6/VREF_6

AG34

IO_L34P_6

AE30

IO_L34N_6

AE31

IO_L35P_6

AD27

IO_L35N_6

AD28

IO_L36P_6

AF33

IO_L36N_6

AE33

IO_L37P_6

AD29

IO_L37N_6

AD30

IO_L38P_6

AB25

IO_L38N_6

AB26

IO_L39P_6

AD31

IO_L39N_6/VREF_6

AD32

IO_L40P_6

AC28

IO_L40N_6

AC29

IO_L41P_6

AB27

IO_L41N_6

AB28

IO_L42P_6

AE34

IO_L42N_6

AD34

IO_L43P_6

AC31

IO_L43N_6

AC32

IO_L44P_6

AA25

IO_L44N_6

AA26

IO_L45P_6

AD33

IO_L45N_6/VREF_6

AC33

IO_L46P_6

AB29

IO_L46N_6

AB30

IO_L47P_6

AA27

IO_L47N_6

AA28

IO_L48P_6

AB31

IO_L48N_6

AB32

IO_L49P_6

AA29

IO_L49N_6

AA30

IO_L50P_6

Y25

IO_L50N_6

Y26

IO_L51P_6

AC34

IO_L51N_6/VREF_6

AB34

IO_L52P_6

AA31

IO_L52N_6

AA32

IO_L53P_6

W25

IO_L53N_6

W26

IO_L54P_6

AB33

IO_L54N_6

AA33

IO_L55P_6

Y28

IO_L55N_6

Y29

IO_L56P_6

W27

IO_L56N_6

W28

IO_L57P_6

Y31

IO_L57N_6/VREF_6

Y32

IO_L58P_6

W29

IO_L58N_6

W30

IO_L59P_6

W24

IO_L59N_6

V24

IO_L60P_6

AA34

IO_L60N_6

Y34

IO_L85P_6

W31

IO_L85N_6

W32

IO_L86P_6

V25

IO_L86N_6

V26

IO_L87P_6

Y33

IO_L87N_6/VREF_6

W33

IO_L88P_6

V29

IO_L88N_6

V30

IO_L89P_6

V27

IO_L89N_6

V28

IO_L90P_6

V31

IO_L90N_6

V32

VCCO_6_1

V23

VCCO_6_2

W23

VCCO_6_3

Y23

VCCO_6_4

Y24

VCCO_6_5

Y30

VCCO_6_6

AA23

VCCO_6_7

AA24

VCCO_6_8

AB23

VCCO_6_9

AB24

VCCO_6_10

AC24

VCCO_6_11

AE29

VCCO_6_12

AJ32

R97

51

C434

0.1uF



SchematicsR

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

QDR_DREA

D_A0

QDR_DREA

D_A1

QDR_DREA

D_A2

QDR_DREA

D_A3

QDR_DREA

D_A4

QDR_DREA

D_A5

QDR_DREA

D_A6

QDR_DREA

D_A7

QDR_DREA

D_A8

QDR_DREA

D_A9

QDR_DREAD_A10

QDR_DREAD_A11

QDR_DREAD_A12

QDR_DREAD_A13

QDR_DREAD_A14

QDR_DREAD_A15

QDR_DREAD_A16

QDR_DREAD_A17

QDR_DREAD_A18

QDR_DREAD_A19

QDR_DREAD_A20

QDR_DREAD_A21

QDR_DREAD_A22

QDR_DREAD_A23

QDR_DREAD_A24

QDR_DREAD_A25

QDR_DREAD_A26

QDR_DREAD_A27

QDR_CQ_A

QDR_DREAD_A[35:0]

QDR_DREAD_A28

QDR_DREAD_A29

QDR_DREAD_A30

QDR_DREAD_A31

QDR_DREAD_A32

QDR_DREAD_A33

QDR_DREAD_A34

QDR_DREAD_A35

QDR_CQ_n_A

R_n_int_A

QDR_CQ_n_A

QDR_CQ_A

QDR_DREAD_A[35:0]

+0.9V_FPGA

+0.9V_FPGA

+1.8V

+0.9V_FPGA

+1.8V

+1.8V

+1.8V

+1.8V

+1.8V

+1.8V

GND_SIGNAL

+0.9V_FPGA

R_n_ext_A

Title

Size

Document Number

Rev

Date:

Sheet

of

<Doc>

11


B

18

28

03/15/04 08:49:

11

BANK7

QDRII SRAM 1 (A) Memory Interface 36 bit

QDR_DREAD_A[35:0]

IN

R302100

R99

51

R509100

C374

0.1uF

R5100

R508100

R526100

C435

0.1uF

R98

51

BANK7

U6H

XC2VP20

IO_L90P_7

U32

IO_L90N_7

U31

IO_L89P_7

U28

IO_L89N_7

U27

IO_L88P_7

V33

IO_L88N_7/VREF_7

U33

IO_L87P_7

U30

IO_L87N_7

U29

IO_L86P_7

U26

IO_L86N_7

U25

IO_L85P_7

T32

IO_L85N_7

T31

IO_L60P_7

T30

IO_L60N_7

T29

IO_L59P_7

T28

IO_L59N_7

T27

IO_L58P_7

T33

IO_L58N_7/VERF_7

R33

IO_L57P_7

R32

IO_L57N_7

R31

IO_L56P_7

T26

IO_L56N_7

T25

IO_L55P_7

R34

IO_L55N_7

P34

IO_L54P_7

R29

IO_L54N_7

R28

IO_L53P_7

U24

IO_L53N_7

T24

IO_L52P_7

P32

IO_L52N_7/VREF_7

P31

IO_L51P_7

P30

IO_L51N_7

P29

IO_L50P_7

R26

IO_L50N_7

R25

IO_L49P_7

P33

IO_L49N_7

N33

IO_L48P_7

N32

IO_L48N_7

N31

IO_L47P_7

P28

IO_L47N_7

P27

IO_L46P_7

N34

IO_L46N_7/VREF_7

M34

IO_L45P_7

N30

IO_L45N_7

N29

IO_L44P_7

P26

IO_L44N_7

P25

IO_L43P_7

M32

IO_L43N_7

M31

IO_L42P_7

L32

IO_L42N_7

L31

IO_L41P_7

N28

IO_L41N_7

N27

IO_L40P_7

M33

IO_L40N_7/VREF_7

L33

IO_L39P_7

M29

IO_L39N_7

M28

IO_L38P_7

N26

IO_L38N_7

N25

IO_L37P_7

L34

IO_L37N_7

K34

IO_L36P_7

L30

IO_L36N_7

L29

IO_L35P_7

L28

IO_L35N_7

L27

IO_L34P_7

K33

IO_L34N_7/VREF_7

J33

IO_L33P_7

K31

IO_L33N_7

K30

IO_L32P_7

M26

IO_L32N_7

M25

IO_L31P_7

H34

IO_L31N_7

H33

IO_L06P_7

F31

IO_L06N_7

F30

IO_L05P_7

J28

IO_L05N_7

J27

IO_L04P_7

E34

IO_L04N_7/VREF_7

E33

IO_L03P_7

E32

IO_L03N_7

E31

IO_L02P_7

F28

IO_L02N_7

F27

IO_L01P_7/VRN_7

D34

IO_L01N_7/VRP_7

D33

VCCO_7_1

T23

VCCO_7_2

U23

VCCO_7_3

F32

VCCO_7_4

K29

VCCO_7_5

M24

VCCO_7_6

N23

VCCO_7_7

N24

VCCO_7_8

P23

VCCO_7_9

P24

VCCO_7_10

R23

VCCO_7_11

R24

VCCO_7_12

R30

R510100




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

FPGA_D0

FPGA_TDO

SYSACE_TDO

TCK

TMS

DONE

SYSACE_TDO

SYSACE_CFGINIT#

SYSACE_CFGPROG#

TCK

TMS

FPGA_TDO

+2.5V

+5V

+2.5V

+3.3V

+3.3V

+5V

+2.5V

+1.5V

+2.5V

+2.5V+1.5V

+1.5V

+3.3V

+2.5V

+2.5V

FPGA_D0

+1.5V

+2.5V

+5V

GND_SIGNAL

+3.3V

DONE

Title

Size

Document Number

Rev

Date:

Sheet

of

<Doc>

5


B

19

28

03/15/04 08:49:

10

MISC CONFIGURATION and POWER5

VGND

For use with SysAce driving the JTAG

chain,jumper P8-5 and P8-6

CCLK

DONE

DIN

PROG

INIT

to D0 pin on Bank4

Do Not Install

INIT

DONE


XCONFIG

active low

1 2 3456

R105

10K

VCCINT

U6K

XC2VP20

VCCINT1

L11

VCCINT2

L24

VCCINT3

M12

VCCINT4

M23

VCCINT5

N13

VCCINT6

N14

VCCINT7

N15

VCCINT8

N16

VCCINT9

N17

VCCINT10

N18

VCCINT11

N19

VCCINT12

N20

VCCINT13

N21

VCCINT14

N22

VCCINT15

P13

VCCINT16

P22

VCCINT17

R13

VCCINT18

R22

VCCINT19

T13

VCCINT20

T22

VCCINT21

U13

VCCINT22

U22

VCCINT23

V13

VCCINT24

V22

VCCINT25

W13

VCCINT26

W22

VCCINT27

Y13

VCCINT28

Y22

VCCINT29

AA13

VCCINT30

AA22

VCCINT31

AB13

VCCINT32

AB14

VCCINT33

AB15

VCCINT34

AB16

VCCINT35

AB17

VCCINT36

AB18

VCCINT37

AB19

VCCINT38

AB20

VCCINT39

AB21

VCCINT40

AB22

VCCINT41

AC12

VCCINT42

AC23

VCCINT43

AD11

VCCINT44

AD24

VCCAUX

U6J

XC2VP20

VCCAUX1

C3

VCCAUX2

C4

VCCAUX3

C17

VCCAUX4

C18

VCCAUX5

C31

VCCAUX6

C32

VCCAUX7

D3

VCCAUX8

D32

VCCAUX9

U1

VCCAUX10

V1

VCCAUX11

U34

VCCAUX12

V34

VCCAUX13

AL3

VCCAUX14

AL32

VCCAUX15

AM3

VCCAUX16

AM4

VCCAUX17

AM17

VCCAUX18

AM18

VCCAUX19

AM31

VCCAUX20

AM32

R102

10K

P26

HEADER 3

1 2 3

R1104.7K

R304

4.7K

GND2

U6M

XC2VP20

GND79

W1

GND81

W15

GND82

W16

GND83

W17

GND84

W18

GND85

W19

GND86

W20

GND87

W21

GND88

W34

GND89

Y8

GND90

Y14

GND91

Y15

GND92

Y16

GND93

Y17

GND94

Y18

GND95

Y19

GND96

Y20

GND97

Y21

GND98

Y27

GND99

AA14

GND100

AA15

GND101

AA16

GND102

AA17

GND103

AA18

GND104

AA19

GND105

AA20

GND106

AA21

GND107

AC5

GND108

AC8

GND109

AC27

GND110

AC30

GND111

AE3

GND112

AE32

GND113

H23

GND114

AG8

GND115

AG12

GND116

AG15

GND117

AG20

GND140

AN34

GND139

AN1

GND138

AM34

GND137

AM33

GND136

AM25

GND135

AM19

GND134

AM16

GND132

AM2

GND131

AM1

GND130

AL31

GND129

AL4

GND128

AK30

GND127

AK23

GND126

AK12

GND125

AK5

GND124

AJ29

GND133

AM10

GND80

W14

GND118

AG23

GND119

AG27

GND120

J34

GND121

AH7

GND122

AH28

GND123

AJ6

R113

4.7K

P9

HEADER 9

1 2 3 4 5 6 7 8 9

MISC

U6I

XC2VP20

CCLK

AE9

PROG_B

J26

DONE

AE10

M0

AF26

M1

AE26

M2

AE25

HSWAP_EN

K25

TCK

J9

TDI

H28

TDO

H7

TMS

K10

PWRDWN_B

AF9

DXN

G27

DXP

K26

VBATT

K9

RSVD

G8

IO_L01P_4/INIT_B

AL6

G

SDQ2

BSS138

GND1

U6L

XC2VP20

GND1

AF34

GND2

B34

GND3

C1

GND4

C2

GND5

C10

GND6

C16

GND7

C19

GND8

C25

GND9

C33

GND10

C34

GND11

D4

GND12

D31

GND13

E5

GND14

E12

GND15

E23

GND16

E30

GND17

F6

GND18

F29

GND19

G7

GND20

G28

GND21

B1

GND22

H8

GND23

H12

GND24

H15

GND25

H20

GND26

J1

GND27

H27

GND28

AF1

GND29

K3

GND30

K32

GND31

M5

GND32

M8

GND33

M27

GND34

M30

GND35

P14

GND36

P15

GND37

P16

GND38

P17

GND39

P18

GND78

V21

GND77

V20

GND76

V19

GND75

V18

GND74

V17

GND73

V16

GND72

V15

GND71

V14

GND70

U21

GND68

U19

GND67

U18

GND66

U17

GND65

U16

GND64

U15

GND63

U14

GND62

T34

GND61

T21

GND60

T20

GND59

T19

GND58

T18

GND57

T17

GND55

T15

GND54

T14

GND53

T1

GND52

R27

GND51

R21

GND50

R20

GND49

R19

GND48

R18

GND47

R17

GND69

U20

GND56

T16

GND40

P19

GND41

P20

GND42

P21

GND43

R8

GND44

R14

GND45

R15

GND46

R16

SW3

SW DIP-3

R103

10K

R111

4.7K

R305

4.7K

R101

4.7K

P8

HEADER 6X2

2 4 6 810

12

1 3 5 7 9 11

D3

RED

12

R104

10K

R1084.7K

G

SDQ1

BSS138

R112

270

SW4

SW PUSHBUTTON

R306

4.7K

R1094.7K

R107220

D4

GRN

12

R100

100



SchematicsR

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

+2.5V

+2.5V

+2.5V

GND_SIGNAL

Title

Size

Document Number

Rev

Date:

Sheet

of

<Doc>

0


B

20

28

03/15/04 08:49:

11

MGTs BANK0

BANK1 MGT

U6Q

XC2VP20

TXNPAD7

A17

TXPPAD7

A16

RXNPAD7

A14

RXPPAD7

A15

AVCCAUXTX7

B16

VTTXPAD7

B17

GNDA7

C15

VTRXPAD7

B15

AVCCAUXRX7

B14

TXNPAD9

A9

TXPPAD9

A8

RXNPAD9

A6

RXPPAD9

A7

AVCCAUXTX9

B8

VTTXPAD9

B9

GNDA6

C8

VTRXPAD9

B7

AVCCAUXRX9

B6

BANK5 MGT

U6S

XC2VP20

TXNPAD19

AP21

TXPPAD19

AP20

RXNPAD19

AP18

RXPPAD19

AP19

AVCCAUXTX19

AN20

VTTXPAD19

AN21

GNDA19

AM20

VTRXPAD19

AN19

AVCCAUXRX19

AN18

TXNPAD21

AP29

TXPPAD21

AP28

RXNPAD21

AP26

RXPPAD21

AP27

AVCCAUXTX21

AN28

VTTXPAD21

AN29

GNDA21

AM27

VTRXPAD21

AN27

AVCCAUXRX21

AN26

BANK4 MGT

U6R

XC2VP20

TXNPAD16

AP9

TXPPAD16

AP8

RXNPAD16

AP6

RXPPAD16

AP7

AVCCAUXTX16

AN8

VTTXPAD16

AN9

GNDA16

AM8

VTRXPAD16

AN7

AVCCAUXRX16

AN6

TXNPAD18

AP17

TXPPAD18

AP16

RXNPAD18

AP14

RXPPAD18

AP15

AVCCAUXTX18

AN16

VTTXPAD18

AN17

GNDA18

AM15

VTRXPAD18

AN15

AVCCAUXRX18

AN14

L4

HZ0805E601R-00

12

BANK0 MGT

U6P

XC2VP20

TXNPAD4

A29

TXPPAD4

A28

RXNPAD4

A26

RXPPAD4

A27

AVCCAUXTX4

B28

VTTXPAD4

B29

GNDA4

C27

VTRXPAD4

B27

AVCCAUXRX4

B26

TXNPAD6

A21

TXPPAD6

A20

RXNPAD6

A18

RXPPAD6

A19

AVCCAUXTX6

B20

VTTXPAD6

B21

GNDA6

C20

VTRXPAD6

B19

AVCCAUXRX6

B18




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

GND_SIGNAL

Title

Size

Document Number

Rev

Date:

Sheet

of

<Doc>

0


B

21

28

03/15/04 08:49:

11

NO CONNECTS

BANK NO CONNS

U6N

XC2VP20

NC0_7

G24

NC0_8

G23

NC0_3

D28

NC0_13

J22

NC0_6

H24

NC0_2

E24

NC0_1

F24

NC0_5

C28

NC0_12

K22

NC0_11

D27

NC0_9

F23

NC0_10

E27

NC1_1

J13

NC1_2

K13

NC1_3

D8

NC1_4

E8

NC1_5

F12

NC1_6

G12

NC1_7

G11

NC1_8

H11

NC1_9

C7

NC1_10

D7

NC1_11

E11

NC1_12

F11

NC2_1

G4

NC2_2

G3

NC2_3

G6

NC2_4

G5

NC2_5

F2

NC2_6

F1

NC2_7

L10

NC2_8

L9

NC2_9

H6

NC2_10

H5

NC2_11

G2

NC2_12

G1

NC3_1

AH1

NC3_2

AH2

NC3_3

AE7

NC3_4

AE8

NC3_5

AF5

NC3_6

AF6

NC3_7

AG3

NC3_8

AG4

NC3_9

AD9

NC3_10

AD10

NC3_11

AH3

NC3_12

AH4

NC4_1

AE12

NC4_2

AF12

NC4_3

AJ9

NC4_4

AK9

NC4_5

AL9

NC4_6

AM9

NC4_7

AG11

NC4_8

AH11

NC4_9

AH12

NC4_10

AJ12

NC4_11

AK10

NC4_12

AL10

NC5_1

AL25

NC5_2

AK25

NC5_3

AJ23

NC5_4

AH23

NC5_5

AH24

NC5_6

AG24

NC5_7

AM26

NC5_8

AL26

NC5_9

AK26

NC5_10

AJ26

NC5_11

AF23

NC5_12

AE23

NC6_1

AG29

NC6_2

AG30

NC6_3

AK33

NC6_4

AK34

NC6_5

AF27

NC6_6

AF28

NC6_7

AJ33

NC6_8

AJ34

NC6_9

AH31

NC6_10

AH32

NC6_11

AD25

NC6_12

AD26

NC7_1

H32

NC7_2

H31

NC7_3

K28

NC7_4

K27

NC7_5

J32

NC7_6

J31

NC7_7

J30

NC7_8

J29

NC7_9

G34

NC7_10

G33

NC7_11

H30

NC7_12

H29

NC2_13

J6

NC2_14

J5

NC2_15

J4

NC2_16

J3

NC2_17

K8

NC2_18

K7

NC2_19

H4

NC2_20

H3

NC3_13

AJ1

NC3_14

AJ2

NC3_15

AF7

NC3_16

AF8

NC3_17

AK1

NC3_18

AK2

NC3_19

AG5

NC3_20

AG6

NC6_13

AG31

NC6_14

AG32

NC6_15

AF29

NC6_16

AF30

NC6_17

AE27

NC6_18

AE28

NC6_19

AH33

NC6_20

AH34

NC7_13

L26

NC7_14

L25

NC7_15

F34

NC7_16

F33

NC7_17

G30

NC7_18

G29

NC7_19

G32

NC7_20

G31

MGT NO CONNS

U6O

XC2VP20

PAD2_NC1

B32

PAD2_NC2

B33

PAD2_NC3

A33

PAD2_NC4

A32

PAD2_NC5

C30

PAD2_NC6

A31

PAD2_NC7

A30

PAD2_NC8

B31

PAD2_NC9

B30

PAD5_NC1

B24

PAD5_NC2

B25

PAD5_NC3

A25

PAD5_NC4

A24

PAD5_NC5

C23

PAD5_NC6

A23

PAD5_NC7

A22

PAD5_NC8

B23

PAD5_NC9

B22

PAD8_NC1

B12

PAD8_NC2

B13

PAD8_NC3

A13

PAD8_NC4

A12

PAD8_NC5

C12

PAD8_NC6

A11

PAD8_NC7

A10

PAD8_NC8

B11

PAD8_NC9

B10

PAD11_NC1

B4

PAD11_NC2

B5

PAD11_NC3

A5

PAD11_NC4

A4

PAD11_NC5

C5

PAD11_NC6

A3

PAD11_NC7

A2

PAD11_NC8

B3

PAD11_NC9

B2

PAD14_NC1

AN2

PAD14_NC2

AN3

PAD14_NC3

AP2

PAD14_NC4

AP3

PAD14_NC5

AM5

PAD14_NC6

AP4

PAD14_NC7

AP5

PAD14_NC8

AN5

PAD14_NC9

AN4

PAD17_NC1

AN10

PAD17_NC2

AN11

PAD17_NC3

AP10

PAD17_NC4

AP11

PAD17_NC5

AM12

PAD17_NC6

AP12

PAD17_NC7

AP13

PAD17_NC8

AN13

PAD17_NC9

AN12

PAD20_NC1

AN22

PAD20_NC2

AN23

PAD20_NC3

AP22

PAD20_NC4

AP23

PAD20_NC5

AM23

PAD20_NC6

AP24

PAD20_NC7

AP25

PAD20_NC8

AN25

PAD20_NC9

AN24

PAD23_NJC1

AN30

PAD23_NJC2

AN31

PAD23_NJC3

AP30

PAD23_NJC4

AP31

PAD23_NJC5

AM30

PAD23_NJC6

AP32

PAD23_NJC7

AP33

PAD23_NJC8

AN33

PAD23_NJC9

AN32



SchematicsR

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

LCD_DATA0

LCD_DATA1

LCD_DATA2

LCD_DATA3

LCD_DATA4

LCD_DATA5

LCD_DATA6

LCD_RS

LCD_R_W#

LCD_DB[7:0]

LCD_DB0

LCD_DB1

LCD_DB2

LCD_DB3

LCD_DB4

LCD_DB5

LCD_DB6

LCD_DATA7

LCD_DB7

LCD_E

LCD_RD/WR

LCD_REGSEL

LCD_DRIVE

LCD_EN

LCD_RS

LCD_R_W#

LCD_E

LCD_DB[7:0]

+3.3V

+5V

GND_SIGNAL

+3.3V

+5V

+3.3V

+5V

Title

Size

Document Number

Rev

Date:

Sheet

of

<Doc>

0

ML365 QD


B

22

28

01/22/04 0

9:07:47

LCD CONNECTOR

1x16 INLINE .025SQ. PINS

16 char x 2 line

Seiko L167100J000

This LCD requires two rows of 16 pins to support it physically

Place the 1X16 SIP headers 31mm apart per the LCD spec sheet

LCD

this divider should give approx. 0.1V at junction

LVCMOS25

+5V TTL

+2.5V

2.3v to 3.6V

supply

U3

MC74LCX541DT

/OE1

1

/OE2

19

D0

2

D1

3

D2

4

D3

5

D4

6

D5

7

D6

8

D7

9

GND

10

VCC3.3

20

O7

11

O6

12

O5

13

O4

14

O3

15

O2

16

O1

17

O0

18

U2

MC74LCX541DT

/OE1

1

/OE2

19

D0

2

D1

3

D2

4

D3

5

D4

6

D5

7

D6

8

D7

9

GND

10

VCC3.3

20

O7

11

O6

12

O5

13

O4

14

O3

15

O2

16

O1

17

O0

18

R34

100

P4

HEADER 161 2 3 4 5 6 7 8 9 10

11

12

13

14

15

16

P5

HEADER 161 2 3 4 5 6 7 8 9 10

11

12

13

14

15

16

R35

4.7K




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

R1IN

RX

RS232_T1IN

RS232_R1OUT

T1OUT

TXRS232_T1IN

RS232_R1OUT

+2.5V

GND_SIGNAL

+2.5V

+2.5V

Title

Size

Document Number

Rev

Date:

Sheet

of

<Doc>

0

ML365 QD


B

23

28

01/22/04 0

9:07:48

RS232 DRIVER

GND1/2 are mounting holes

DB9 Female

check pin 2 and 3 for RX and TX

C13

0.1uF

R36

100

C12

0.1uF

TSSOP20

U4

MAX3316ECUP

C1P

2

C1N

4

T1IN

14

T1OUT

17

R1IN

16

R1OUT

15

VN7

VP3

C2P

5

GND 18

T2IN

13

T2OUT

8

R2OUT

12

R2IN

9VCC19

C2N

6

NC1

1

NC2

10

NC3

11

NC4

20

J5

CONN_DSUB_9-S

16

27

38

49

5

GND1

GND2

L1

HZ0805E601R-00

12

C11

0.1uF

R37

100C10

0.1uF

C14

0.1uF

L2

HZ0805E601R-00

12



SchematicsR

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

INPU

T_+5V

+5V

+3.3V

+2.5V

GND_SIGNAL

+1.5V

+1.5V

+5V

+3.3V

+5V

+2.5V

+5V

+5V

+5V

+2.5V

+5V

+3.3V

+5V

+5V

+1.5V

+5V

+3.3V

+2.5V

GND_SIGNAL

+1.5V

Title

Size

Document Number

Rev

Date:

Sheet

of

<Doc>

0

ML365 QD


B

24

28

01/22/04 0

9:07:45

1.5V VCCINT for FPGA

FY11

11C

Vfwd

= 1

.9V

If =

20mA

2.5V VCCAUX for FPGA

FR11

11C

Vfwd

= 1

.9V

If =

20mA

3.3V = Blue

1.5V = Yellow

5V = Red

2.5V = Green

Fixed 2.5V vertical

+1.5V @ 3A

Fixed 3.3V vertical

+3.3V @ 3A

Fixed 2.5V vertical

+2.5V @ 3A

PG11

12C

Vfwd

= 2

.2V

If =

20mA

DB11

11C

Vfwd

= 3

.3V

If =

10mA

may be too high, s/b 3.3K

change to blue?

Slide switch is for ON - OFF

5V input via barrel jack

Make layout template and duplicate for each reg.

LOCAL POWER REGULATION

U10

PT5501N

INH1

VoADJ5

Vin

2Vo

4

GND 3

MH1

6

MH2

7MH3

8

MH4

9

P15

HEADER 1

1

G

SDQ4BSS138

D9

RED

12

R124

1K

+C346

10uF

1 2

+C357

100uF

1 2

G

SDQ5BSS138

R1284.7K

U7

PT5505N

INH1

VoADJ5

Vin

2Vo

4

GND 3

MH1

6

MH2

7MH3

8

MH4

9

P13

HEADER 1

1

D7

GRN

12

SW8

SLIDE_DPDT

CK-L202MS02

13 2

4

56

D6

YEL

12

+C363

100uF

1 2

G

SDQ3BSS138

C356

1uF

R123

4.7K

R132

1K

+C287

10uF

1 2

P10

HEADER 1

1

+C29

330uF

1 2

+C361

100uF

1 2

P14

HEADER 1

1

U9

PT5502N

INH1

VoADJ5

Vin

2Vo

4

GND 3

MH1

6

MH2

7MH3

8

MH4

9

R1274.7K

C362

1uF

D5

BLUE

12

P11

HEADER 1

1

C359

1uF

R1254.7K

R131

1K

J4

Barrel Jack

PJ002ASM

11

22

33




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

GND_SIGNAL

+1.8V

+0.9V_FPGA

+0.9V_QDR

+5V

+5V

+1.8V

+1.8V

+5V

+0.9V_FPGA

+0.9V_QDR

+1.8V

+0.9V_QDR

+0.9V_FPGA

GND_SIGNAL

+1.8V

+5V

+0.9V_FPGA

+0.9V_QDR

+0.9V_QDR

Title

Size

Document Number

Rev

Date:

Sheet

of

<Doc>

5

ML365 QD


B

25

28

01/22/04 0

9:07:45

LOCAL POWER REGULATION

+1.8V @ 8A

Panasonic ETQP6F2R5SFA 2.5uH 10.8A 5 mOhm

Do NOT Install

PG11

12C

Vfwd

= 2

.2V

If =

20mA

1206

+0.9V for FPGA

1.8V for FPGA and QDR

1.8V = Green

0603

0603

1206

X7R

X7R

JW M

ille

rPM

1812

-2R2J

2.2u

H 38

0mA

1812

Nominal 0.9V for QDR ref

+0.9V for QDR

1206

+0.6V to +1.2V ref for FPGA

Ceramic X5R 0805 6.3V

CD ESRE151M06R

C385

10uF

R1264.7K

L5

2.5uH

R307

4.7K

R308

3.48K 1%

R135

1K

R310

287 1%

P16

HEADER 1

1

C383

180pF

C379

0.018uF

+C386

150uF_AlumPoly

1 2

L3

PM1812-2R2J

12

C382

5600pF

C296

0.001uF

R129

22.6

C378

10uF

U13

TPS54810

AGND

1

VSENSE

2

COMP

3

PWRGD

4

BOOT

5

PH1

6

PH2

7

PH3

8

PH4

9

PH5

10

PH6

11

PH7

12

PH8

13

PH9

14

PGND1

15

PGND2

16

PGND3

17

PGND4

18

PGND5

19

VIN1

20

VIN2

21

VIN3

22

VIN4

23

VIN5

24

VBIAS

25

SS/ENA

26

SYNC

27

RT

28

PowerPad 29

G

SDQ6BSS138

R133

1K

R130

50_25turn

1 3

2

P17

HEADER 1

1

+C297

330uF

1 2

C377

10uF

R311

9.76K 1%

D8

GRN

12

C298

0.01uF

R536

1K_25turn

1 3

2

C381

0.047uF

+C376

220uF

1 2

C384

3900pF

R134

1K

P18

HEADER 1

1

R309

10.0K 1%

+C28

330uF

1 2

C380

0.1uF

R312

0



SchematicsR

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

+1.5V

+1.8V

+2.5V

+0.9V_FPGA

+0.9V_QDR

+0.9V_QDR

+2.5V

+1.8V

+0.9V_FPGA

+1.5V

+2.5V

+1.8V

+0.9V_FPGA

+0.9V_QDR

GND_SIGNAL

+1.5V

Title

Size

Document Number

Rev

Date:

Sheet

of

<Doc>

9

ML365 QD


B

26

28

01/22/04 0

9:07:44

DECOUPLING

VCCINT 1.5V

VCCo 1.8V

VCCAUX +2.5V

VREF 0.9V

XC2VP20 Vref decoupling

ALL non-Tantalum caps are X7R or X5R

+C58

33uF

1 2

C111

0.01uF

C320

0.047uF

C85

0.01uF

C55

0.01uF

C87

0.01uF

C31

0.047uF

C299

2.2uF

C351

0.047uF

C131

0.01uF

C330

0.047uF

C26

0.047uF

C294

2.2uF

C354

0.047uF

C125

0.01uF

C322

0.047uF

C20

0.047uF

C93

0.01uF

C107

0.01uF

C151

0.01uF

C32

0.047uF

+C302

330uF

1 2

C144

0.01uF

C301

2.2uF

C50

0.01uF

C176

0.01uF

C100

0.01uF

C328

0.047uF

C315

0.047uF

C179

0.01uF

C332

0.047uF

C57

0.01uF

C135

0.01uF

C293

2.2uF

C99

0.01uF

C185

0.01uF

C145

0.01uF

C327

0.047uF

C71

0.01uF

C21

0.047uF

C184

0.01uF

C338

0.047uF

C101

0.01uF

C110

0.01uF

C160

2.2uF

C305

2.2uF

C235

2.2uF

C132

0.01uF

+C42

33uF

1 2C49

0.01uF

C134

0.01uF

+C335

33uF

1 2

C121

0.01uF

C51

0.01uF

C337

0.047uF

C333

0.047uF

C336

0.047uF

C115

0.01uF

C78

0.01uF

C61

0.01uF

C289

2.2uF

C117

0.01uF

C92

0.01uF

C118

0.01uF

C339

0.047uF

C290

2.2uF

C307

0.047uF

C268

2.2uF

C24

0.047uF

C350

0.047uF

C39

0.01uF

C172

0.01uF

C190

2.2uF

+C15

330uF

1 2

C319

0.047uF

C323

0.047uF

C186

0.01uF

C66

0.01uF

C70

0.01uF

C137

0.01uF

C62

0.01uF

C113

0.01uF

C133

0.01uF

C308

0.047uF

C74

0.01uF

C365

0.047uF

C139

0.01uF

C30

0.047uF

C325

0.047uF

C202

2.2uF

+C80

33uF

1 2

+C82

330uF

1 2

C79

0.01uF

C128

0.01uF

C158

0.01uF

C340

0.047uF

C213

2.2uF

+C47

33uF

1 2

C364

0.047uF

+C44

33uF

1 2

C355

0.047uF

C146

0.01uF

C75

0.01uF

+C40

33uF

1 2

C91

0.01uF

C183

0.01uF

C303

2.2uF

C147

0.01uF

C89

0.01uF

C53

0.01uF

C17

0.047uF

C326

0.047uF

C156

0.01uF

C41

0.01uF

C295

2.2uF

C127

2.2uF

C310

0.047uF

C348

0.047uF

C148

0.01uF

C306

0.047uF

C65

0.01uF

C84

0.01uF

C98

0.01uF

C174

0.01uF

C152

0.01uF

C22

0.047uF

C25

0.047uF

C279

2.2uF

C304

2.2uF

C341

0.047uF

C343

0.047uF

C48

0.01uF

C102

0.01uF

C178

0.01uF

C59

0.01uF

C353

0.047uF

C170

0.01uF

C108

0.01uF

C119

0.01uF

C123

0.01uF

C173

0.01uF

C23

0.047uF

C366

0.01uF

C182

0.01uF

C314

0.047uF

C345

0.047uF

C285

2.2uF

C344

0.047uF

C312

0.047uF

C112

0.01uF

C35

0.047uF

+C94

33uF

1 2

C33

0.047uF

C187

0.01uF

C334

0.047uF

C292

2.2uF

C54

0.01uF

+C69

33uF

1 2

C122

0.01uF

C143

0.01uF

C286

2.2uF

+C27

33uF

1 2

C188

0.01uF

C120

0.01uF

C37

0.047uF

+C16

33uF

1 2

C38

0.047uF

C52

0.01uF

C97

0.01uF

C67

0.01uF

C331

0.047uF

C257

2.2uF

C291

2.2uF

C171

0.01uF

C246

2.2uF

C126

0.01uF

C64

0.01uF

C309

0.047uF

C116

2.2uF

C86

0.01uF

C189

0.01uF

+C201

330uF

1 2

C114

0.01uF

C18

0.047uF

C154

0.01uF

C130

0.01uF

C311

0.047uF

+C313

330uF

1 2

C56

0.01uF

C136

0.01uF

C317

0.047uF

+C324

33uF

1 2

C104

0.01uF

C72

0.01uF

C34

0.047uF

C106

0.01uF

C329

0.047uF

C142

0.01uF

C63

0.01uF

C46

0.01uF

C96

0.01uF

C90

0.01uF

C316

0.047uF

C300

2.2uF

C76

0.01uF

C155

0.01uF

C321

0.047uF

C105

2.2uF

C138

2.2uF

+C347

33uF

1 2

C153

0.01uF




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

+3.3V

+5V

+1.8V

+1.8V

+5V

+1.5V

+3.3V

+1.5V

+2.5V

+2.5V

+1.5V

+5V

+1.8V

GND_SIGNAL

+3.3V

+1.5V

+2.5V

Title

Size

Document Number

Rev

Date:

Sheet

of

<Doc>

10


B

27

28

01/22/04 09:07:

45

+3.3V

Additional 1.8V

+5V LCD and RS232

DECOUPLING

Additional 1.5V

Additional 2.5V

Additional 1.5V added 8/14/03 for Rev10

C396

0.01uF

P31

HEADER 1

1

C216

0.047uF

C251

0.047uF

C140

0.01uF

C207

2.2uF

+C199

330uF

1 2

C242

2.2uF

P46

HEADER 1

1

+C273

330uF

1 2

P41

HEADER 1

1

C177

0.01uF

C234

0.01uF

C211

2.2uF

C198

0.01uF

+C43

33uF

1 2

C270

0.01uF

P35

HEADER 1

1

+C240

330uF

1 2

C159

0.01uF

C418

2.2uF

C276

2.2uF

C421

2.2uF

C424

0.01uF

C19

0.047uF

C81

0.01uF

C230

0.01uF

+C412

330uF

1 2

C427

0.01uF

C281

0.047uF

C265

0.01uF

C228

0.01uF

C238

0.01uF

+C205

33uF

1 2

+C415

33uF

1 2

C263

0.01uF

C349

0.047uF

C390

2.2uF

C223

0.01uF

C401

0.01uF

C259

0.01uF

C256

0.047uF

C224

2.2uF

C397

0.01uF

C68

0.01uF

+C83

33uF

1 2

C217

0.047uF

P42

HEADER 1

1

C252

0.047uF

P37

HEADER 1

1

C73

0.01uF

P36

HEADER 1

1

+C200

330uF

1 2

C393

0.01uF

C243

2.2uF

+C274

330uF

1 2

+C237

330uF

1 2

C236

0.01uF

C212

2.2uF

C271

0.01uF

C248

2.2uF

P27

HEADER 1

1

C88

0.01uF

C277

2.2uF

C109

0.01uF

C231

0.01uF

C208

2.2uF

C195

0.01uF

C282

0.047uF

C266

0.01uF

C192

0.01uF

C264

0.01uF

+C241

33uF

1 2

C225

0.01uF

C247

2.2uF

C260

0.01uF

C419

2.2uF

C342

0.047uF

C391

2.2uF

C422

0.01uF

C45

0.01uF

P29

HEADER 1

1

+C410

330uF

1 2

C425

0.01uF

P43

HEADER 1

1

+C413

330uF

1 2

C428

0.01uF

P38

HEADER 1

1

+C416

33uF

1 2

C149

2.2uF

C398

0.01uF

P32

HEADER 1

1

C129

0.01uF

C218

0.047uF

C253

0.047uF

C175

0.01uF

P28

HEADER 1

1

C394

0.01uF

+C275

330uF

1 2

+C191

330uF

1 2

C214

0.047uF

C272

0.01uF

C249

2.2uF

C150

0.01uF

C181

0.01uF

C232

0.01uF

C209

2.2uF

C196

0.01uF

+C203

330uF

1 2

C283

0.047uF

C267

0.01uF

C244

2.2uF

C193

0.01uF

C180

2.2uF

P30

HEADER 1

1

C278

2.2uF

C226

0.01uF

P44

HEADER 1

1

C261

0.01uF

P39

HEADER 1

1

C141

0.01uF

P33

HEADER 1

1

C221

0.01uF

C399

0.01uF

C392

2.2uF

C318

0.047uF

C124

0.01uF

C219

0.047uF

C254

0.047uF

C95

0.01uF

C395

0.01uF

+C389

33uF

1 2

C420

2.2uF

C423

0.01uF

C215

0.047uF

+C411

330uF

1 2

C426

0.01uF

C36

0.047uF

C250

0.047uF

+C414

33uF

1 2

C429

0.01uF

C77

0.01uF

C206

2.2uF

+C239

330uF

1 2

+C417

33uF

1 2

C103

0.01uF

C233

0.01uF

C210

2.2uF

C197

0.01uF

C284

0.047uF

C269

0.01uF

C245

2.2uF

C194

0.01uF

P45

HEADER 1

1

P40

HEADER 1

1

C229

0.01uF

P34

HEADER 1

1

C280

2.2uF

C227

0.01uF+

C204

330uF

1 2

+C288

330uF

1 2

C262

0.01uF

C222

0.01uF

C400

0.01uF

C258

0.01uF

C352

0.047uF

C220

0.047uF

C255

0.047uF

C157

0.01uF

+C388

330uF

1 2



SchematicsR

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Title

Size

Document Number

Rev

Date:

Sheet

of

<Doc>

12


B

28

28

03/15/04 08:49:

12

Rev Notes

Rev# Sheet# Description

0 All Initial Release

1 Change Bank2, Bank7 pinout per Olivier Despaux

2 Change Bank7 pinout R_n_int_A from L30 to P29 per Olivier Despaux

3 Change +3.3V on P3.2 to +2.5V (P3 is 2mm PC IV cable connector)

4 Add additional +1.5V decoupling caps, add 20 GND TP

5 Change QDR term pullup R’s from 50 ohm to 100 ohm, add 100 ohm pulldown R’s

Change QDR CQ/CQ_n term R’s to pullup/pulldown 100 ohm scheme

Change QDR R_n_ext_* term R’s to pullup/pulldown 100 ohm scheme

Tied all unused FPGA Bank pins to GND

Wired FPGA DONE signal to Bank3.AH8

Added 1K 25 turn trimpot to +0.9V_FPGA vref to give +0.6V to +1.2V adjustment

Change TPS54610 1.8V@6A to TPS54810 1.8V @ 8A power

6 Updated component footprints only, no changes to schematic

7 Added P47 2x1 header wired to Bank4 for logic analyzer clock

8 Changed existing 51 ohm 0402 R’s to 100 ohm: QDR1 R276-R281, QDR2 R282-R287, QDR3 R288-R293

9 Changed existing decoupling capacitors:

From 1.5V To 2.5V: C318,C149,C224,C159,C88,C150,C77,C140,C73,C175,C95,C157

From 1.8V To 2.5V: C288,C43,C83,C180,C247,C342,C36,C352,C349,C19,C81,C109,C181,C103,C177,C45,C141,C68,C129,C124

10 Added additional +1.5V decoupling caps C410 - C429

11 Added additional 0.1uF filter caps C430-C435 to Bank0, 1, 2, 3, 6, 7 VRP pins

Design formally renamed ML365, first board in Xilinx Memory Toolkit program under Olivier Despaux

12 Bank4, SW6 and SW7, change switch configuration from active low, to active high with pulldown

R537 4.7K 0402 pull down, R538 4.7K 0402 pulldown added




Characterization Results

Long-Term RunsThe significant long-term runs are as follows:

• ML365 Serial 10 ran 215 MHz for 48 hours with no errors

• ML365 Serial 11 ran overnight at 240 MHz and 235 MHz with bit errors (one or more)

• ML635 Serial 11 ran 230 MHz for 144 hours with no errors

Corners Results MatrixThe measurements made on eleven boards are listed in Table 3-1. The slowest performance numbers are:

6C: 210 MHz 6C prod: 237 MHz

7C: 242 MHz 7C prod: 275 MHz

Observations

Memory device Vref levels are very important. They have been adjusted for each single test, and were set up at the optimal value for the memory interface under test. At optimal voltage (1.800V), it appears that 0.900V was, in almost all cases, the optimal setting; variations of 1.8V required significant adjustments of Vref to obtain the best performance (+5% tests can require a +10% increase of Vref).

Table 3-1: Corners Results Measurements

AmbientTemp

VCC

Bd 3 Bd 9 Bd 10 Bd 8 Bd9A Bd 11 Bd 4 Bd 7 Bd 6 Bd B Bd C

-6 Slow -6 Prod -7 Prod -7 Slow

25 Degree C Nom 218 219 223 217 223 247 260 271 284 248 254

Nom -5% 216 218 219 215 219 245 257 267 271 246 253

Nom +5% 219 220 224 218 224 248 263 266 285 249 256

70 Degrees C Nom 213 219 216 212 215 241 257 263 280 243 251

Nom -5% 212 216 214 210 214 237 254 262 275 242 250

Nom +5% 214 220 217 213 215 243 258 263 282 245 252

0 Degrees C Nom 228 230 231 226 229 266 278 273 292 264 268

Nom -5% 224 229 230 226 228 265 278 272 290 263 268

Nom +5% 230 231 232 228 230 267 279 291 302 266 272


Documents

UG119 Virtex-II Pro Memory Board Toolkit€¦ · Memory Board, which connects a Virtex-II Pro FPGA to Quad Data Rate (QDR) memories. Guide Contents This manual contains the following