10 Gbps Serial Backplanes using Virtex-II Pro X

10 Gbps

Serial

Backplanes

using Virtex-II

Pro X

Xilinx, Inc.

2

Networking

Telecom

Computing

Storage

VideoVirtex-4

RocketPHY

Serial I/O Landscape

0.622 1.0 2.0 3.0 5.0 10.0 11.0

OC-12 OC-48 OC-192

GbE XAUI 10GbECEI (OIF)

SATA3

SATA2SATA

1GFC 2GFC

PCIE

HD-SDI

SATAGbE

1.45

1.25 2.51.5 3.0

0.622 2.488

3.1251.25 10.3136.25

1.5 3.0 6.0

1.06 2.12

9.952

10GFC

6.0

10.519

SATA2

Rate (Gb/s)

CEI (OIF)11G

Virtex-II Pro

4GFC4.25

Virtex-II Pro

X

8GFC8.5

3

Introduction• Why are better models, techniques, and tools needed?

– Speed = Problems

• Evolution of a short circuit

– Once interconnects stop behaving as transmission lines, SPICE

models and SPICE like tools can not predict performance

SPEED

A. Fraser, S. Argyrakis, “Does Signal Integrity Engineering have a Future”, DesignCon 2003,.

4

Introduction• Why are better models, techniques, and tools needed?

– Co-dependent terms

• Example: As speed increases, the connector performance

begins to depend on the board integration

?

5

At these high data rates…..

Courtesy: Agilent Technologies – Educator’s corner

6

Without the proper tools….

Rules of Thumb???

7

Estimated Backplane

Prototyping Costs28 Layers, approx 16"X18", 0.240" thick

0

1000

2000

3000

4000

5000

6000

PCB T

oolin

gPC

B Tes

t5

boar

ds (5

-day

)

10 b

oard

s (5

-day

)

5 bo

ards

(4W

KS)

10 b

oard

s (4

WKS)

Assem

bly

Pe r

Bo

ard

Co

st

(in

$)

FR-4

Nelco13

Numbers based on estimates from Whizz Systems

8

Board Re-spins Cost

Time & Money


9

Project Schedules Slip…..

Manager

You!!


10

Physical Channel Design

Challenges

• There can be significant degradation to the data

after it has passed through the transmission path.

– Degradation includes loss of signal amplitude,

reduction of signal rise time, and a spreading at the

zero crossings.

DRIVER RECEIVER

Board

Interconnect

11

Channel is a low-pass filter


12

Virtex Features: Backplanes

Direct interface to other

devices, reduces

component count

YesYesIntegrated AC coupling

Equalizes stringent channel;

allows legacy backplanes

to be upgraded

Linear and

DFELinearReceive Equalization

Yes

Yes

Yes

Yes

Equalizes simple channelsYesYesTransmit Pre-Emphasis

Automatically finds optimum

EQ setting for a given

channel; eases design

and ensures Signal

Integrity

Automatic EQ Settings

Algorithm

Reduces Power

Reduces Reflections

Benefit

YesYesProgrammable Voltage

Swing

YesYesProgrammable

Termination

Feature

13

Equalization Options: Summary

6-tap6-zeros

9-poles

3-tap

(pre- and post-cursor)

-4-zeros

7-poles

2-tap

(post-cursor)

--2-tap

(post-cursor)

DFE Rx

EqualizationDiscrete-time

Linear Rx

EqualizationContinuous-time

Tx

Pre-EmphasisDiscrete-time

Any combination of the three techniques can be combined simultaneously

14

Physical Channel Design

Challenges

• It is critical to model the transmission path whendesigning a high-performance, high-speed serialinterconnect system

– Transmission path may include long transmission lines,connectors, vias and crosstalk from adjacent interconnect

DRIVER RECEIVER

Board

Interconnect

15

So many handles….

16

Enter Gigabit Virtual Design

Kit• Xilinx teamed with Ansoft to provide customers with an

extendable methodology for 10 Gb/s serial channel design

– (Virtex II Pro-X Board design kit available at Xilinx

“SICentral’ website:

http://www.xilinx.com/products/design_resources/highs

peed_design/resource/si_gig.htm)

• Parameterized Board Design Kit for Virtex–II Pro X

• Optimization and rapid what-if analyses made simple, to

serve Xilinx high-speed FPGA customers!!

17

Agenda

• Board Design for Virtex–II Pro X

– BGA Package Modeling

– Transmission Line Models

– Via Modeling

– SMA Connector Modeling

– Using the Models in Nexxim

Simulation = Measurement for nominal

design

18

Design Example: Virtex-II Pro

X Evaluation BoardRX Pair TX Pair

19

Evaluation Board High-Speed

Interconnect

• Transmission path includes the FPGA package, a

differential microstrip transmission line in FR4, a

differential via structure, a stripline transmission

line, and an SMA connectorDRIVER RECEIVER

BGA

Package

Microstrip

Transmission

Line

Differential

Via

SMA

Connector

Stripline

Transmission

Line

20

Design Methodology• Where possible, segregate the system into individual

components

• Chain together the individual components for a complete

system design

Package

Stripline

Microstrip

Connector

Via

FF896 Flip-FF896 Flip-

ChipChip

PackagePackage

22

FF896 Flip Chip Package• TX Differential Pair – HFSS Version 9.2

• 4-Port Single Ended Lumped Ports

Differential S-Parameters

MK322MK322

EvaluationEvaluation

BoardBoard

24

Vias

Microstrip

Stripline

MK322 Evaluation Board•12 Layer Board

•100 Ohm Differential Signaling

•Board Material: FR4

•Trace & Plane Layers: 0.5 oz. copper (0.65 mil thick)

Virtex II Pro X Evaluation Board

TX PairRX Pair

25

MK322 Stack Up

Stripline

Microstrip

26

MK322 Evaluation Board –

Microstrip ModelsDesigner Version 2.0

– Circuit Models

• Multi-Coupled Line Model

– A Four-Layer Substrate stackup was used to account for the solder mask

4-Layer Model

Circuit ModelDifferential S-Parameters

27

• Designer Version 2.0

– PlanarEM used to model Part 7

– Circuit Components used to model Parts 1 – 6

• The stripline is approximately 2.5 inches long

Part1

Part3

Part2

Part4

Part5 Part7

Part6


Stripline Model

28

• MK322 Evaluation Board – Differential Via

– Through Hole Via

• The via will have the largest impact on

the overall channel so it is important to

be able to study the effect of variations

in this structureDifferential S-Parameters


Via Model

29

50 Ohm Stripline Launch on Layer 10

Single-ended S-Parameters

MK322 Evaluation Board

– Connector Model • MK322 Evaluation Board – Differential Via

– Connector model from Rosenberger• Connector ground pin stubs – 37 mils long

• Connector signal pin stub – 22 mils long

• Output for the MK322 board

FullFull

ChannelChannel

ResultsResults

31

Full Channel Model in Designer(frequency domain)

• Nexxim

– Frequency Profile Extraction

• Group Delay

• Transmission (Insertion Loss)

• Reflection (Return Loss)

32

Full Channel Model Results

(frequency domain)

Group Delay

855ps


• Nexxim Circuit Simulator– Frequency Domain Data

• Group Delay

• S-Parameters

33

Full Channel Model in Designer(time domain)

• System Model

– Transient Simulation

– Measurement Correlation

34

• System Model

– Eye Diagram Comparison• Pseudo-Random Bit Source (2^31 – 1 pattern)

• Eye Opening

Full Channel Model Results(time domain)

Xilinx Measured Data

Eye Height = 292 mV

Eye Width = 70.8 ps

Ansoft Designer System Simulator

Eye Height = 318 mV

Eye Width = ~ 90 ps

35

• Quad AAAA Pattern

– Alternating 1’s and 0’s

– Risetime (10-90%)

• System Simulation: ~53ps

• Measured: 51.7ps

Full Channel Model Results(time domain)

What What –– If If

AnalysisAnalysis Alternate Via Route Alternate Via Route

LayersLayers

Alternate Line Alternate Line

LengthsLengths

Alternate Data RatesAlternate Data Rates

37

• Through Hole Via– Parameterized Geometry

• Antipad Radius

• Via Radius

• Via Pad Radius

• Route Layer

• Trace Width

• Ground Via Distance

MK322 Evaluation Board –Differential Via Antipad Radius

Pad RadiusVia Radius

38

• MK322 Evaluation Board –

Differential Via– Through Hole Via

– Parameterized Geometry

• Route Layer

MK322 Evaluation Board –Differential Via

39

• Via Route Layer


• Stripline Traces can be

routed on:

– Layer 3

– Layer 5

– Layer 10 (nominal)


40

• Via Route Layer


• Stripline Traces can be routed on:

– Layer 3

– Layer 5

– Layer 10 (nominal case)

Single-ended S-Parameters



41

•Nominal Length is approximately 2.5 inches

•Data Rate is 10 GbpsLength = 2.5 inches

Length = 5.0 inches

Stripline Length – Eye Diagrams

Length = 7.5 inches

Length = 10.0 inches

42

Stripline Length –

Differential S-Parameters•Nominal length is approximately 2.5 inches

•Frequency swept from 0.1 to 40 GHz

L=2.5 inches

L=5.0 inches

L=7.5 inches

L=10.0 inches

43

•30ps Rise TimeData Rate 2.5 Gbps

Data Rate 3.125 Gbps

Data Rate 5 Gbps

Data Rate 10 Gbps

Data Rate 10 Gbps

Channel – Data Rate

44

These bad boys can be

managed !


45

Surf’s Up!!

46

Board Design Kit

• The models shown in this presentation have been

assembled into a “Design Kit” for Virtex-II Pro-X

customers, which is available at the Xilinx

“SICentral”.

– Design kit will include parameterized HFSS and

Designer models for transmission lines, differential

vias, and connectors

– A white paper that describes the use methodology

will be included

47

Board Design Kit

• Customers of Xilinx and Ansoft may use the

parameterized design kit to evaluate board and

system design in a virtual environment to

accelerate the ability to design high-speed

systems, right the first time!!

48

Additional Considerations

• Predicting pre-emphasis/optimization settings

• Inclusion of driver/receiver models

• SIwave results are being worked on to show post

layout verification… the ability to incorporate

decoupling capacitor strategies into the overall

backplane design

AppendixAppendix

50

• AnsoftLinks 3.0 creates models from the following layout tools:

– Cadence

• APD

• Allegro

• Virtuoso

– Mentor

• Expedition

• Board Station

– Zuken

• CR5000

– Synopsis

• Encore

Translation Path

AnsoftLinks

Zuken Synopsis

Mentor

Cadence

Ansoft

TPA

Ansoft

Q3D

Ansoft

SIWave

Ansoft

HFSS

Ansoft

Designer

51

• Pads to Mentor Expedition

• Mentor Expedition to AnsoftLinks 3.0

Translation Path –

MK322 Board

AnsoftLinks

PADS

Mentor Expedition

Ansoft

SIWaveAnsoft

HFSS

Ansoft

Designer

Documents

10 Gbps Serial Backplanes using Virtex-II Pro X