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Evaluating System-wide Monitoring Capsule Design Using Xilinx Virtex-II Pro FPGA. Taeweon Suh § , Hsien-Hsin S. Lee § , Sally A. Mckee † , and Martin Schulz ♀ § Georgia Institute of Technology , † Cornell University, and ♀ Lawrence Livermore National Laboratory. - PowerPoint PPT Presentation
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Evaluating System-wide Monitoring Evaluating System-wide Monitoring
Capsule Design Capsule Design
Using Xilinx Virtex-II Pro FPGAUsing Xilinx Virtex-II Pro FPGA
Taeweon SuhTaeweon Suh §, Hsien-Hsin S. Lee Hsien-Hsin S. Lee §, Sally A. Mckee Sally A. Mckee †,
and Martin Schulz Martin Schulz ♀
§ Georgia Institute of Technology, Georgia Institute of Technology, † Cornell University, Cornell University, and and ♀ Lawrence Livermore National LaboratoryLawrence Livermore National Laboratory
Georgia Tech, Cornell, LLNL - WARFP 2005
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Overcome traditional sampling, counter-based performance monitoring
Proposed general framework for system-wide monitoring called Owl
Monitoring capsule can be deployed anywhere in a system
Each monitoring capsule consists of FPGA cells to hold monitoring modules as well as standardized hardware interfaces
Pre-built monitoring modules are dynamically deployed in monitoring capsule’s FPGA fabric
OwlOwl: System-wide Monitoring: System-wide Monitoring
CPU
L2 Cache
MemoryI/O
Bridge
L1 Cache
L2 Cache
L1 Cache
CPUM
MMM
M
M
M
M
M
M
M
M
M
Georgia Tech, Cornell, LLNL - WARFP 2005
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Cross CapsuleAnalysis
Example: Multi-level Memory MonitoringExample: Multi-level Memory Monitoring
Monitor
Main Memory
L1 Cache
CPU
L2 Cache
Monitor
Monitor
Georgia Tech, Cornell, LLNL - WARFP 2005
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Feasibility StudyFeasibility Study
0.00.20.40.60.81.01.21.41.61.8
gzip swim vpr gcc mesa art crafty ammp gap bzip2 Avg.
IR 0
IR 1/1
IR 1/8
IR 1/64
IPC perturbation according to different injection rates (IR) of all L1 traffic
Simplescalar-4.0 alpha with bus and SDRAM models
In this work, we conduct a feasibility study with a rapid prototyping environment using FPGA platform
Georgia Tech, Cornell, LLNL - WARFP 2005
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Microblaze-based Evaluation PlatformMicroblaze-based Evaluation Platform
D-Cache behavior monitoring
Serial JTAG Ethernet
Microblaze
DDR SDRAMcontroller
Ethernetcontroller
UART
Monitoring Capsulefor D-Cache
Virtex-II Pro
OPB
Xilinx ML310 board
Georgia Tech, Cornell, LLNL - WARFP 2005
6
PowerPC-based Evaluation PlatformPowerPC-based Evaluation Platform
D-Cache behavior monitoring
Serial JTAG Ethernet
PowerPC 405
DDR SDRAMcontroller
Ethernetcontroller
UART
Monitoring Capsule for D-Cache
Bridge
Virtex-II Pro
OPBPLB
Xilinx ML310 board
Georgia Tech, Cornell, LLNL - WARFP 2005
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Evaluation Hardware Design FlowEvaluation Hardware Design Flow
Base System Builder
Add CPU,DDR controller
Ethernet controller,UART,
Interrupt Controller
Debugging with
Xilinx EDK 6.3
Add Monitoring Capsule
Synthesize & Place & Route
Xilinx ISE 6.3
Deploy a Monitoring
Module
Georgia Tech, Cornell, LLNL - WARFP 2005
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Owl Evaluation StackOwl Evaluation Stack
uClinux running on Microblaze
SPEC2000
Measure system perturbation adopting monitoring modules with different injection rates, by comparing execution times of SPEC2000 with/without monitoring
Georgia Tech, Cornell, LLNL - WARFP 2005
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Owl Evaluation Challenges on FPGA platformOwl Evaluation Challenges on FPGA platform
Memory on board is too fast, compared to processors in FPGAs
DDR SDRAM: 100MHz
Microblaze: 100MHz
=> This can be solved by inserting wait cycles for memory transactions in monitoring capsule
Available processors (Microblaze, PowerPC405) in FPGAs are too simple to mimic the state-of-the-art superscalar processors
=> However, Owl concept covers any complexity system,
which includes a rapid prototyped simple system like
Microblaze-based platform
Georgia Tech, Cornell, LLNL - WARFP 2005
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That’s All Folks !That’s All Folks !
Questions & AnswersQuestions & Answers
