Xilinx UG079 Virtex-4 ML461 Memory Interfaces Development ... · R Virtex-4 ML461 Memory Interfaces Development Board User Guide UG079 (v1.1) September 5, 2007

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Virtex-4 ML461Memory InterfacesDevelopment BoardUser Guide

UG079 (v1.1) September 5, 2007

Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007

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Virtex-4 ML461 Development Board UG079 (v1.1) September 5, 2007

The following table shows the revision history for this document.

R

Date Version Revision

11/15/04 1.0 Initial Xilinx release.

http://www.xilinx.com

UG079 (v1.1) September 5, 2007 www.xilinx.com Virtex-4 ML461 Development Board User Guide

09/05/07 1.1 Chapter 1: Added XAPP721 to “Virtex-4 ML461 Memory Interfaces Development Board” section.

Chapter 3: Added tables on voltage margining: Table 3-12, Table 3-13, and Table 3-14. Updated “Hardware Overview.” Updated Table 3-2.

Chapter 4: Added “Power Measurements on the ML461” section. Updated link to Samsung documentation in Table 4-1 and Table 4-3.

Chapter 5: Updated Read Data (Q) values in Table 5-5.

Appendix A: Updated FPGA pinout tables.

General text edits.

Date Version Revision


Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007


Virtex-4 ML461 Development Board User Guide www.xilinx.com 5UG079 (v1.1) September 5, 2007

Chapter 1: IntroductionAbout the Virtex-4 ML461 Memory Interfaces Tool Kit. . . . . . . . . . . . . . . . . . . . . . . . 7Virtex-4 ML461 Memory Interfaces Development Board . . . . . . . . . . . . . . . . . . . . . . 8

Chapter 2: Getting StartedDocumentation and Reference Design CD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Initial Board Check Before Applying Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Applying Power to the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Chapter 3: Hardware DescriptionHardware Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Memory Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Direct Clocking Data Capture Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16DDR400 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17DDR2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20QDR II Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23RLDRAM II Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

External Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Liquid Crystal Display (LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Configuration INIT and DONE LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27User Pushbutton Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Program Switch (PROG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28RS-232 Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Z-DOK+ Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Test Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Power Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Board Design Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Chapter 4: Electrical RequirementsPower Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37FPGA Internal Power Budget . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Power Measurements on the ML461 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Chapter 5: Signal Integrity Recommendations and SimulationsTermination and Transmission Line Summaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49IBIS Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table of Contents


6 www.xilinx.com Virtex-4 ML461 Development Board User GuideUG079 (v1.1) September 5, 2007

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Chapter 6: ConfigurationConfiguration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53JTAG Chain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54JTAG Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Parallel Cable IV Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55System ACE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Appendix A: FPGA PinoutsFPGA #1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57FPGA #2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64FPGA #3 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70FPGA #4 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Appendix B: LCD InterfaceGeneral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Display Hardware Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Hardware Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Peripheral Device KS0713 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85Controller – Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87Controller – LCD Panel Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89Controller – Power Supply Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Operation Example of the 64128EFCBC-3LP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96Read/Write Characteristics (6800 Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

LCD Panel Used in Full Graphics Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100LCD Panel Used in Character Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Array Connector Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105UCF Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105



R

Chapter 1

Introduction

This chapter introduces the Virtex™-4 ML461 reference design. It contains the following sections:

• ”About the Virtex-4 ML461 Memory Interfaces Tool Kit”

• ”Virtex-4 ML461 Memory Interfaces Development Board”

About the Virtex-4 ML461 Memory Interfaces Tool KitThe Virtex-4 ML461 Memory Interfaces Tool Kit provides a complete development platform to interface with external memory devices for designing and verifying applications based on the Virtex-4 LX FPGA family. This kit allows designers to implement high-speed applications with extreme flexibility using IP cores and customized modules. The Virtex-4 LX FPGA, with its column-based architecture, makes it possible to develop highly flexible memory interface applications.

The Virtex-4 ML461 Memory Interfaces Tool Kit includes the following:

• Virtex-4 ML461 Memory Interfaces Development Board (XC4VLX25-FF668 FPGA)

• 5V/6.5 A DC power supply

• Country-specific power supply line cord

• RS-232 serial cable, DB9-F to DB9-F

• Documentation and reference design CD-ROM

Optional items that also support development efforts include:

• Xilinx ISE™ software

• JTAG cable

• Xilinx Parallel Cable IV

FCRAM-II memory is not supported any longer on the ML461 board.

For assistance with any of these items, contact your local Xilinx distributor or visit the Xilinx online store at www.xilinx.com.

The heart of the Virtex-4 ML461 Memory Interfaces Tool Kit is the Virtex-4 ML461 Development Board. This manual provides comprehensive information on Rev B1 and later revisions of this board.




Chapter 1: IntroductionR

Virtex-4 ML461 Memory Interfaces Development BoardA high-level functional block diagram of the Virtex-4 ML461 Memory Interfaces Development Board is shown in Figure 1-1.

The Virtex-4 ML461 Development Board includes the following major functional blocks:

• Four XC4VLX25-FF668 FPGAs (see DS112: Virtex-4 Family Overview)

• DDR1 DIMM memory: Two PC-3200 DIMM sockets for up to 64M x 144 bits (see XAPP709)

• DDR400 components: 16M x 28 bits at 200 MHz clock speed

• DDR2 DIMM memory: Two PC2-4300 DIMM sockets for up to 64M x 144 bits (see XAPP702 and XAPP721)

• DDR2-533 components: 8M x 28 bits at 267 MHz clock speed

• QDR II memory: 2M x 72 bits at up to 300 MHz clock speed (see XAPP703)

• RLDRAM II memory: 16M x 36 bits at up to 400 MHz clock speed (see XAPP710)

• One DB9-M RS232 port

• One 64 x 128 pixel Liquid Crystal Display (LCD)

• A System ACE™ CompactFlash (CF) Configuration Controller that allows storing and downloading of up to eight FPGA configuration image files

• On-board power regulators with ±5% output margin test capabilities

Figure 1-1: Virtex-4 ML461 Development Board Block Diagram

DD

R2

DIM

M14

4

DD

R2

SD

RA

Mx4

, x8,

x16

QD

R II

SR

AM

72 72

RLD

RA

M II

36

FC

RA

M II

36

DD

R1

DIM

M14

4

FPGA #1LX25/FF668

FPGA #2LX25/FF668

DD

R1

SD

RA

Mx4

, x8,

x16

SSTL2 SSTL18 HSTLHSTL/SSTL18

External Interfaces: System ACE Controller,ML410 Z-DOK+, LCD

UG079_c1_02_072905

FPGA #3LX25/FF668

FPGA #4LX25/FF668

http://www.xilinx.com/bvdocs/publications/ds112.pdf

http://www.xilinx.com/bvdocs/appnotes/xapp709.pdf







Virtex-4 ML461 Memory Interfaces Development BoardR

Figure 1-2 shows the Virtex-4 ML461 Development Board and indicates the locations of the resident memory devices.

Figure 1-2: Virtex-4 ML461 Development Board

Source: Arial Narrow, 10 pt., white w/ drop shadow, F/L

DDR2 DIMM

DDR DIMM

System ACECompactFlashController

FCRAM II

QDR IISDRAM

LCDDisplay

RLDRAM II

DDR2 SDRAM

DDR400 SDRAM

UG079_c1_02_102104



Chapter 1: IntroductionR



R

Chapter 2

Getting Started

This chapter describes the items needed to configure the Virtex-4 ML461 Memory Interfaces Development Board. The Virtex-4 ML461 Development Board is tested at the factory after assembly and should be received in working condition. It is set up to load a bitstream from the CompactFlash card at socket J6 through the System ACE controller (U36).

This chapter contains the following sections:

• “Documentation and Reference Design CD”

• “Initial Board Check Before Applying Power”

• “Applying Power to the Board”

Documentation and Reference Design CDThe CD included in the Virtex-4 ML461 Memory Interfaces Tool Kit contains the design files for the Virtex-4 ML461 Development Board, including schematics, board layout, and reference design files. Open the ReadMe.rtf file on the CD to review the list of contents.

Initial Board Check Before Applying PowerPerform these steps before applying board power:

1. Set up the Configuration Mode Switch SW1.

See “Configuration Modes” on page 53 for all available modes for the Virtex-4 ML461 Development Board.

2. Confirm that the JTAG chain jumpers P9, P10, P26, and P60 are connecting pins 1 to 2. This way, all four devices are in the chain. Otherwise, the ISE iMPACT software will not find all four devices to configure. For more information see “JTAG Chain” on page 54.

3. Make sure that no inhibit jumpers are present on any of the power supply regulator modules. For more information, see “Voltage Regulators” on page 30.

4. The Virtex-4 ML461 Development Board has a 200 MHz on-board oscillator, which provides a copy of a differential LVPECL clock to each of the four FPGAs through a differential clock buffer (ICS853006). There is also a connection to a pair of SMA connectors to provide a differential LVDS clock from an off-board signal generator. Another differential clock buffer (ICS853006) provides a copy of this clock to each FPGA. These clocks are available after configuration for the design to use for various system clocks.

5. Insert the CompactFlash card included in the kit into socket J6 on the ML461 Development Board. To select the startup file, check that SW6 is set to position 0.



Chapter 2: Getting StartedR

Applying Power to the BoardThe Virtex-4 ML461 Development Board is now ready to power on. The Virtex-4 ML461 Development Board is shipped with a country-specific AC line cord for the universal input 5V desktop power supply. Follow these steps to power on the Virtex-4 ML461 Development Board:

1. Confirm that the ON-OFF switch, SW4, is in the OFF position.

2. Plug the 5V desktop power supply into the 5V DC input barrel jack J9 on the Virtex-4 ML461 Development Board. Plug the desktop power supply AC line cord into an electrical outlet supplying the appropriate voltage.

3. Turn SW4 to the ON position. The power indicators for all regulator modules should come on, indicating output from the regulators. The System ACE status LED D9 comes on when the System ACE controller (U36) extracts the BIT configuration file from the CompactFlash card to the FPGA. If no CompactFlash card is installed in the card socket J6 on the Virtex-4 ML461 Development Board, the red System ACE error LED D11 flashes.

4. If a CompactFlash card is not installed in socket J6, a JTAG cable must be used to configure the FPGAs. To use a Parallel Cable IV or other JTAG pod, download the FPGA configuration bitstream into each FPGA. After the DONE LED (D1) comes on, the FPGAs are configured and ready to use.

5. Eject the CompactFlash card from J6 after configuration is done and push the reset button SW2.



R

Chapter 3

Hardware Description

This chapter describes the major hardware blocks on the Virtex-4 ML461 Development Board and provides useful design consideration. It contains the following sections:

• “Hardware Overview”

• “Memory Interfaces”

• “External Interfaces”

• “Board Design Considerations”

Hardware OverviewThe ML461 Development/Evaluation system reference design is implemented with four XC4VLX25-FF668 devices from the Virtex-4 FPGA device family to demonstrate high-speed external memory application interfaces. The memory technologies supported by the Virtex-4 ML461 Development Board are DDR1 (DIMM and discrete components), DDR2 (DIMM and discrete components), QDR II, and RLDRAM II.

Figure 3-1 is a high-level block diagram of the Virtex-4 ML461 Memory Interfaces Development Board.

Figure 3-1: Virtex-4 ML461 Memory Interfaces Development Board Block Diagram

3672

DD

R2

Com

pone

nts

28144

DD

R2

DIM

M

144

28

DD

R1

DIM

M

DD

R1

Com

pone

nts

QD

R II

72 36F

CR

AM

II

RLD

RA

M II

FPGA #4FPGA #3FPGA #2FPGA #1

Parallel IV Port

External Interface,

System ACEController

MII Links Between FPGA #4 and Three Other FPGAs

Power Supply+ Clocks

ML410 Z-DOK+ Interface

LCD DisplaySSTL2 SSTL18 HSTL/SSTL18 HSTL

UG079_c3_01_072905



Chapter 3: Hardware DescriptionR

Memory InterfacesTable 3-1 summarizes the implementation of the Virtex-4 ML461 Development Board for various memory types. The maximum speed goal is based on using faster speed grade XC4VLX25-FF668-12 devices.

When a memory with a larger data/strobe ratio is implemented, for example, a x36 QDR II device, the smaller configurations can also be demonstrated by programming the FPGA for a smaller data width, such as a 9:1 data/strobe ratio for the QDR II device.

Figure 3-2 illustrates a detailed block diagram of the Virtex-4 ML461 Development Board showing connectivity between the memory types and the four XC4VLX25-FF668 FPGAs. The conventions for showing multiple loads on a net are as follows:

• stacks of devices are shown with overlapping blocks, such as two x4 devices for the DDR1 component interface

• multiple signals are on the same arrow, such as Address/Control signals to most of the memories

Table 3-1: Summary of ML461 Memory Interfaces

Memory TypeMaximum

SpeedData Rate Data Width I/O Standard

Data/Strobe Ratios

DDR2 DIMM 267 MHz 533 Mb/s 144 SSTL18 4:1, 8:1

DDR2 SDRAM 267 MHz 533 Mb/s 28 SSTL18 4:1, 8:1

DDR1 DIMM 200 MHz 400 Mb/s 144 SSTL2 4:1, 8:1

DDR1 SDRAM 200 MHz 400 Mb/s 28 SSTL2 4:1, 8:1

QDR II 300 MHz 1.2 Gb/s 72 HSTL 18:1, 36:1

RLDRAM II 300 MHz 600 Mb/s 36 HSTL Class II 9:1, 18:1



Memory InterfacesR

Figure 3-2: ML461-XC4VLX25-FF668 Board Connectivity Diagram

ADDR/CNTL

36-BitRLDRAM II

36-BitFCRAM II

72-BitQDR II

28-BitDDR2COMP

144-BitDDR2DIMM

144-BitDDR1DIMM

28-BitDDR1COMP

Virtex-4FPGA #1

(XC4VLX25-FF668)448 I/Os

External Interfaces

8

16

4

8

16

4

72

72

72

72

36

36

36

36

36

18

18

ADDR/CNTL

ADDR/CNTL

ADDR/CNTL

ADDR/CNTL

ADDR/CNTL

ADDR/CNTL

Virtex-4FPGA #2


Virtex-4FPGA #3


Virtex-4FPGA #4


UG079_c3_02_072905




Direct Clocking Data Capture MethodThe read data capture technique for all five memories (DDR1, DDR2, QDR II, and RLDRAM II) is labeled as Direct Clocking method. Refer to XAPP701: “Memory Interfaces Data Capture Using Direct Clocking Technique” for a detailed description. Figure 3-3 shows a basic block diagram for all external memory interfaces on the Virtex-4 ML461 Development Board.

The memory controller in the respective FPGA sits in between the physical layer to the external memory devices and the user interface. Refer to the respective application notes of reference designs for each memory interface to understand the details of the memory controller implementations.

Figure 3-3: Basic Memory Controller Block Diagram

UG079_c3_03_082807

External Memory Device

DCM

Datapath

Address and Controls

Data Bus

CLKs

Clock/Strobe

Rd/Wr Addr

Write Data

System Clock DCM Clocks

DCM Clocks

Ctrl

FPGA

Memory Clock

Memory Controller

State Machine

Memory Interfaces Board

Read Data

UserInterface

(Testbench)




Memory InterfacesR

DDR400 MemoryThe FPGA #1 device on the Virtex-4 ML461 Development Board is connected to DDR1 memories. The DDR1 memory interface includes:

• a 144-bit-wide DIMM connection to two 184-pin DDR1 DIMM sockets

• a 28-bit-wide datapath to four DDR400 memory discrete components

For the 144-bit-wide DIMM datapath, the data bytes are spread across multiple banks of the FPGA #1 device. Figure 3-4 summarizes the distribution of DDR1 DIMM and discrete component interface signals among the different banks of the FPGA #1 device.

Table 3-2 describes all the signals associated with DDR1 DIMM component memories. For a bus or a group of signals, a shorthand method is used to describe these signals and follows these rules:

1. All entities with a pair of square brackets represent a different signal.

For example, DDR1_[RAS,CAS,WE]_N represents three signals: DDR1_RAS_N, DDR1_CAS_N, and DDR1_WE_N.

2. All numbers are represented as a range, for example, n:m, expands into (n-m+1) unique signals.

For example, DDR1_A[12:0] represents 13 separate signals: DDR1_A12, DDR1_A11, …., DDR1_A0.

3. Other items are listed within brackets separated by commas.

Figure 3-4: FPGA #1 Banks for DDR1 (SSTL2) Interfaces (Top View)

BANK 8 (64)

DIMM Bytes:4, 5, 12, 13

BANK 10 (64)

DIMM Addr/Cntl

Component Bytes:3

BANK 9 (64)

DIMM Bytes:CB0_7, CB8_15

Component Bytes:1,2

BANK 6 (64)

DIMM Bytes:2, 3, 10, 11

Component Bytes:0

BANK 7 (64)

DIMM Bytes:6, 7, 14, 15

BANK 5 (64)

DIMM Bytes:0, 1, 8, 9

BANK 0

(Configuration)

BANK 4 (16)

Global Clock Inputs

BANK 2 (16)

Component Control/Clocks

BANK 3 (16)

Inter-FPGA SERDES Links

BANK 1 (16)

Component Address

Note: Banks 1 & 2 do not have DCI capability due to lack of VRP/VRN.

UG079_c3_04_072905




For example, DDR1_CK[3:0]_[P,N] represents 4 * 2 = 8 signals to fully expand two sets of brackets. That is, the eight signals are: DDR1_CK3_P, DDR1_CK3_N, DDR1_CK2_P, …., DDR1_CK0_N.

To use Registered DDR1 DIMMs with the ML461 memory board, it is necessary to connect Pin 10 of socket XP2 (reset#) and drive this signal with FPGA1.

Table 3-2: DDR1 DIMM Signal Summary

Board Signal Name(s) Bits Description Bank #Schematic

Page #

DDR1_DIMM_A[12:0] 13 DDR1 DIMM Address 10 10

DDR1_DIMM_CK[5:0]_[P,N] 12 DDR1 DIMM Differential Clock 10 10

DDR1_DIMM_[RAS,CAS,WE]_N, DDR1_DIMM_CKE, DDR1_DIMM_BA[1:0], DDR1_DIMM_CS[3:0]_N,

10 DDR1 DIMM Control Signals 10 10

DDR1_DIMM_DQ_BY[0,1,8,9]_B[7:0], DDR1_DIMM_DQS_BY[0,1,8,9]_L_P, DDR1_DIMM_DM_DQS_BY[0,1,8,9]_H_P

40 DDR1 DIMM Data and Strobes: Bytes 0, 1, 8, 9

6 8



8 11



5 7



6 8

DDR1_DIMM_DQ_CB0_7_B[7:0], DDR1_DIMM_DQS_CB0_7_L_P, DDR1_DIMM_DM_DQS_CB0_7_H_P

10 DDR1 DIMM Data and Strobes: Check Byte 0

9 9

DDR1_DIMM_DQ_CB8_15_B[7:0], DDR1_DIMM_DQS_CB8_15_L_P, DDR1_DIMM_DM_DQS_CB8_15_H_P


9 9

Notes: 1. DDR1_DIMM_CKE is connected to a 4.7K pull-down resistor.



Memory InterfacesR

Table 3-3 describes all signals associated with DDR400 Component memories.

A copy of XAPP709: "DDR SDRAM Controller Using Virtex-4 FPGA Devices" and its corresponding reference design RTL code are included on the CD shipped with the ML461 Tool Kit. For a complete list of FPGA #1 signals and their pin locations, refer to Appendix A, “FPGA Pinouts.”

Table 3-3: DDR400 Component Signal Summary

Board Signal Name(s) Bits DescriptionBank

#Schematic

Page #

DDR1_A[12:0] 13 DDR400 Component Address 1 4

DDR1_CK[3:0]_[P,N] 8 DDR400 Component Differential Clock 2 4

DDR1_[RAS,CAS,WE]_N, DDR1_CKE, DDR1_BA[1:0], DDR1_CS[3:0]_N, DDR1_DM_BY[3:0]

14 DDR400 Component Control Signals 2, 10 4, 10

DDR1_DQ_BY0_B[3:0], DDR1_DQS_BY0_L_P

5 DDR400 Data and Strobe: Byte 0 6 8

DDR1_DQ_BY1_B[7:0], DDR1_DQS_BY1_P






Notes: 1. DDR1_CKE is connected to a 4.7K pull-down resistor.





DDR2 MemoryThe FPGA #2 device on the Virtex-4 ML461 Development Board is connected to DDR2 memories. The DDR2 memory interface includes:

• a 144-bit-wide DIMM connection to two 240-pin DDR2 DIMM sockets

• a 28-bit-wide datapath to four DDR2 memory discrete components

For the 144-bit-wide DIMM datapath, the data bytes are spread across multiple banks of the FPGA #2 device. Figure 3-5 summarizes the distribution of DDR2 DIMM and discrete component interface signals among the different banks of the FPGA #2 device.

Table 3-4 describes all the signals associated with DDR2 DIMM component memories.

Figure 3-5: FPGA #2 Banks for DDR2 (SSTL18) Interfaces (Top View)

BANK 8 (64)

DIMM Bytes:4, 5, 12, 13

BANK 10 (64)

DIMM Address/Control

Component Bytes:3

BANK 9 (64)

DIMM Bytes:CB0_7, CB8_15

Component Bytes:1,2

BANK 6 (64)

DIMM Bytes:2, 3, 10, 11

Component Bytes:0

BANK 7 (64)

DIMM Bytes:6, 7, 14, 15

BANK 5 (64)

DIMM Bytes:0, 1, 8, 9

BANK 0

(Configuration)

BANK 4 (16)

Global Clock Inputs

BANK 2 (16)

Component Control/Clocks

BANK 3 (16)

Inter-FPGA SERDES Links

BANK 1 (16)

Component Address


UG079_c3_05_072905



Memory InterfacesR

Table 3-4: DDR2 DIMM Signal Summary


#Schematic

Page #

DDR2_DIMM_A[12:0] 13 DDR2 DIMM Address 10 34

DDR2_DIMM_CK[5:0]_[P,N] 12 DDR2 DIMM Differential Clock 10 34

DDR2_DIMM_[RAS,CAS,WE]_N, DDR2_DIMM_CKE, DDR2_DIMM_BA[1:0], DDR2_DIMM_CS[3:0]_N,

10 DDR2 DIMM Control Signals 10 34

DDR2_DIMM_BY0_7_ODT, DDR2_DIMM_BY8_15_ODT, DDR2_DIMM_DQ_BY[0,1,8,9]_B[7:0], DDR2_DIMM_DQS_BY[0,1,8,9]_L_[P,N], DDR2_DIMM_DM_DQS_BY[0,1,8,9]_H_[P,N]


5 31

DDR2_DIMM_DQ_BY[2,3,10,11]_B[7:0], DDR2_DIMM_DQS_BY[2,3,10,11]_L_[P,N], DDR2_DIMM_DM_DQS_BY[2,3,10,11]_H_[P,N]


6 32



8 35



7 36

DDR2_DIMM_DQ_CB0_7_B[7:0], DDR2_DIMM_DQS_CB0_7_L_[P,N], DDR2_DIMM_DM_DQS_CB0_7_H_[P,N]


9 33

DDR2_DIMM_DQ_CB8_15_B[7:0], DDR2_DIMM_DQS_CB8_15_L_[P,N], DDR2_DIMM_DM_DQS_CB8_15_H_[P,N]


9 33

Notes: 1. DDR2_DIMM_CKE, DDR2_DIMM_BY0_7_ODT, and DDR2_DIMM_BY8_18_ODT signals are connected to a 4.7K pull-down

resistor.




Table 3-5 describes all signals associated with DDR2 Component memories. For a complete list of FPGA #2 signals and their pin locations, refer to Appendix A, “FPGA Pinouts.”

A copy of XAPP702: "DDR-2 Controller Using Virtex-4 Devices" and its corresponding reference design RTL code are included on the CD shipped with the ML461 Tool Kit.

Table 3-5: DDR2 Component Signal Summary


#Schematic

Page #

DDR2_A[12:0] 13 DDR2 Component Address 1 28

DDR2_CK[3:0]_[P,N] 8 DDR2 Component Differential Clock 2 28

DDR2_ODT, DDR2_[RAS,CAS,WE]_N,DDR2_CKE, DDR2_BA[1:0], DDR2_CS[3:0]_N, DDR2_DM_BY[3:0]

14 DDR2 Component Control Signals 2, 10 28, 34

DDR2_DQ_BY0_B[3:0], DDR2_DQS_BY0_L_[P,N]


DDR2_DQ_BY1_B[7:0], DDR2_DQS_BY1_[P,N]






Notes: 1. DDR2_CKE and DDR2_ODT signals are connected to a 4.7K pull-down resistor.




Memory InterfacesR

QDR II MemoriesFigure 3-6 summarizes the distribution of QDR II component interface signals among the different banks of the FPGA #3 device.

Table 3-6 describes all the signals associated with QDR II component memories.

Figure 3-6: FPGA #3 Banks for QDR II (HSTL) and FCRAM II (SSTL18) Interfaces (Top View)

BANK 8 (64)

QDR II Bytes:4 through 7

BANK 10 (64)


BANK 9 (64)


BANK 6 (64)

FCRAM II Bytes:0, 1

BANK 7 (64)


BANK 5 (64)

FCRAM II Bytes:2, 3

BANK 0

(Configuration)

BANK 4 (16)

Global Clock Inputs

BANK 2 (16)

BANK 3 (16)

Inter-FPGA MII Links

BANK 1 (16)

Clock SynthesizerSerial Load Control




A copy of XAPP703: "QDR-2 SRAM Interface" and the corresponding reference design RTL code are included on the CD shipped with the ML461 Tool Kit.

Table 3-7 describes all signals associated with FCRAM-II Component memories.

For a complete list of FPGA #3 signals and their pin locations, refer to Appendix A, “FPGA Pinouts.”

Table 3-6: QDR II Component Signal Summary


Page #

QDR2_SA[17:0] 18 QDR II Address 8 59

QDR2_CK_BY0_3_[P,N], QDR2_CK_BY4_7_[P,N]

4 QDR II Differential Clock 8 59

QDR2_[R,W]_N 2 QDR II Control Signals 8 59

QDR2_D_BY[3:0]_B[8:0], QDR2_K_BY0_3_[P,N], QDR2_BW_BY[3:0]

42 QDR II Write Data, Strobes, and Byte Write: Bytes 3:0

7, 9 58

QDR2_Q_BY[3:0]_B[8:0], QDR2_CQ_BY0_3_[P,N]

38 QDR II Read Data and Strobes: Bytes 3:0 7, 9 58

QDR2_D_BY[7:4]_B[8:0], QDR2_K_BY4_7_[P,N], QDR2_BW_BY[3:0]

42 QDR II Write Data, Strobes, and Byte Write: Bytes 7:4

8, 10 59

QDR2_Q_BY[7:4]_B[8:0], QDR2_CQ_BY4_7_[P,N]

38 QDR II Read Data and Strobes: Bytes 7:4 8, 10 59

Table 3-7: FCRAM II Component Signal Summary


Page #

FCR2_A[13:0] 14 FCRAM II Address 5 54

FCR2_CK[1:0] _[P,N] 4 FCRAM II Differential Clock 5 54

FCR2_CS[1:0]_N, FCR2_FN, FCR2_PD_N

4 FCRAM II Control Signals 5 54

FCR2_DQ_BY[1:0]_B[8:0], FCR2_DS_BY0_1, FCR2_QS_BY0_1

20 FCRAM II Data and Strobes: Bytes 1:0 6 55

FCR2_DQ_BY[3:2]_B[8:0], FCR2_DS_BY2_3, FCR2_QS_BY2_3

20 FCRAM II Data and Strobes: Bytes 3:2 5 54




Memory InterfacesR

RLDRAM II MemoryFigure 3-7 summarizes the distribution of RLDRAM II component interface signals among the different banks of the FPGA #4 device. FPGA #4 also implements some of the auxiliary functions, such as connections to the LCD display and Z-DOK+ connector interface.

Figure 3-7: FPGA #4 Banks for RLDRAM II (HSTL) Interfaces (Top View)

BANK 8 (64)

Z-DOK+ Interface

BANK 10 (64)

Z-DOK+ Interface

BANK 9 (64)

Z-DOK+ Interface

BANK 6 (64)

RLDRAM Bytes:0, 1

BANK 7 (64)

System ACE ControllerLCD Display

BANK 5 (64)

RLDRAM Bytes:2, 3

BANK 0

(Configuration)

BANK 4 (16)

Global Clock Inputs

BANK 2 (16)


BANK 3 (16)


BANK 1 (16)



UG079_c3_07_072905




Table 3-8 describes all signals associated with RLDRAM II memories.

A copy of XAPP710: "RLDRAM II Controller Using Virtex-4 Devices" and the corresponding reference design RTL code are included on the CD shipped with the ML461 Tool Kit. For a complete list of FPGA #4 signals and their pin locations, refer to Appendix A, “FPGA Pinouts.”

Table 3-8: RLDRAM II Component Signal Summary


#Schematic

Page #

RLD2_A[19:0], RLD2_BA[2:0] 23 RLDRAM II Address 5 72

RLD2_CK0_1 _[P,N] 2 RLDRAM II Differential Clock 6 71

RLD2_CK2_3 _[P,N] 2 RLDRAM II Differential Clock 5 72

RLD2_CS_BY[0_1,2_3]_N, RLD2_[REF,WE]_N, RLD2_DM_BY[0_1,2_3]_N, RLD2_QVLD_BY[0_1]

7 RLDRAM II Control Signals 6 71

RLD2_QVLD_BY[2_3] 1 RLDRAM II Control Signals 5 72

RLD2_DQ_BY[1:0]_B[8:0], RLD2_DK_BY0_1_[P,N], RLD2_QK_BY[1:0]_[P,N]

24 RLDRAM II Data and Strobes: Bytes 1:0 6 71

RLD2_DQ_BY[3:2]_B[8:0], RLD2_DK_BY0_1_[P,N], RLD2_QK_BY[3:2]_[P,N]

24 RLDRAM II Data and Strobes: Bytes 3:2 5 72




External InterfacesR

External InterfacesThe external interfaces of the Virtex-4 ML461 Development Board are described in this section.

Clock GenerationThe clock generation section of the ML461 Development Board provides all necessary clocks for the four Virtex-4 FPGAs. Three clock sources are provided to each FPGA as follows:

• A 200 MHz differential LVPECL oscillator (Epson EG2121CA 2.5V at Y3)

This oscillator is required for the IDELAY tap controller for Virtex-4 devices. A differential clock buffer (ICS853006 from ICS Technology) is used on the board (U13) to generate four LVPECL copies of the differential clock signal, one for each FPGA. (DIRECT_CLK_TO_FPGAx_[P,N])

• An external signal generator SMA connector (J2, J3) interface

An LVDS differential clock can be provided to the board via a pair of SMA connectors. Another differential clock buffer (ICS853006) is used on the board (U12) to generate four LVPECL copies of the differential clock signal, one for each FPGA (EXT_CLK_TO_FPGAx_[P,N]).

• A high-frequency synthesized clock interface

A 33 MHz oscillator (EPSON SG-8002CA) on the board (Y1) provides a single-ended, low-frequency clock. Four copies of this clock are generated using a clock buffer (ICS8304) on the board (U8). Each of these copies is an input to a dedicated clock synthesizer (ICS8430), one per FPGA (SYNTH_CLK_TO_FPGAx_[P,N]).

Liquid Crystal Display (LCD)The Virtex-4 ML461 Development Board provides an 8-bit interface to a 64 x 128 LCD panel (DisplayTechQ 64128E-FC-BC-3LP, 64 x 128). The LCD is attached to the board via the receptacle connector P55 and four stand-offs. This display was chosen because of its possible use in embedded systems. Refer to the product specification at http://www.displaytech.com.hk/pdf/graphic/64128e%20series-v10.PDF for more information. Appendix B, “LCD Interface,” describes the LCD operation in detail.

Configuration INIT and DONE LEDsThe Virtex-4 ML461 Development Board provides an INIT LED and a DONE LED, which can be turned ON by driving the LEDs signal Low. Table 3-9 describes these LEDs and their associated pin assignments for the FF668 FPGA used on the Virtex-4 ML461 Development Board.

Table 3-9: Configuration INIT and DONE LED Pin Assignments

LED DesignationFPGA Pin Number(FF668 Package)

FPGA_INIT INIT (D19) G15

FPGA_DONE DONE (D20) H14


http://www.icst.com/

http://www.displaytech.com.hk/pdf/graphic/64128e%20series-v10.PDF



User Pushbutton SwitchThe Virtex-4 ML461 Development Board provides one user pushbutton switch that generates an active-Low signal when the switch is pressed (see Table 3-10). There is a pull-up resistor on the pushbutton switch signal on the Virtex-4 ML461 Development Board. The internal FPGA pull-up resistor does not need to be used to force the pushbutton switch signal High when its associated switch is not pressed. Switch contact debounce logic must be implemented inside the FPGA.

Program Switch (PROG)The Virtex-4 ML461 Development Board provides a pushbutton program switch (SW5) for initiating the configuration of the Virtex-4 FPGAs. This switch is used to force a reconfiguration of the FPGAs from PROMs, if they are present and enabled. The Virtex-4 ML461 Development Board does not include PROMs.

The primary configuration device is the System ACE Controller (U26), which loads image files from a CompactFlash card. The mode switch (SW1) must be set to the proper mode for configuration to occur via the System ACE interface (refer to “Configuration Modes” on page 53 for further information regarding setting mode jumpers). The PROG pushbutton simply clears the FPGA configuration on this board.

RS-232 PortThe Virtex-4 ML461 Development Board provides a DB9-M connection for a simple RS-232 port. The board uses the Maxim MAX3316 device to drive the RD, TD, RTS, and CTS signals. The user must provide a UART core internal to the FPGA to enable serial communication.

Table 3-11 describes the RS-232 interface signal names and their respective Virtex-4 FPGA pin assignments..

Table 3-10: User Pushbutton Switch Assignment

Signal Switch Designation DescriptionFPGA Pin Number(FF668 Package)

FPGA_RESETB SW2 RESET FPGA #1, FPGA #2: K1

FPGA #3: K3

FPGA #4: N3

Table 3-11: RS-232 Interface Signal Names and Pin Assignments

SignalName

DescriptionDB9-M

Pin NumberDirection

FPGA Pin Number(FF668 Package)

RX Receive Data (RD) 2 Input AC20

TX Transmit Data (TD) 3 Output AB20

RTS Request to Send (RTS)

7 Output AD17

CTS Clear to Send (CTS) 8 Input AD16



External InterfacesR

A high-level block diagram of the RS-232 interface is shown in Figure 3-8.

The RS-232 DB9-F to DB9-F cable included in the kit mates with the P30 connector.

Z-DOK+ PortFor an external processor interface, a pair of Z-DOK+ connectors (Tyco 137555-1) are provided (at locations PM1 and PM2). Through these connectors, the Virtex-4 ML461 Development Board can plug into an MLx10-series motherboard developed by the Xilinx APD Systems Engineering Group (SEG).

Test HeadersAll four FPGAs have two 16-pin (2X8, 100-mil spacing) headers each, connected to test header signals on Banks 3 and 4, that is, a total of eight connectors (P1, P2, P3, P4, P21, P27, P54, and P57).

1. Bank 3 Headers: The 16-pin header connected to Bank 3 signals is exclusively dedicated for the test signals. Based on the number of spare signals available on Bank 3, up to eight test signals are accessible at this connector. FPGA #1, FPGA #3, and FPGA #4 have eight test signals (FPGAx_TEST_HDR_BY0_B[7:0]) on connectors P2, P3, and P4, respectively. FPGA #2 has only three test signals (FPGA2_TEST_HDR_BY0_B[2:0]) accessible via connector P1.

2. Bank 4 Headers: The 16 test signals connected to Bank 4 on each FPGA serve dual purposes:

♦ To provide connectivity between FPGA #4 and the other three FPGAs via unidirectional 8-bit MII buses (Tx and Rx). The eight bits are Data[0:3], Clock, Enable, Error, and Spare. The Rev B1 board does not implement this connectivity. It can be implemented by populating the corresponding 0Ω resistors. See pages 6, 30, 53, and 70 of ML461 Rev B1 schematics for details.

To provide 16 additional test header signals to access the FPGA ports. The current implementation of the Rev B1 board provides access to these 16 test headers signals (FPGAx_TEST_HDR_BY[3:2]_B[7:0]) through connectors P27, P21, P54, and P57 for FPGA #1, #2, #3, and #4, respectively.

Figure 3-8: RS-232 Interface Block Diagram

TX

RX

RTS

CTS

T1IN

R1OUT

T2IN

R2OUT

3

2

7

8

T1OUT

R1IN

T2OUT

R2IN

DB9-M

P30U25U33

MAX3316

Virtex-4FPGA

#4

ug079_08_072905




CharacterizationThe memory interfaces implemented on the ML461 board have been characterized across voltage and temperature using various Virtex-4 devices. This section describes the setup for performing such characterization on the ML461 board. For actual characterization data obtained with the reference designs implemented on the ML461, please refer to www.xilinx.com/memory.

Voltage Regulators

Twelve power planes are used on the ML461 Development Board to provide various on-board voltage sources. • Connector J9 or a pair of banana jacks (J7 and J8) provides the main +5.0V voltage to

the board.

• This +5.0V voltage source is supplied as input to six on-board regulator modules (TI PTH05010-WAS) to generate the +1.2V, +2.5V, +1.8V for SSTL18, +1.8V for HSTL18, +2.6V for SSTL2, and +3.3V voltages for the digital section of the board. The HSTL18 power plane can be changed to HSTL power plane for supplying +1.5V by adjusting the VO_ADJ input of VR3 power regulator module. The value of R1565 then must be changed from 5.49 KΩ to 8.87 KΩ .

• Additional three bulk voltage regulators (Fairchild ML6554CU) are used to generate termination (VTT) and reference (VREF) voltages each for the SSTL2, SSTL18, and HSTL power levels. By design, these voltage levels are half of the input reference voltage from the corresponding VDD planes.

The TI PTH05010-WAS power module provides two input pins to control the voltage output level. The output can be margined up to +5% of the nominal value by driving pin 10 to GND or digital Low. Similarly, the output can be margined down to -5% of the nominal value by driving pin 9 Low. There are two ways to apply these digital controls to these voltage margin input pins:

1. The FPGA drives the VMARGIN_DN_xxxx_N and VMARGIN_UP_xxxx_N signals, where xxxx indicates one of the six power planes: SSTL2, HSTL, SSTL18, VCC1V2, VCC2V5, and 3V3.

To control the voltage levels using FPGA #4, make sure there are no jumpers connecting the header pins listed in Table 3-12. Table 3-12 illustrates the signals from FPGA #4 that are used to control the voltage margining for all the power regulators.

Table 3-12: FPGA #4 Signals for Voltage Margining

Power Plane Signal Name Pin

VCC1V2 VMARGIN_UP_VCC1V2_N N21

VMARGIN_DN_VCC1V2_N N20

SSTL18 VMARGIN_UP_SSTL18_N P25

VMARGIN_DN_SSTL18_N P24

SSTL2 VMARGIN_UP_SSTL2_N P23

VMARGIN_DN_SSTL2_N P22

HSTL VMARGIN_UP_HSTL_N R26

VMARGIN_DN_HSTL_N R25


http://focus.ti.com/lit/ds/symlink/pth05010w.pdf

http://focus.ti.com/lit/ds/symlink/pth05010w.pdf

http://www.fairchildsemi.com/ds/ML/ML6554.pdf


CharacterizationR

Another module I/O allows the output voltages of two related power planes to track. Tying pin 8 (TRACK) of two or more power modules together guarantees that these voltages will come up together at power-up. (This feature has not been tested on the Virtex-4 ML461 Development Board, although there is a provision to do so by populating some 0Ω resistors.)

The module output also can be enabled or inhibited through the use of on-board two-pin jumpers (P18, P20, P34, P36, P52, P63). The inhibit jumpers use the following conventions:

• Jumper OFF = Enabled

• Jumper ON = Inhibited

VCC2V5 VMARGIN_UP_VCC2V5_N P20

VMARGIN_DN_VCC2V5_N P19

VCC3V3 VMARGIN_UP_VCC3V3_N T23

VMARGIN_DN_VCC3V3_N R20

Notes: 1. The schematics on the CD have a typographical error in signal naming. The VMARGIN_UP_xxxx_N

signals are connected to the DN_N input (pin 9) on the PTH05010 modules and vice versa for the UP_N input (pin 10). When this control function is implemented, the code within FPGA #4 accounts for swapping the functionality of these pins.

Table 3-13: Voltage Margining

VMARGIN_UP VMARGIN_DN Output Voltage

Open Open Nominal

Open Low -5%

Low Open +5%

Low Low Undefined

Note:1. If both of the voltage-margining inputs to the power regulator are pulled Low, the output voltage will

be close to nominal but results in the possibility of a slightly higher error in the output voltage. The power modules use a low-leakage “open-drain” control signal to control the voltage margining. In the FPGA, this can be approximated by using a control signal that drives the output low when active and does not drive the signal at all when inactive (high impedance output).

2. To control the voltage levels using FPGA #4, make sure there are no jumpers connecting the header pins listed in Table (table added for headers below).

3. Three-pin jumpers on the board connect to these module input pins: P11, P12, P28, P29, P39.

Table 3-14: Header Connections and Voltage

Connection on Headers Voltage

None Nominal

2 – 3 -5%

1 – 2 +5%

Table 3-12: FPGA #4 Signals for Voltage Margining (Continued)

Power Plane Signal Name Pin




Figure 3-9 shows a typical schematic for voltage regulator control.

The TI PTH05010 regulator module requires a fixed 5V input. The output is adjustable over a range of 0.9V to 3.6V by changing the resistor tied between pin 4 and GND.

Power ConnectorsThe Virtex-4 ML461 Development Board is powered through the +5V input power jack (J9) from the power supply included in the ML461 Tool Kit. Alternatively, the +5V can also be supplied from a bench power supply using the two banana jacks: J8 (RED) for +5V and J7 (BLACK) for GND.

The Rev B1 assembly of the Virtex-4 ML461 Development Board does not support the +12V input via jack J5 or via banana jacks J4 and J1 because the power module for the 12V – 5V functionality is not populated.

Figure 3-9: Typical Voltage Regulator Configuration

PTH05010Voltage Regulator

VIN

GND TRACKMRGNUP MRGNDN GND

CIN RSET470μF

COUT

330μF(optional)

VOUT5V

++

1

2

3 54

6

7

8910

InhibitJumper

INHIBIT VO_ADJ VO_SENSE

VMARGIN_UP_xxxx_N

VMARGIN_DN_xxxx_N

TRACK

ug079_09_072905



Board Design ConsiderationsR

Board Design ConsiderationsThe Virtex-4 ML461 Development Board design allows for DCI termination to each of the memory interfaces on the board. A preliminary analysis of the Weighted Average Simultaneously Switching Outputs (WASSO) for all four Virtex-4 FPGA devices indicates that the SSO guidelines are met for the current pinout. Occasionally, for banks with more outputs than supported by WASSO analysis, additional pins are used to provide complimentary outputs to compensate for the switching guidelines. As a back-up plan, to protect against any power-related issues due to exclusive use of DCI termination, external terminations at both the memory and FPGA are also provided for all data signals for all memory interfaces on the current version of the Virtex-4 ML461 Development Board. There are two choices of terminations for the memory interfaces:

1. A split termination with a pair of 100Ω resistors between VDD and GND.

2. A VTT termination with a single 50Ω termination to the VREF level.

Simulation results show no performance difference between these two schemes, and the power usage for the split termination scheme is much higher than the VTT termination. Thus, the termination of choice for Data and Strobe signals throughout the Virtex-4 ML461 Development Board is the VTT termination. Address and Control signals also have VTT termination. See Chapter 5, “Signal Integrity Recommendations and Simulations,” for specific recommendations and guidelines for terminations.

For a fully configured DCI implementation, these external terminations can be depopulated. These are VTT terminations to the respective voltage levels for SSTL2, SSTL18, and HSTL signals.

The current implementation of the direct clocking method for data capture delays all data bits associated with a given strobe signal by the same number of taps using the IDELAY controller. This imposes a requirement on the board layout such that the trace delay for a strobe and the corresponding data bits are matched up to the pad of the die of the Virtex-4 device. So the sum of board trace delay and pad-to-pin flight delay are matched for each group of such data/strobe signals.

The physical dimensions of the raw PCB board is 12 inches x 12 inches. With the overhangs due to edge connectors, the actual size of the fully assembled board is approximately 12.5 inches x 13 inches, with 1.5 inches height allowance for the DIMM modules. This is an 18-layer board with eight signal layers and 10 power planes and uses NELCO 4013 material. Figure 3-10 shows a stack-up diagram of the ML461 Revision B PCB.

Refer to UG072: Virtex-4 PCB Designer’s Guide for more information on the Printed Circuit Board design using Virtex-4 devices.


http://www.xilinx.com/bvdocs/userguides/ug072.pdf



Table 3-15 shows the details of the dielectric material and construction for each layer and the controlled impedance values for the signal layers.

Figure 3-10: ML461 Revision B PCB Stack-up

TOP

GND1

PWR1

InnerSignal1

GND1a

InnerSignal2

GND2

PWR2

InnerSignal3

InnerSignal4

GND4

PWR3

InnerSignal5

GND5a

InnerSignal6

GND5

PWR4

BOTTOM

1.3 mils1.338 mils

4 mils1.338 mils

4 mils1.338 mils

5 mils0.669 mils

5 mils1.338 mils

5 mils0.669 mils

5 mils1.338 mils

4 mils1.338 mils

4 mils0.669 mils

4 mils0.669 mils

4 mils1.338 mils

4 mils1.338 mils

5 mils0.669 mils

5 mils1.338 mils

5 mils0.669 mils

5 mils1.338 mils

4 mils1.338 mils

4 mils1.338 mils

1.3 mils

Total Thickness = 98.67 mils UG079_c3_10_072905



Board Design ConsiderationsR

Table 3-15: ML461 Revision B PCB Controlled Impedance

Layer Name Type UsageThickness

(mils)Er

Test Width (mils)

Z0Ω

1 Dielectric Solder Mask 1.3 3.3

2 TOP Metal Signal 1.338 <Auto> 5 54.3

3 Dielectric Substrate 4 4.3

4 GND1 Metal Solid Plane 1.338 <Auto>


6 PWR1 Metal Solid Plane 1.338 <Auto>


8 InnerSignal1 Metal Signal 0.669 <Auto> 4 51.3


10 GND1a Metal Solid Plane 1.338 <Auto>


















28 GND5a Metal Solid Plane 1.338 <Auto>











36 Bottom Metal Signal 1.338 <Auto> 5 54.3

37 Dielectric Solder Mask 1.3 3.3

Table 3-15: ML461 Revision B PCB Controlled Impedance (Continued)

Layer Name Type UsageThickness

(mils)Er

Test Width (mils)

Z0Ω



R

Chapter 4

Electrical Requirements

This chapter provides the electrical requirements for the Virtex-4 ML461 Development Board. It contains the following sections:

• “Power Consumption”

• “FPGA Internal Power Budget”

• “Power Measurements on the ML461”

Power ConsumptionTable 4-1 lists the operating voltages, maximum currents, and power consumption used by the ML461 board devices. The Virtex-4 ML461 Development Board has provisions for two power inputs: a 5V power supply and a 12V power supply. The maximum rating of a commercially available 5V power supply is limited to 8A, or a 40W maximum capacity. This power supply is similar to the 5V brick used for previous memory tool kits, for example, ML361 and ML365. This tool kit expects the Virtex-4 ML461 Development Board to exercise only one external memory interface at a time. In this case, the total power consumption of the board stays within the 40W limit.

As shown in Table 4-1, if all four FPGA devices and their associated memory devices are activated simultaneously, then the total power consumption is 57W, which exceeds the 40W capacity of the 5V power brick. So an alternate 12V power input jack (J5) is provided on the Virtex-4 ML461 Development Board to hook up a 12V power brick, for example, CUI DTS120500U with a 60W capacity. The 12V is converted to 5V using TI's PTH12010WAS power module (VR6), which can supply up to 12A of current at 5V, or a 60W capacity.



Chapter 4: Electrical RequirementsR

Table 4-1: ML461 Power Consumption

Device Description QuantityVoltage

(V)Current

(mA)Power

(W)Source

Total Available Power

5V Power Supply 1 5.0 8000 40.0 Bellus Power SPD-050-5

12V Power Supply 1 12.0 5000 60.0 CUI DTS120500U

Power Consumed

DDR1 Memory Interface

XC4VLX25-FF668: FPGA #1 (DDR1)

1 1.2, 2.5, 2.6 3197 5.6 Virtex-4 Power Estimator

DDR1 DIMM Memory 2 2.6 1800 9.4 Micron DDR1 DIMM Data Sheet

DDR1 DIMM VTT Termination 160 0.7 16 1.8

DDR1 x16 Memory 1 2.6 260 0.7 Micron DDR1 Component Data Sheet

DDR1 x4 Memory 2 2.6 145 0.8

DDR1 x8 Memory 1 2.6 145 0.4

DDR2 Memory Interface

XC4VLX25-FF668: FPGA #2 (DDR2)

1 1.2, 1.8[S], 2.5

4973 7.5 Virtex-4 Power Estimator



DDR2 x16 Memory 1 1.8 180 0.3 Micron DDR2 Component Data SheetDDR2 x4 Memory 2 1.8 160 0.6

DDR2 x8 Memory 1 1.8 160 0.3

QDR II and FCRAM II Memory Interfaces

XC4VLX25-FF668: FPGA #3 (QDR II and FCRAM II)

1 1.2, 1.8[H], 1.8[S], 2.5


QDR II Memory [H] 2 1.8 640 2.3 Samsung QDR-II Datasheet

QDR II VTT Termination 175 0.6 16 1.7

FCRAM II Memory [S] 2 1.8 380 1.4 Toshiba FCRAM-II Data Sheet

FCRAM II VTT Termination 50 0.7 16 0.6

RLDRAM II Memory Interface

XC4VLX25-FF668: FPGA #4 (RLDRAM II)

1 1.2, 1.8[H], 2.5


http://www.belluspower.com/PDF/spd-050.pdf

http://www.cui.com/pdffiles/DTS120500UC-P5-ETa.pdf

http://www.xilinx.com/cgi-bin/power_tool/power_Virtex4

http://download.micron.com/pdf/datasheets/modules/ddr/DD18C32_64_128_256x72AG.pdf

http://download.micron.com/pdf/datasheets/dram/ddr/512MBDDRx4x8x16.pdf


http://download.micron.com/pdf/datasheets/modules/ddr2/HTF18C64_128_256x72DG.pdf

http://download.micron.com/pdf/datasheets/dram/ddr2/256MbDDR2.pdf


http://www.samsung.com/global/business/semiconductor/productInfo.do?fmly_id=176&partnum=K7R163684B&&ppmi=1295

http://www.toshiba.com/taec/components/Datasheet/59LM836DKB_040827.pdf





Power ConsumptionR

RLDRAM II Memory 2 1.8 990 3.6 Micron RLDRAM-II Data Sheet

RLDRAM II VTT Termination 60 0.6 16 0.6

Miscellaneous Circuit

Clock Buffer 1 3.3 23 0.1 ICS 8304 Data Sheet

Differential Clock Buffer 2 3.3 115 0.8 ICS 853006 Data Sheet

Clock Synthesizer 4 3.3 150 2.0 ICS 8430 Data Sheet

System ACE Controller 1 3.3 200 0.7 Xilinx Data Sheet DS080

200 MHz Oscillator 1 3.3 30 0.1 Epson EG2121CA Data Sheet

33 MHz Oscillator 2 3.3 45 0.3 Epson SG-8002CA Data Sheet

Total Power Consumed 57.0

Power Modules Capacity

VCCINT Power Plane (1.2V) 1 1.2 15000 18.0 TI PTH05010 15A Module Data Sheet

HSTL Power Plane (1.8V) 1 1.8 15000 27.0

HSTL _VREF Power Plane (0.9V) 1 0.9 3000 2.7 Fairchild ML6554CU Data Sheet

SSTL18 Power Plane (1.8V) 1 1.8 15000 27.0 TI PTH05010 15A Module Data Sheet

SSTL18 _VREF Power Plane (0.9V) 1 0.9 3000 2.7 Fairchild ML6554CU Data Sheet

SSTL2 Power Plane (2.6V) 1 2.6 15000 39.0 TI PTH05010 15A Module Data Sheet

SSTL2 _VREF Power Plane (1.3V) 1 1.3 3000 3.9 Fairchild ML6554CU Data Sheet

2.5V Power Plane 1 2.5 15000 37.5 TI PTH05010 15A Module Data Sheet

3.3V Power Plane 1 3.3 15000 49.5

12V-to-5V Converter 1 5.0 12000 60.0 TI PTH12010 12A Module Data Sheet

Notes: 1. [S] = 1.8V power for SSTL18 plane.2. [H] = 1.8V power for HSTL18 plane.

Table 4-1: ML461 Power Consumption (Continued)


(V)Current

(mA)Power

(W)Source

http://download.micron.com/pdf/datasheets/rldram/MT49H8M36.pdf

http://www.icst.com/products/pdf/ics8304.pdf


http://www.icst.com/products/pdf/ics8430-61.pdf


http://www.eea.epson.com/go/Resources/TestC2/go/Resources/TestC2/EG2121CASERIES

http://www.eea.epson.com/go/Prod_Admin/Categories/EEA/QD/Crystal_Oscillators/all_oscillators/go/Resources/TestC2/SG8002CA

http://www-s.ti.com/sc/ds/pth05010w.pdf











Table 4-2 lists the 12 different power planes on the Virtex-4 ML461 Development Board.

Each of the three Fairchild ML6554 Bus Terminator Regulators has two voltage outputs: one each for VREF and VTT. The ML6554 regulator is a push-pull device rated at ± 3A for the VTT output and 3 mA for the VREF output.

Because the VREF voltage is used by the FPGA and memory devices only as reference, the power supply does not source any real current. Thus the 3 mA capacity for the VREF output is considered sufficient.

The VTT voltage is guaranteed to within ± 20 mV of the VREF output by the ML6554 regulator. The minimum driver output voltage swing around VREF is specified for the SSTL18, SSTL2, and HSTL I/O standards as:

• SSTL2: ± 608 mV

• SSTL18: ± 603 mV

• HSTL: ± 500 mV (for HSTL18)

For a given memory interface, the maximum number of single-ended (non-differential) signals that might need to be pulled up or down at a time for QDR II is 144 data bits and approximately 30 address and control signals. The differential pair signals offset for the sink and source of current. With a continuous current capacity of 3A for the ML6554 regulator, the regulator can supply up to (3000 / 175) = 17 mA of current per signal. The maximum drive strength for a driver is specified at 16 mA. For a 50Ω VTT termination, this current can support a voltage swing of up to (16 mA * 50Ω) = 800 mV, which is sufficient to meet the output voltage specifications for SSTL18, SSTL2, and HSTL18 I/O standards.

Table 4-3 separates the power consumption information from Table 4-1 according to the six TI power modules for the first set of six power planes and the three Fairchild regulators for the VTT power planes. The positive values in the Excess Power column of Table 4-3 show that each of the nine modules can supply the necessary power for the corresponding power plane.

Table 4-2: Power Planes

Power Power Source

+1.2V

Texas Instruments PTH05010WAS Modules

+1.8V for SSTL18

+1.8V for HSTL18

+2.5V

+2.6V

+3.3V

+0.9V for SSTL18 VREF

Three Fairchild ML6554 Bus Terminator Regulators

+0.9V for SSTL18 VTT

+0.9V for HSTL18 VREF

+0.9V for HSTL18 VTT

+1.3V for SSTL2 VREF

+1.3V for SSTL2 VTT



Power ConsumptionR

Table 4-3: ML461 Power Plane Capacities


(V)Current

(mA)Power (Watts)

Excess Power (Watts)

Source

Total Available Power

5V Power Supply 1 5.0 8000 40.0 Bellus Power SPD-050-5

12V Power Supply 1 12.0 5000 60.0 CUI DTS120500U

Power Consumed by Power Plane

XC4VLX25-FF668: FPGA #1 (DDR1) 1 1.2 1906 2.3 Virtex-4 Power Estimator

XC4VLX25-FF668: FPGA #2 (DDR2) 1 1.2 2501 3.0


1 1.2 1348 1.6


1 1.2 2198 2.6

VCCINT Power Plane (1.2V) Capacity 1 1.2 15000 18.0 8.5 TI PTH05010 15A Module Datasheet


1 1.8 944 1.7 Virtex-4 Power Estimator


1 1.8 548 1.0

QDR II Memory [H] 2 1.8 640 2.3 Samsung QDR-II Data Sheet

RLDRAM II Memory 2 1.8 990 3.6 Micron RLDRAM-II Data Sheet

HSTL Power Plane (1.8V) Capacity 1 1.8 15000 27.0 18.4 TI PTH05010 15A Module Datasheet



1 1.8 449 0.8


DDR2 x16 Memory 1 1.8 180 0.3 Micron DDR2 Component Data SheetDDR2 x4 Memory 2 1.8 160 0.6

DDR2 x8 Memory 1 1.8 160 0.3

FCRAM II Memory [S] 2 1.8 380 1.4 Toshiba FCRAM-II Data Sheet


http://www.cui.com/pdffiles/DTS120500UC-P5-ETa.pdf




http://www.samsung.com/global/business/semiconductor/productInfo.do?fmly_id=176&partnum=K7R163684B&&ppmi=1295

http://download.micron.com/pdf/datasheets/rldram/MT49H8M36.pdf



http://download.micron.com/pdf/datasheets/modules/ddr2/HTF18C64_128_256x72DG.pdf

http://download.micron.com/pdf/datasheets/dram/ddr2/256MbDDR2.pdf

http://www.toshiba.com/taec/components/Datasheet/59LM836DKB_040827.pdf






SSTL18 Power Plane (1.8V) Capacity 1 1.8 15000 27.0 14.0 TI PTH05010 15A Module Datasheet


XC4VLX25-FF668: FPGA #2 (DDR2) 1 2.5 140 0.4


1 2.5 145 0.4


1 2.5 176 0.4

2.5V Power Plane Capacity 1 2.5 15000 37.5 35.9 TI PTH05010 15A Module Datasheet



DDR1 x16 Memory 1 2.6 260 0.7 Micron DDR1 Component DatasheetDDR1 x4 Memory 2 2.6 145 0.8

DDR1 x8 Memory 1 2.6 145 0.4

SSTL2 Power Plane (2.6V) Capacity 1 2.6 15000 39.0 25.0 TI PTH05010 15A Module Datasheet

Clock Buffer 1 3.3 23 0.1 ICS 8304 Data Sheet

Differential Clock Buffer 2 3.3 115 0.8 ICS 853006 Data Sheet

Clock Synthesizer 4 3.3 150 2.0 ICS 8430 Data Sheet

System ACE Controller 1 3.3 200 0.7 Xilinx Data Sheet DS080

200-MHz Oscillator 1 3.3 30 0.1 Epson EG2121CA Data Sheet

33-MHz Oscillator 2 3.3 45 0.3 Epson SG-8002CA Data Sheet

3.3V Power Plane Capacity 1 3.3 15000 49.5 45.6 TI PTH05010 15A Module Datasheet

QDR II VTT Termination 175 0.6 16 1.7

Table 4-3: ML461 Power Plane Capacities (Continued)


(V)Current

(mA)Power (Watts)


Source





http://download.micron.com/pdf/datasheets/modules/ddr/DD18C32_64_128_256x72AG.pdf

http://download.micron.com/pdf/datasheets/dram/ddr/512MBDDRx4x8x16.pdf



http://www.icst.com/products/pdf/ics8430-61.pdf


http://www.eea.epson.com/go/Resources/TestC2/go/Resources/TestC2/EG2121CASERIES

http://www.eea.epson.com/go/Prod_Admin/Categories/EEA/QD/Crystal_Oscillators/all_oscillators/go/Resources/TestC2/SG8002CA









Power ConsumptionR

RLDRAM II VTT Termination 60 0.6 16 0.6

HSTL _VREF Power Plane (0.9V) 1 0.9 3000 2.7 0.4 Fairchild ML6554CU Data Sheet


FCRAM II VTT Termination 50 0.7 16 0.6

SSTL18 _VREF Power Plane (0.9V) 1 0.9 3000 2.7 0.3 Fairchild ML6554CU Data Sheet


SSTL2 _VREF Power Plane (1.3V) 1 1.3 3000 3.9 2.1 Fairchild ML6554CU Data Sheet

Total Power Consumed 57.0

12V-to-5V Power Module Capacity 1 5.0 12000 60.0 3.0 TI PTH12010 12A Module Data Sheet

Notes: 1. [S] = 1.8V power for SSTL18 plane.2. [H] = 1.8V power for HSTL18 plane.

Table 4-3: ML461 Power Plane Capacities (Continued)


(V)Current

(mA)Power (Watts)


Source








FPGA Internal Power BudgetTable 4-4 summarizes power consumption estimates by each of the four XC4VLX25-FF668 FPGAs on the Virtex-4 ML461 Development Board. This estimate derives the FPGA utilization information from the respective map report of a fully configured reference design.

Power Measurements on the ML461This section describes the setup for measuring power on the Virtex-4 ML461 Development Board and lists the power measurements for different designs running on the board.

The ML461 board contains four FPGAs that all must be configured for any one design to run on the board. A blank design was created to program the other unused FPGAs on the board to be able to measure the power consumed by only one design at a time.

The ML461 board contains six power planes, each powered by a Texas Instrument PTH05010-WAS power regulator. These power modules have an inhibit feature that can be used to disable the corresponding power plane. Each power plane contains a header pin where the power can either be measured or supplied from an external source. By disabling a power regulator and using a bench supply as an input through this header pin, the

Table 4-4: ML461 FPGA Power Estimate Summary

Parameter FPGA #1 FPGA #2 FPGA #3 FPGA #4

Total Estimated Design Power (mW) 5513 7540 4488 4063

Estimated Design VCCINT 1.2V Power (mW) 2287 3001 1617 2637

Estimated Design VCCAUX 2.5V Power (mW) 281 293 299 420

Estimated Design VCCO 2.5V Power (mW) 145 57 64 19



Frequency (MHz) 200 267 300 300

Number of Slices 5910 5910 2200 3161

Number of Flip-Flops 7352 7352 2000 3600

Number of Shift Register LUTs 143 143 750 800

Number of Block RAM Blocks 17 17 14 21

Number of DCMs 1 1 1 3

Inputs 10 10 90 112

Outputs 75 75 185 142

Bidirectionals 160 192 36 36



Power Measurements on the ML461R

current can be measured for each of these power planes. The current measurement for each design running on the ML461 is shown in Table 4-5.

Before each measurement was taken, the design was verified to be running without error at the listed frequency using the ChipScope™ analyzer. The VTT and VREF power for SSTL18, SSTL2, and HSTL standards are derived from their corresponding VDD power so separate power usage for these power planes is not available.

The measured current usage is shown in Table 4-5.

After the current has been measured, the power is calculated by multiplying the current supplying the power plane by the voltage level of that power plane. The power consumption is shown in Table 4-6.

The measured power consumption is shown in Table 4-6.

Table 4-5: Measured Current Usage

Configuration ImageFrequency

(MHz)

Power Plane Current Usage (mA)

1.2V 2.5V 3.3VSSTL18

1.8VSSTL2 2.6V

HSTL 1.8V

Initial Power-Up n/a 0 2600 600 900 1000 100

All FPGAs with Blank Design n/a 400 700 600 900 1100 100

DDR1 Registered DIMM, 72-bit Design

200 900 1200 800 900 3100 100

DDR2 Registered DIMM, 144-bit Design

267 1700 1800 600 5000 1100 100

DDR2 Registered DIMM, 72-bit Design using SSTL18_II_DCI for DQ and ODT on DDR2 Memory

267 1100 1300 600 4600 1100 100

DDR2 Registered DIMM 144-bit Design using SSTL18_II_DCI for DQ

267 1700 1800 600 7300 1100 100

QDR2 72-bit Design 300 1100 1200 700 1700 1100 1000

RLDRAM II 36-bit Design 267 900 1100 600 1100 1100 700

Table 4-6: Measured Power Consumption

Configuration ImageFreq (MHz)

Power Consumption (Watts)

1.2V 2.5V 3.3VSSTL18

1.8VSSTL22.6V

HSTL1.8V

TOTAL Design

Initial Power-Up n/a 0.00 6.50 1.98 1.62 2.60 0.18 12.88 4.01

All FPGAs with Blank Design n/a 0.48 1.75 1.98 1.62 2.86 0.18 8.87

DDR1 Registered DIMM 72-bit Design

200 1.08 3.00 2.64 1.62 8.06 0.18 16.58 9.93


267 2.04 4.50 1.98 9.00 2.86 0.18 20.56 13.91




The ML461 Memory Board contains four Virtex-4 VC4VLX25 FF668 Engineering Sample (ES) parts. A known errata exists for these ES parts causing excessive VCCAUX power to be consumed at power-up. This is evident when comparing the power being consumed at power-up to the power being consumed where all the FPGAs are loaded with a blank design. To learn more about this errata, visit www.xilinx.com.

Table 4-7 and Table 4-8 show estimated values for current and power consumption not tested on the ML461. This data was extrapolated from the measured current data listed in Table 4-5.

DDR2 Registered DIMM 72-bit Design using SSTL18_II_DCI for DQ and ODT on DDR2 Memory

267 1.32 3.25 1.98 8.28 2.86 0.18 17.87 11.22

DDR2 Registered DIMM 144-bit Design using SSTL18_II_DCI for DQ

267 2.04 4.50 1.98 13.14 2.86 0.18 24.70 18.05

QDR2 72-bit Design 300 1.32 3.00 2.31 3.06 2.86 1.80 14.35 7.70

RLDRAM II 36-bit Design 267 1.08 2.75 1.98 1.98 2.86 1.26 11.91 5.26

Table 4-6: Measured Power Consumption (Continued)



1.2V 2.5V 3.3VSSTL18

1.8VSSTL22.6V

HSTL1.8V

TOTAL Design

Table 4-7: Estimated Current Usage


Power Plane Current Usage (mA)

1.2V 2.5V 3.3VSSTL18

1.8VSSTL22.6V

HSTL1.8V

DDR1 Registered DIMM 144-bit Design 200 1400 1700 800 900 5100 100


267 1700 1800 600 8300 1100 100

RLDRAM II 72-bit Design

(not implemented on the ML461 board)

267 1400 1100 600 1100 1100 1300




Power Measurements on the ML461R

Table 4-8: Estimated Power Consumption



1.2V 2.5V 3.3VSSTL18

1.8VSSTL22.6V

HSTL1.8V

TOTAL Design


200 1.68 4.25 2.64 1.62 13.26 0.18 23.63 19.98


267 2.04 4.50 1.98 14.94 2.86 0.18 26.50 19.85

RLDRAM_II 72-bit Design (not implemented on the ML461)

267 1.6 2.75 1.98 1.98 2.86 2.34 13.59 6.94





Virtex-4 ML461 Development Board www.xilinx.com 49UG079 (v1.1) September 5, 2007

R

Chapter 5

Signal Integrity Recommendations and Simulations

This chapter provides summaries of the termination schemes for various signals and discusses IBIS simulations. It contains the following sections:

• “Termination and Transmission Line Summaries”

• “IBIS Simulations”

Termination and Transmission Line SummariesThe following bulleted items provide recommendations for the signal termination scheme to the seven different external memories implemented on the Virtex-4 ML461 Development Board:

• Single-ended signals: Simulation indicates that for a single-ended signal, there is no significant performance difference for a signal with split termination of 100Ω + 100Ω between VDD and GND versus the VTT termination of 50Ω to the VREF voltage. Because the power consumption for the split termination is considerably higher than the VTT termination for the SSTL2, SSTL18, and HSTL I/O standards, VTT termination is recommended for single-ended signals on the board, such as data, address, and control.

• Differential signals: For differential pair signals, a 100Ω differential termination is provided between the two legs of the differential pair. This termination is placed closest to the load.

• Bidirectional signals: For bidirectional single-ended signals, for example, DDR2 DQ, the VTT termination is provided at both ends of the signal, that is, at the FPGA as well as at the memory. For differential bidirectional signals, for example, DDR2 DQS, the newly introduced differential SelectIO™ primitives in Virtex-4 FPGAs, for example, DIFF_SSTL_II_18_DCI, account for the differential termination within the IOB. So external differential termination at the FPGA is not required.

• Multiload signals: Address and control signals are driven by the FPGA, and they have multiple loads. The termination is placed at the end of the trace after the last load.


50 www.xilinx.com Virtex-4 ML461 Development BoardUG079 (v1.1) September 5, 2007

R

Table 5-1 through Table 5-7 summarize the termination schemes used on the Virtex-4 ML461 Development Board for the following seven different memory interfaces:

1. DDR1 SDRAM DIMM

2. DDR1 SDRAM Components

3. DDR2 SDRAM DIMM

4. DDR2 SDRAM Components

5. QDR-II SRAM

6. FCRAM-II SDRAM

7. RLDRAM-II SDRAM

Table 5-1: DDR1 SDRAM DIMM Terminations

Signal FPGA Driver Termination at FPGA Termination at Memory

Data (DQ) SSTL2_II 50Ω pull-up to 1.3V 50Ω pull-up to 1.3V

Data Strobe (DQS) SSTL2_II 50Ω pull-up to 1.3V 50Ω pull-up to 1.3V

6 pairs of Clocks (CK, CK), 3 each per DIMM

SSTL2_II No termination 100Ω differential termination between pair

Address (A, BA) SSTL2_II No termination 50Ω pull-up to 1.3V after the second DIMM

Control (RAS, CAS, WE, CS, CKE and others)

SSTL2_II No termination 50Ω pull-up to 1.3V after the second DIMM

Table 5-2: DDR1 SDRAM Components Terminations


Data (DQ) SSTL2_II 50Ω pull-up to 1.3 V 50Ω pull-up to 1.3V

Data Strobe (DQS) SSTL2_II 50Ω pull-up to 1.3 V 50Ω pull-up to 1.3V

Clock (CK, CK) SSTL2_II No termination 100Ω differential termination between pair

Address (A, BA) SSTL2_II No termination 50Ω pull-up to 1.3V after the last component

Control (RAS, CAS, WE, CS, CKE)

SSTL2_II No termination 50Ω pull-up to 1.3V after the last component


Virtex-4 ML461 Development Board www.xilinx.com 51UG079 (v1.1) September 5, 2007

Termination and Transmission Line Summaries R

Table 5-3: DDR2 SDRAM DIMM Terminations



Data Strobe (DQS, DQS) DIFF_SSTL18_II No termination 100Ω differential termination between pair

6 pairs of Clocks (CK, CK), 3 each per DIMM

SSTL18_II No termination 100Ω differential termination between pair

Address (A, BA) SSTL18_II No termination 50Ω pull-up to 0.9V after the second DIMM

Control (RAS, CAS, WE, CS, CKE, and others)

SSTL18_II No termination 50Ω pull-up to 0.9V after the second DIMM

Table 5-4: DDR2 SDRAM Components Terminations



Data Strobe (DQS, DQS) DIFF_SSTL18_II No termination 100Ω differential termination between pair





Table 5-5: QDR-II SRAM Terminations


Write Data (D) HSTL18_I No termination 50Ω pull-up to 0.9V

Read Data (Q) HSTL18_I_DCI No termination No termination

Write Strobe (K, K) HSTL18_I No termination 100Ω differential termination between pair

Read Strobe (CQ, CQ) DIFF_HSTL18_II No termination No termination

Clock (CK, CK) HSTL18_I No termination 100Ω differential termination between pair

Address (A, BA) HSTL18_I No termination 50Ω pull-up to 0.9V after the last component

Control (RAS, CAS, WE, CS, CKE, BW)

HSTL18_I No termination 50Ω pull-up to 0.9V after the last component


52 www.xilinx.com Virtex-4 ML461 Development BoardUG079 (v1.1) September 5, 2007

R

IBIS SimulationsSignal Integrity (SI) simulations were performed during the Virtex-4 ML461 Development Board layout. The simulations utilized a combination of preliminary Virtex-4 device IBIS and HSPICE models, as well as memory models available from memory vendors at that time.

Table 5-6: FCRAM-II SDRAM Terminations



Write Strobe (DS) SSTL18_I No termination 50Ω pull-up to 0.9V

Read Strobe (QS) SSTL18_I 50Ω pull-up to 0.9V No termination





Table 5-7: RLDRAM-II SDRAM Terminations


Data (DQ) HSTL18_II 50Ω pull-up to 0.9V 50Ω pull-up to 0.9V

Write Strobe (DK, DK) DIFF_HSTL18_II No termination 100Ω differential termination between pair

Read Strobe (QK, QK) HSTL18_II No termination No termination

Clock (CK, CK) HSTL18_II No termination 100Ω differential termination between pair

Address (A, BA) HSTL18_II No termination 50Ω pull-up to 0.9V after the last component


HSTL18_II No termination 50Ω pull-up to 0.9V after the last component



R

Chapter 6

Configuration

This chapter provides a brief description of the FPGA configuration methods used on the Virtex-4 ML461 Development Board. This chapter contains the following sections:

• “Configuration Modes”

• “JTAG Chain”

• “JTAG Port”

• “Parallel Cable IV Port”

• “System ACE Interface”

Configuration ModesThe Virtex-4 ML461 Memory Interfaces Development Board includes several options to configure the Virtex-4 FPGAs. The configuration modes are:

• System ACE mode

• JTAG mode

Table 6-1 shows the Virtex-4 configuration modes. The Master and Slave (Parallel) SelectMap configuration modes are not supported on the Virtex-4 ML461 Development Board. Figure 6-1 shows the Configuration Mode switch (SW1).

Table 6-1: Configuration Modes

ModeXCONFIG

P31JTAG

P64 or P65

Mode SW1(3,4)

3(M2)

2(M1)

1(M0)

Master Serial X(1) —(2) 0 0 0

Slave Serial X — 1 1 1

Master SelectMAP — — 0 1 1

Slave SelectMAP — — 1 1 0

JTAG — X 1 0 1

System ACE CF Card — — 1 1 1

Notes: 1. X = Supported.2. — = Not applicable.3. 0 = SW1 switch position (n) is Closed.4. 1 = SW1 switch position (n) is Open.



Chapter 6: ConfigurationR

JTAG ChainFive devices (the System ACE chip and four XC4VLX25-FF668 FPGAs) are connected via a JTAG chain on the Virtex-4 ML461 Development Board. The order of the five devices in the JTAG chain is System ACE chip (U36), FPGA #1 (U15), FPGA #2 (U14), FPGA #3 (U23), and FPGA #4 (U33). The DONE pin of the FPGAs in the chain are tied together to a single LED (D1). Each FPGA in the JTAG chain must be programmed for the board to be configured properly. A blank design can be used to program FPGAs in the JTAG chain that do not need functionality.

Three different sources can be used to drive this JTAG chain:

• JTAG Port

• Xilinx Parallel Cable IV

• System ACE controller

JTAG PortThe Virtex-4 ML461 Development Board provides a JTAG connector (P65) that can be used to program the Virtex-4 FPGAs, and program and/or configure other JTAG devices in the chain. Figure 6-2 shows the pin assignments for the JTAG connector on the Virtex-4 ML461 Development Board.

Figure 6-1: Configuration Mode Switch

SW1

MODEug079_c6_01_080105

12

3

OP

EN

Figure 6-2: JTAG Connector P65

P65 JTAGConnector

1

3

5

7

9

11

13

15

2

4

6

8

10

12

14

16

TSTTDO

TSTTCK

TSTTMS

HALTB

TSTTDI TRSTB

3.3V

GND

ug079_c6_02_080105



Parallel Cable IV PortR

Table 6-2 describes the P65 JTAG Header signal names, descriptions, and pin assignments.

Parallel Cable IV PortThe Virtex-4 ML461 Development Board provides a Parallel Cable IV connector (P64) to configure the Virtex-4 FPGAs and program JTAG devices located in the JTAG chain.

System ACE InterfaceThe Virtex-4 ML461 Development Board provides a System ACE interface to configure the Virtex-4 FPGA. The interface also gives software designers the ability to run code (for soft processor IP within the FPGA) from removable CompactFlash cards.

Refer to the Xilinx System ACE CompactFlash Solution data sheet (DS080) for detailed information on creating System ACE compatible ACE files, formatting the CompactFlash card, and storing multiple design images.

Table 6-3 shows the System ACE interface signal names, descriptions, and pin assignments.

Table 6-2: P65 JTAG Header Signal Descriptions and Pin Assignments

Signal Name DescriptionP65 Pin Number

System ACE Pin Number

TSTTDO JTAG TDO from System ACE Interface

1 97

TSTTDI JTAG TDI to System ACE Interface

3 102

TSTTCK JTAG TCK to System ACE Interface

7 101

TSTTMS JTAG TMS to System ACE Interface

9 98

HALTB User Defined 11 N/A; goes to FPGA pin V5

TRSTB User Defined 4 N/A; goes to PFGA pin V6

Table 6-3: System ACE Interface Signal Descriptions


Signal Name FPGA Pin Number

70 SYSACE_MPA0 Y26

69 SYSACE_MPA1 Y25

68 SYSACE_MPA2 V20

67 SYSACE_MPA3 W20

45 SYSACE_MPA4 W24

44 SYSACE_MPA5 W23

43 SYSACE_MPA6 W22




Chapter 6: ConfigurationR

66 SYSACE_MPD0 AB26

65 SYSACE_MPD1 AC25

63 SYSACE_MPD2 Y24

62 SYSACE_MPD3 AA24

61 SYSACE_MPD4 AC21

60 SYSACE_MPD5 AB21

59 SYSACE_MPD6 AB25

58 SYSACE_MPD7 AB24

77 SYSACE_CTRL0/MPOE W21

76 SYSACE_CTRL1/MPWE W26

42 SYSACE_CTRL2/MPCE W25

41 SYSACE_CTRL3/MPIRQ V22

39 SYSACE_CTRL4/MPBRDY V21

93 SYSACE_CLK AC26

Table 6-3: System ACE Interface Signal Descriptions (Continued)


Signal Name FPGA Pin Number



R

Appendix A

FPGA Pinouts

This appendix provides the pinouts for the four FPGAs on the Virtex-4 ML461 Development Board.

FPGA #1 PinoutTable A-1 lists the connections for FPGA #1 (U14).

Table A-1: FPGA #1 Pinout

Signal Name Pin Signal Name Pin

DDR1 DIMM Memory Interface

DDR1_DIMM_A0 Y9 DDR1_DIMM_BY8_15_CK0_N P2

DDR1_DIMM_A1 AA9 DDR1_DIMM_BY8_15_CK0_P P3

DDR1_DIMM_A2 V1 DDR1_DIMM_BY8_15_CK1_N P4

DDR1_DIMM_A3 V2 DDR1_DIMM_BY8_15_CK1_P P5

DDR1_DIMM_A4 T6 DDR1_DIMM_BY8_15_CK2_N P6

DDR1_DIMM_A5 T7 DDR1_DIMM_BY8_15_CK2_P P7

DDR1_DIMM_A6 T3 DDR1_DIMM_BY8_15_CS_N N2

DDR1_DIMM_A7 T4 DDR1_DIMM_CAS_N F1

DDR1_DIMM_A8 U3 DDR1_DIMM_CKE R1

DDR1_DIMM_A9 R4 DDR1_DIMM_DM_DQS_BY0_H_N D6

DDR1_DIMM_A10 AD5 DDR1_DIMM_DM_DQS_BY0_H_P E7

DDR1_DIMM_A11 M6 DDR1_DIMM_DM_DQS_BY1_H_N C7

DDR1_DIMM_A12 M4 DDR1_DIMM_DM_DQS_BY1_H_P B7

DDR1_DIMM_BA0 Y8 DDR1_DIMM_DM_DQS_BY2_H_N H25

DDR1_DIMM_BA1 AA8 DDR1_DIMM_DM_DQS_BY2_H_P H26

DDR1_DIMM_BY0_7_CK0_N N4 DDR1_DIMM_DM_DQS_BY3_H_N E24

DDR1_DIMM_BY0_7_CK0_P N5 DDR1_DIMM_DM_DQS_BY3_H_P E25

DDR1_DIMM_BY8_15_CK0_N P2 DDR1_DIMM_DM_DQS_BY4_H_N AF20

DDR1_DIMM_BY8_15_CK0_P P3 DDR1_DIMM_DM_DQS_BY4_H_P AF19

DDR1_DIMM_BY8_15_CK1_N P4 DDR1_DIMM_DM_DQS_BY5_H_N Y18

DDR1_DIMM_BY8_15_CK1_P P5 DDR1_DIMM_DM_DQS_BY5_H_P AA18

DDR1_DIMM_BY8_15_CK2_N P6 DDR1_DIMM_DM_DQS_BY6_H_N AB9



Appendix A: FPGA PinoutsR

DDR1 DIMM Memory Interface (cont’d)

DDR1_DIMM_DM_DQS_BY6_H_P AC9 DDR1_DIMM_DQS_BY7_L_N AB6

DDR1_DIMM_DM_DQS_BY7_H_N AE4 DDR1_DIMM_DQS_BY7_L_P AC6

DDR1_DIMM_DM_DQS_BY7_H_P AF4 DDR1_DIMM_DQS_BY8_L_N E2

DDR1_DIMM_DM_DQS_BY8_H_N H5 DDR1_DIMM_DQS_BY8_L_P E3

DDR1_DIMM_DM_DQS_BY8_H_P H6 DDR1_DIMM_DQS_BY9_L_N D1

DDR1_DIMM_DM_DQS_BY9_H_N K6 DDR1_DIMM_DQS_BY9_L_P D2

DDR1_DIMM_DM_DQS_BY9_H_P K7 DDR1_DIMM_DQS_BY10_L_N G17

DDR1_DIMM_DM_DQS_BY10_H_N A19 DDR1_DIMM_DQS_BY10_L_P G18

DDR1_DIMM_DM_DQS_BY10_H_P A20 DDR1_DIMM_DQS_BY11_L_N A23

DDR1_DIMM_DM_DQS_BY11_H_N A18 DDR1_DIMM_DQS_BY11_L_P A24

DDR1_DIMM_DM_DQS_BY11_H_P B18 DDR1_DIMM_DQS_BY12_L_N Y24

DDR1_DIMM_DM_DQS_BY12_H_N AB22 DDR1_DIMM_DQS_BY12_L_P AA24

DDR1_DIMM_DM_DQS_BY12_H_P AC22 DDR1_DIMM_DQS_BY13_L_N AC19

DDR1_DIMM_DM_DQS_BY13_H_N AE18 DDR1_DIMM_DQS_BY13_L_P AD19

DDR1_DIMM_DM_DQS_BY13_H_P AF18 DDR1_DIMM_DQS_BY14_L_N Y3

DDR1_DIMM_DM_DQS_BY14_H_N W5 DDR1_DIMM_DQS_BY14_L_P Y4

DDR1_DIMM_DM_DQS_BY14_H_P W6 DDR1_DIMM_DQS_BY15_L_N Y5

DDR1_DIMM_DM_DQS_BY15_H_N AB5 DDR1_DIMM_DQS_BY15_L_P Y6

DDR1_DIMM_DM_DQS_BY15_H_P AC5 DDR1_DIMM_DQS_CB0_7_L_N T23

DDR1_DIMM_DM_DQS_CB0_7_H_N P19 DDR1_DIMM_DQS_CB0_7_L_P T24

DDR1_DIMM_DM_DQS_CB0_7_H_P P20 DDR1_DIMM_DQS_CB8_15_L_N R19

DDR1_DIMM_DM_DQS_CB8_15_H_N T19 DDR1_DIMM_DQS_CB8_15_L_P R20

DDR1_DIMM_DM_DQS_CB8_15_H_P U20 DDR1_DIMM_DQ_BY0_B0 C4

DDR1_DIMM_DQS_BY0_L_N G9 DDR1_DIMM_DQ_BY0_B1 D4

DDR1_DIMM_DQS_BY0_L_P G10 DDR1_DIMM_DQ_BY0_B2 A4

DDR1_DIMM_DQS_BY1_L_N C6 DDR1_DIMM_DQ_BY0_B3 B4

DDR1_DIMM_DQS_BY1_L_P B6 DDR1_DIMM_DQ_BY0_B4 F7

DDR1_DIMM_DQS_BY2_L_N D25 DDR1_DIMM_DQ_BY0_B5 G7

DDR1_DIMM_DQS_BY2_L_P D26 DDR1_DIMM_DQ_BY0_B6 E6

DDR1_DIMM_DQS_BY3_L_N F23 DDR1_DIMM_DQ_BY0_B7 E5

DDR1_DIMM_DQS_BY3_L_P F24 DDR1_DIMM_DQ_BY1_B0 A5

DDR1_DIMM_DQS_BY4_L_N AC26 DDR1_DIMM_DQ_BY1_B1 A6

DDR1_DIMM_DQS_BY4_L_P AC25 DDR1_DIMM_DQ_BY1_B2 E9

DDR1_DIMM_DQS_BY5_L_N AB21 DDR1_DIMM_DQ_BY1_B3 F9

DDR1_DIMM_DQS_BY5_L_P AC21 DDR1_DIMM_DQ_BY1_B4 G8

DDR1_DIMM_DQS_BY6_L_N AF7 DDR1_DIMM_DQ_BY1_B5 F8

DDR1_DIMM_DQS_BY6_L_P AF8 DDR1_DIMM_DQ_BY1_B6 A9

Table A-1: FPGA #1 Pinout (Continued)




FPGA #1 PinoutR


DDR1_DIMM_DQ_BY1_B7 B9 DDR1_DIMM_DQ_BY5_B4 AE24

DDR1_DIMM_DQ_BY2_B0 J20 DDR1_DIMM_DQ_BY5_B5 AF24

DDR1_DIMM_DQ_BY2_B0_N K22 DDR1_DIMM_DQ_BY5_B6 AE23

DDR1_DIMM_DQ_BY2_B1 G24 DDR1_DIMM_DQ_BY5_B6_N Y20


DDR1_DIMM_DQ_BY2_B2_N J26 DDR1_DIMM_DQ_BY6_B0 AA10

DDR1_DIMM_DQ_BY2_B3 J23 DDR1_DIMM_DQ_BY6_B0_N AC7

DDR1_DIMM_DQ_BY2_B3_N K21 DDR1_DIMM_DQ_BY6_B1 Y10

DDR1_DIMM_DQ_BY2_B4 G26 DDR1_DIMM_DQ_BY6_B2 AC8

DDR1_DIMM_DQ_BY2_B5 G25 DDR1_DIMM_DQ_BY6_B3 AD8

DDR1_DIMM_DQ_BY2_B6 H24 DDR1_DIMM_DQ_BY6_B4 AE9

DDR1_DIMM_DQ_BY2_B7 H23 DDR1_DIMM_DQ_BY6_B5 AF9

DDR1_DIMM_DQ_BY3_B0 C23 DDR1_DIMM_DQ_BY6_B6 AD6

DDR1_DIMM_DQ_BY3_B1 D23 DDR1_DIMM_DQ_BY6_B7 AE6

DDR1_DIMM_DQ_BY3_B2 G20 DDR1_DIMM_DQ_BY7_B0 AD1

DDR1_DIMM_DQ_BY3_B2_N C26 DDR1_DIMM_DQ_BY7_B1 AD2

DDR1_DIMM_DQ_BY3_B3 H20 DDR1_DIMM_DQ_BY7_B2 AE3

DDR1_DIMM_DQ_BY3_B4 F26 DDR1_DIMM_DQ_BY7_B3 AF3

DDR1_DIMM_DQ_BY3_B5 E26 DDR1_DIMM_DQ_BY7_B4 AC3

DDR1_DIMM_DQ_BY3_B6 H22 DDR1_DIMM_DQ_BY7_B5 AD3

DDR1_DIMM_DQ_BY3_B7 H21 DDR1_DIMM_DQ_BY7_B6 AF5

DDR1_DIMM_DQ_BY4_B0 AA26 DDR1_DIMM_DQ_BY7_B6_N AA7

DDR1_DIMM_DQ_BY4_B0_N Y26 DDR1_DIMM_DQ_BY7_B7 AF6

DDR1_DIMM_DQ_BY4_B1 AB26 DDR1_DIMM_DQ_BY8_B0 H8

DDR1_DIMM_DQ_BY4_B1_N Y25 DDR1_DIMM_DQ_BY8_B1 H7

DDR1_DIMM_DQ_BY4_B2 AB25 DDR1_DIMM_DQ_BY8_B2 E4

DDR1_DIMM_DQ_BY4_B2_N V20 DDR1_DIMM_DQ_BY8_B3 D3

DDR1_DIMM_DQ_BY4_B3 AB24 DDR1_DIMM_DQ_BY8_B4 G2

DDR1_DIMM_DQ_BY4_B3_N W20 DDR1_DIMM_DQ_BY8_B5 G1

DDR1_DIMM_DQ_BY4_B4 AC24 DDR1_DIMM_DQ_BY8_B6 F3

DDR1_DIMM_DQ_BY4_B5 AC23 DDR1_DIMM_DQ_BY8_B7 F4

DDR1_DIMM_DQ_BY4_B6 AD23 DDR1_DIMM_DQ_BY9_B0 H4

DDR1_DIMM_DQ_BY4_B7 AD22 DDR1_DIMM_DQ_BY9_B1 H3

DDR1_DIMM_DQ_BY5_B0 W19 DDR1_DIMM_DQ_BY9_B2 H2

DDR1_DIMM_DQ_BY5_B1 Y19 DDR1_DIMM_DQ_BY9_B3 H1

DDR1_DIMM_DQ_BY5_B2 AA19 DDR1_DIMM_DQ_BY9_B4 J7

DDR1_DIMM_DQ_BY5_B3 AA20 DDR1_DIMM_DQ_BY9_B4_N L7







DDR1_DIMM_DQ_BY9_B5 J6 DDR1_DIMM_DQ_BY12_B6 AD26

DDR1_DIMM_DQ_BY9_B5_N L6 DDR1_DIMM_DQ_BY12_B6_N Y22

DDR1_DIMM_DQ_BY9_B6 J5 DDR1_DIMM_DQ_BY12_B7 AD25

DDR1_DIMM_DQ_BY9_B6_N K5 DDR1_DIMM_DQ_BY13_B0 AA17

DDR1_DIMM_DQ_BY9_B7 J4 DDR1_DIMM_DQ_BY13_B0_N AB20

DDR1_DIMM_DQ_BY9_B7_N K4 DDR1_DIMM_DQ_BY13_B1 Y17

DDR1_DIMM_DQ_BY10_B0 D24 DDR1_DIMM_DQ_BY13_B2 AB18

DDR1_DIMM_DQ_BY10_B1 C24 DDR1_DIMM_DQ_BY13_B3 AC18

DDR1_DIMM_DQ_BY10_B2 A22 DDR1_DIMM_DQ_BY13_B4 AF22

DDR1_DIMM_DQ_BY10_B3 A21 DDR1_DIMM_DQ_BY13_B5 AF21

DDR1_DIMM_DQ_BY10_B4 F18 DDR1_DIMM_DQ_BY13_B6 AD21

DDR1_DIMM_DQ_BY10_B5 E18 DDR1_DIMM_DQ_BY13_B7 AE21

DDR1_DIMM_DQ_BY10_B6 C22 DDR1_DIMM_DQ_BY14_B0 V5

DDR1_DIMM_DQ_BY10_B7 D22 DDR1_DIMM_DQ_BY14_B1 V6

DDR1_DIMM_DQ_BY10_B7_N E21 DDR1_DIMM_DQ_BY14_B2 W1

DDR1_DIMM_DQ_BY11_B0 C19 DDR1_DIMM_DQ_BY14_B3 W2

DDR1_DIMM_DQ_BY11_B0_N E17 DDR1_DIMM_DQ_BY14_B4 V7

DDR1_DIMM_DQ_BY11_B1 D18 DDR1_DIMM_DQ_BY14_B4_N W4

DDR1_DIMM_DQ_BY11_B1_N F17 DDR1_DIMM_DQ_BY14_B5 W7

DDR1_DIMM_DQ_BY11_B2 C21 DDR1_DIMM_DQ_BY14_B6 Y1

DDR1_DIMM_DQ_BY11_B2_N B24 DDR1_DIMM_DQ_BY14_B7 Y2

DDR1_DIMM_DQ_BY11_B3 B21 DDR1_DIMM_DQ_BY15_B0 AA1

DDR1_DIMM_DQ_BY11_B3_N B23 DDR1_DIMM_DQ_BY15_B1 AB1

DDR1_DIMM_DQ_BY11_B4 C17 DDR1_DIMM_DQ_BY15_B2 AA3

DDR1_DIMM_DQ_BY11_B5 D17 DDR1_DIMM_DQ_BY15_B3 AA4

DDR1_DIMM_DQ_BY11_B5_N D20 DDR1_DIMM_DQ_BY15_B4 AB4

DDR1_DIMM_DQ_BY11_B6 C20 DDR1_DIMM_DQ_BY15_B4_N AB3

DDR1_DIMM_DQ_BY11_B7 B20 DDR1_DIMM_DQ_BY15_B5 AC4

DDR1_DIMM_DQ_BY12_B0 W26 DDR1_DIMM_DQ_BY15_B6 AC1

DDR1_DIMM_DQ_BY12_B0_N W23 DDR1_DIMM_DQ_BY15_B7 AC2

DDR1_DIMM_DQ_BY12_B1 W25 DDR1_DIMM_DQ_CB0_7_B0 P25

DDR1_DIMM_DQ_BY12_B1_N W22 DDR1_DIMM_DQ_CB0_7_B0_N N23

DDR1_DIMM_DQ_BY12_B2 V22 DDR1_DIMM_DQ_CB0_7_B1 P24

DDR1_DIMM_DQ_BY12_B2_N W21 DDR1_DIMM_DQ_CB0_7_B1_N N22

DDR1_DIMM_DQ_BY12_B3 V21 DDR1_DIMM_DQ_CB0_7_B2 T26

DDR1_DIMM_DQ_BY12_B4 AA23 DDR1_DIMM_DQ_CB0_7_B3 U26

DDR1_DIMM_DQ_BY12_B5 AB23 DDR1_DIMM_DQ_CB0_7_B4 R24





FPGA #1 PinoutR


DDR1_DIMM_DQ_CB0_7_B4_N R26 DDR1_DIMM_DQ_CB8_15_B4 V26

DDR1_DIMM_DQ_CB0_7_B5 P23 DDR1_DIMM_DQ_CB8_15_B5 V25

DDR1_DIMM_DQ_CB0_7_B5_N N21 DDR1_DIMM_DQ_CB8_15_B6 T21

DDR1_DIMM_DQ_CB0_7_B6 P22 DDR1_DIMM_DQ_CB8_15_B7 T20

DDR1_DIMM_DQ_CB0_7_B6_N N20 DDR1_DIMM_RESET_N L1

DDR1_DIMM_DQ_CB0_7_B7 R23 DDR1_DIMM_SA0 L3

DDR1_DIMM_DQ_CB8_15_B0 U22 DDR1_DIMM_SA1 M8

DDR1_DIMM_DQ_CB8_15_B1 U21 DDR1_DIMM_SA2 L8

DDR1_DIMM_DQ_CB8_15_B2 U23 DDR1_DIMM_SCL K2

DDR1_DIMM_DQ_CB8_15_B3 V23 DDR1_DIMM_SDA L4

DDR1_DIMM_DQ_CB8_15_B3_N U25 DDR1_DIMM_WE_N M5

DDR1 Component Memory Interface

DDR1_A0 D12 DDR1_CK2_P AA16

DDR1_A1 E13 DDR1_CK3_N AD14

DDR1_A2 D11 DDR1_CK3_P AC14

DDR1_A3 C11 DDR1_CKE AC15

DDR1_A4 E14 DDR1_DM_BY0 J2

DDR1_A5 D15 DDR1_DM_BY1 K3

DDR1_A6 D14 DDR1_DM_BY2 M2

DDR1_A7 F15 DDR1_DM_BY3 M1

DDR1_A8 F16 DDR1_DQS_BY0_L_N A7

DDR1_A9 F11 DDR1_DQS_BY0_L_P A8

DDR1_A10 D16 DDR1_DQS_BY1_P K26

DDR1_A11 F12 DDR1_DQS_BY2_P M19

DDR1_A12 F13 DDR1_DQS_BY3_P U1

DDR1_BA0 AC13 DDR1_DQ_BY0_B0 D9

DDR1_BA1 AD13 DDR1_DQ_BY0_B1 C8

DDR1_BY0_CS0_N G19 DDR1_DQ_BY0_B2 C10

DDR1_BY0_CS1_N F19 DDR1_DQ_BY0_B3 D10

DDR1_BY1_CS_N E23 DDR1_DQ_BY1_B0 L19

DDR1_BY2_3_CS_N E22 DDR1_DQ_BY1_B1 K20

DDR1_CAS_N AA11 DDR1_DQ_BY1_B2 L21

DDR1_CK0_N AB14 DDR1_DQ_BY1_B3 L20

DDR1_CK0_P AA14 DDR1_DQ_BY1_B4 K24

DDR1_CK1_N AC11 DDR1_DQ_BY1_B5 K23

DDR1_CK1_P AC12 DDR1_DQ_BY1_B6 L24

DDR1_CK2_N AA15 DDR1_DQ_BY1_B7 L23






DDR1 Component Memory Interface (cont’d)

DDR1_DQ_BY2_B0 M25 DDR1_DQ_BY3_B3 U4

DDR1_DQ_BY2_B1 M24 DDR1_DQ_BY3_B4 T8




DDR1_DQ_BY2_B5 M22 DDR1_RAS_N AA12

DDR1_DQ_BY2_B6 N25 DDR1_READ_VALID_LOOPBACK D8

DDR1_DQ_BY2_B7 N24 DDR1_READ_VALID_LOOPBACK F10

DDR1_DQ_BY3_B0 R8 DDR1_READ_VALID_LOOPBACK_BANK9 J21

DDR1_DQ_BY3_B1 R7 DDR1_READ_VALID_LOOPBACK_BANK9 L26

DDR1_DQ_BY3_B2 V4 DDR1_WE_N AC16

FPGA #1 Clock Signals

SYNTH_CLK_TO_FPGA1_N C14 EXT_CLK_TO_FPGA1_P B15

SYNTH_CLK_TO_FPGA1_P C15 DIRECT_CLK_TO_FPGA1_N A15

EXT_CLK_TO_FPGA1_N B14 DIRECT_CLK_TO_FPGA1_P A16

FPGA #1 MII Link Interface

FPGA4_FPGA1_MII_TX_CLK AF12 FPGA1_FPGA4_MII_TX_CLK AE14

FPGA4_FPGA1_MII_TX_DATA_B0 AB10 FPGA1_FPGA4_MII_TX_DATA_B0 AD10


FPGA4_FPGA1_MII_TX_DATA_B2 AC17 FPGA1_FPGA4_MII_TX_DATA_B2 AD16

FPGA4_FPGA1_MII_TX_DATA_B3 AF11 FPGA1_FPGA4_MII_TX_DATA_B3 AD12

FPGA4_FPGA1_MII_TX_EN AE12 FPGA1_FPGA4_MII_TX_EN AE13

FPGA4_FPGA1_MII_TX_ERR AC10 FPGA1_FPGA4_MII_TX_ERR AE10

FPGA4_FPGA1_MII_TX_SPARE AF10 FPGA1_FPGA4_MII_TX_SPARE AD11

FPGA #1 Configuration Signals

FPGA_CCLK G14 FPGA_PROGB H15

FPGA_CNFG_M0 W15 FPGA_TCK W12

FPGA_CNFG_M1 Y15 FPGA_TDO Y13

FPGA_CNFG_M2 W14 FPGA_TMS Y11

FPGA_DIN G12 FPGA_VBATT Y16

FPGA_DONE H14 SYS_RESET_IN_N K1

FPGA_INIT G15

FPGA #1 Test Header Signals

FPGA1_TEST_HDR_B0 A12 FPGA1_TEST_HDR_B2 B13


FPGA #1 Test Header Signals (cont’d)





FPGA #1 PinoutR


FPGA1_TEST_HDR_B5 B10 FPGA1_TEST_HDR_B7 A17









DDR2 DIMM Memory Interface

DDR2_DIMM_A0 Y9 DDR2_DIMM_CKE R1

DDR2_DIMM_A1 AA9 DDR2_DIMM_DM_DQS_BY0_H_N A18

DDR2_DIMM_A2 V1 DDR2_DIMM_DM_DQS_BY0_H_P B18

DDR2_DIMM_A3 V2 DDR2_DIMM_DM_DQS_BY1_H_N E24

DDR2_DIMM_A4 T6 DDR2_DIMM_DM_DQS_BY1_H_P E25

DDR2_DIMM_A5 T7 DDR2_DIMM_DM_DQS_BY2_H_N H5

DDR2_DIMM_A6 T3 DDR2_DIMM_DM_DQS_BY2_H_P H6

DDR2_DIMM_A7 T4 DDR2_DIMM_DM_DQS_BY3_H_N K6

DDR2_DIMM_A8 U3 DDR2_DIMM_DM_DQS_BY3_H_P K7

DDR2_DIMM_A9 R4 DDR2_DIMM_DM_DQS_BY4_H_N W5

DDR2_DIMM_A10 AD5 DDR2_DIMM_DM_DQS_BY4_H_P W6

DDR2_DIMM_A11 M6 DDR2_DIMM_DM_DQS_BY5_H_N AE4

DDR2_DIMM_A12 M4 DDR2_DIMM_DM_DQS_BY5_H_P AF4

DDR2_DIMM_A13 AD4 DDR2_DIMM_DM_DQS_BY6_H_N AB22

DDR2_DIMM_BA0 Y8 DDR2_DIMM_DM_DQS_BY6_H_P AC22

DDR2_DIMM_BA1 AA8 DDR2_DIMM_DM_DQS_BY7_H_N Y18

DDR2_DIMM_BA2 R2 DDR2_DIMM_DM_DQS_BY7_H_P AA18

DDR2_DIMM_BY0_7_CK0_N N4 DDR2_DIMM_DM_DQS_BY8_H_N A19

DDR2_DIMM_BY0_7_CK0_P N5 DDR2_DIMM_DM_DQS_BY8_H_P A20

DDR2_DIMM_BY0_7_CK1_N M7 DDR2_DIMM_DM_DQS_BY9_H_N H25

DDR2_DIMM_BY0_7_CK1_P N7 DDR2_DIMM_DM_DQS_BY9_H_P H26

DDR2_DIMM_BY0_7_CK2_N N8 DDR2_DIMM_DM_DQS_BY10_H_N C7

DDR2_DIMM_BY0_7_CK2_P P8 DDR2_DIMM_DM_DQS_BY10_H_P B7

DDR2_DIMM_BY0_7_CS_N N3 DDR2_DIMM_DM_DQS_BY11_H_N D6

DDR2_DIMM_BY0_7_ODT F20 DDR2_DIMM_DM_DQS_BY11_H_P E7


DDR2_DIMM_BY8_15_CK0_P P3 DDR2_DIMM_DM_DQS_BY12_H_P AC5


DDR2_DIMM_BY8_15_CK1_P P5 DDR2_DIMM_DM_DQS_BY13_H_P AC9

DDR2_DIMM_BY8_15_CK2_N P6 DDR2_DIMM_DM_DQS_BY14_H_N AF20

DDR2_DIMM_BY8_15_CK2_P P7 DDR2_DIMM_DM_DQS_BY14_H_P AF19

DDR2_DIMM_BY8_15_CS_N N2 DDR2_DIMM_DM_DQS_BY15_H_N AE18

DDR2_DIMM_BY8_15_ODT E20 DDR2_DIMM_DM_DQS_BY15_H_P AF18

DDR2_DIMM_CAS_N F1 DDR2_DIMM_DM_DQS_CB0_7_H_N P19



FPGA #2 PinoutR


DDR2_DIMM_DM_DQS_CB0_7_H_P P20 DDR2_DIMM_DQS_CB8_15_L_N R19

DDR2_DIMM_DM_DQS_CB8_15_H_N T19 DDR2_DIMM_DQS_CB8_15_L_P R20

DDR2_DIMM_DM_DQS_CB8_15_H_P U20 DDR2_DIMM_DQ_BY0_B0 C21

DDR2_DIMM_DQS_BY0_L_N A23 DDR2_DIMM_DQ_BY0_B0_N E17

DDR2_DIMM_DQS_BY0_L_P A24 DDR2_DIMM_DQ_BY0_B1 B21

DDR2_DIMM_DQS_BY1_L_N F23 DDR2_DIMM_DQ_BY0_B1_N F17

DDR2_DIMM_DQS_BY1_L_P F24 DDR2_DIMM_DQ_BY0_B2 D18

DDR2_DIMM_DQS_BY2_L_N E2 DDR2_DIMM_DQ_BY0_B2_N B24

DDR2_DIMM_DQS_BY2_L_P E3 DDR2_DIMM_DQ_BY0_B3 C19

DDR2_DIMM_DQS_BY3_L_N D1 DDR2_DIMM_DQ_BY0_B3_N B23

DDR2_DIMM_DQS_BY3_L_P D2 DDR2_DIMM_DQ_BY0_B4 C20

DDR2_DIMM_DQS_BY4_L_N Y3 DDR2_DIMM_DQ_BY0_B5 B20

DDR2_DIMM_DQS_BY4_L_P Y4 DDR2_DIMM_DQ_BY0_B5_N D20

DDR2_DIMM_DQS_BY5_L_N AB6 DDR2_DIMM_DQ_BY0_B6 C17

DDR2_DIMM_DQS_BY5_L_P AC6 DDR2_DIMM_DQ_BY0_B7 D17

DDR2_DIMM_DQS_BY6_L_N Y24 DDR2_DIMM_DQ_BY1_B0 C23

DDR2_DIMM_DQS_BY6_L_P AA24 DDR2_DIMM_DQ_BY1_B1 D23

DDR2_DIMM_DQS_BY7_L_N AB21 DDR2_DIMM_DQ_BY1_B2 G20

DDR2_DIMM_DQS_BY7_L_P AC21 DDR2_DIMM_DQ_BY1_B2_N C26

DDR2_DIMM_DQS_BY8_L_N G17 DDR2_DIMM_DQ_BY1_B3 H20

DDR2_DIMM_DQS_BY8_L_P G18 DDR2_DIMM_DQ_BY1_B4 E26

DDR2_DIMM_DQS_BY9_L_N D25 DDR2_DIMM_DQ_BY1_B5 F26

DDR2_DIMM_DQS_BY9_L_P D26 DDR2_DIMM_DQ_BY1_B6 H21

DDR2_DIMM_DQS_BY10_L_N C6 DDR2_DIMM_DQ_BY1_B7 H22

DDR2_DIMM_DQS_BY10_L_P B6 DDR2_DIMM_DQ_BY2_B0 E4

DDR2_DIMM_DQS_BY11_L_N G9 DDR2_DIMM_DQ_BY2_B1 D3

DDR2_DIMM_DQS_BY11_L_P G10 DDR2_DIMM_DQ_BY2_B2 H8

DDR2_DIMM_DQS_BY12_L_N Y5 DDR2_DIMM_DQ_BY2_B3 H7

DDR2_DIMM_DQS_BY12_L_P Y6 DDR2_DIMM_DQ_BY2_B4 F3

DDR2_DIMM_DQS_BY13_L_N AF7 DDR2_DIMM_DQ_BY2_B5 F4

DDR2_DIMM_DQS_BY13_L_P AF8 DDR2_DIMM_DQ_BY2_B6 G2

DDR2_DIMM_DQS_BY14_L_N AC26 DDR2_DIMM_DQ_BY2_B7 G1

DDR2_DIMM_DQS_BY14_L_P AC25 DDR2_DIMM_DQ_BY3_B0 H2

DDR2_DIMM_DQS_BY15_L_N AC19 DDR2_DIMM_DQ_BY3_B1 H1

DDR2_DIMM_DQS_BY15_L_P AD19 DDR2_DIMM_DQ_BY3_B2 H4

DDR2_DIMM_DQS_CB0_7_L_N T23 DDR2_DIMM_DQ_BY3_B3 H3

DDR2_DIMM_DQS_CB0_7_L_P T24 DDR2_DIMM_DQ_BY3_B4 J6







DDR2_DIMM_DQ_BY3_B4_N L7 DDR2_DIMM_DQ_BY7_B0 W19

DDR2_DIMM_DQ_BY3_B5 J7 DDR2_DIMM_DQ_BY7_B1 Y19

DDR2_DIMM_DQ_BY3_B5_N L6 DDR2_DIMM_DQ_BY7_B2 AA19

DDR2_DIMM_DQ_BY3_B6 J4 DDR2_DIMM_DQ_BY7_B3 AA20




DDR2_DIMM_DQ_BY4_B0 V5 DDR2_DIMM_DQ_BY7_B6_N Y20

DDR2_DIMM_DQ_BY4_B1 V6 DDR2_DIMM_DQ_BY7_B7 AF23

DDR2_DIMM_DQ_BY4_B2 W1 DDR2_DIMM_DQ_BY8_B0 D24

DDR2_DIMM_DQ_BY4_B3 W2 DDR2_DIMM_DQ_BY8_B1 C24

DDR2_DIMM_DQ_BY4_B4 V7 DDR2_DIMM_DQ_BY8_B2 A22

DDR2_DIMM_DQ_BY4_B4_N W4 DDR2_DIMM_DQ_BY8_B3 A21

DDR2_DIMM_DQ_BY4_B5 W7 DDR2_DIMM_DQ_BY8_B4 C22

DDR2_DIMM_DQ_BY4_B6 Y1 DDR2_DIMM_DQ_BY8_B5 D22

DDR2_DIMM_DQ_BY4_B7 Y2 DDR2_DIMM_DQ_BY8_B6 F18

DDR2_DIMM_DQ_BY5_B0 AD1 DDR2_DIMM_DQ_BY8_B7 E18

DDR2_DIMM_DQ_BY5_B1 AD2 DDR2_DIMM_DQ_BY8_B7_N E21

DDR2_DIMM_DQ_BY5_B2 AE3 DDR2_DIMM_DQ_BY9_B0 J23

DDR2_DIMM_DQ_BY5_B3 AF3 DDR2_DIMM_DQ_BY9_B0_N K21

DDR2_DIMM_DQ_BY5_B4 AC3 DDR2_DIMM_DQ_BY9_B1 G24

DDR2_DIMM_DQ_BY5_B5 AD3 DDR2_DIMM_DQ_BY9_B2 J22

DDR2_DIMM_DQ_BY5_B6 AF5 DDR2_DIMM_DQ_BY9_B2_N J26

DDR2_DIMM_DQ_BY5_B6_N AA7 DDR2_DIMM_DQ_BY9_B3 J20

DDR2_DIMM_DQ_BY5_B7 AF6 DDR2_DIMM_DQ_BY9_B3_N K22

DDR2_DIMM_DQ_BY6_B0 V21 DDR2_DIMM_DQ_BY9_B4 G25

DDR2_DIMM_DQ_BY6_B0_N W23 DDR2_DIMM_DQ_BY9_B5 G26

DDR2_DIMM_DQ_BY6_B1 V22 DDR2_DIMM_DQ_BY9_B6 H23

DDR2_DIMM_DQ_BY6_B1_N W22 DDR2_DIMM_DQ_BY9_B7 H24

DDR2_DIMM_DQ_BY6_B2 W25 DDR2_DIMM_DQ_BY10_B0 F9

DDR2_DIMM_DQ_BY6_B2_N W21 DDR2_DIMM_DQ_BY10_B1 E9

DDR2_DIMM_DQ_BY6_B3 W26 DDR2_DIMM_DQ_BY10_B2 A6

DDR2_DIMM_DQ_BY6_B4 AA23 DDR2_DIMM_DQ_BY10_B3 A5

DDR2_DIMM_DQ_BY6_B5 AB23 DDR2_DIMM_DQ_BY10_B4 F8

DDR2_DIMM_DQ_BY6_B6 AD26 DDR2_DIMM_DQ_BY10_B5 G8

DDR2_DIMM_DQ_BY6_B6_N Y22 DDR2_DIMM_DQ_BY10_B6 B9

DDR2_DIMM_DQ_BY6_B7 AD25 DDR2_DIMM_DQ_BY10_B7 A9





FPGA #2 PinoutR


DDR2_DIMM_DQ_BY11_B0 A4 DDR2_DIMM_DQ_BY14_B7 AD22

DDR2_DIMM_DQ_BY11_B1 B4 DDR2_DIMM_DQ_BY15_B0 AA17

DDR2_DIMM_DQ_BY11_B2 C4 DDR2_DIMM_DQ_BY15_B0_N AB20

DDR2_DIMM_DQ_BY11_B3 D4 DDR2_DIMM_DQ_BY15_B1 Y17

DDR2_DIMM_DQ_BY11_B4 F7 DDR2_DIMM_DQ_BY15_B2 AB18

DDR2_DIMM_DQ_BY11_B5 G7 DDR2_DIMM_DQ_BY15_B3 AC18

DDR2_DIMM_DQ_BY11_B6 E6 DDR2_DIMM_DQ_BY15_B4 AF22

DDR2_DIMM_DQ_BY11_B7 E5 DDR2_DIMM_DQ_BY15_B5 AF21

DDR2_DIMM_DQ_BY12_B0 AA3 DDR2_DIMM_DQ_BY15_B6 AD21

DDR2_DIMM_DQ_BY12_B1 AA4 DDR2_DIMM_DQ_BY15_B7 AE21

DDR2_DIMM_DQ_BY12_B2 AA1 DDR2_DIMM_DQ_CB0_7_B0 P25

DDR2_DIMM_DQ_BY12_B3 AB1 DDR2_DIMM_DQ_CB0_7_B0_N N23

DDR2_DIMM_DQ_BY12_B4 AC1 DDR2_DIMM_DQ_CB0_7_B1 P24

DDR2_DIMM_DQ_BY12_B5 AC2 DDR2_DIMM_DQ_CB0_7_B1_N N22

DDR2_DIMM_DQ_BY12_B6 AB4 DDR2_DIMM_DQ_CB0_7_B2 T26

DDR2_DIMM_DQ_BY12_B6_N AB3 DDR2_DIMM_DQ_CB0_7_B3 U26

DDR2_DIMM_DQ_BY12_B7 AC4 DDR2_DIMM_DQ_CB0_7_B4 R24

DDR2_DIMM_DQ_BY13_B0 AC8 DDR2_DIMM_DQ_CB0_7_B4_N R26

DDR2_DIMM_DQ_BY13_B0_N AC7 DDR2_DIMM_DQ_CB0_7_B5 P23

DDR2_DIMM_DQ_BY13_B1 AD8 DDR2_DIMM_DQ_CB0_7_B5_N N21

DDR2_DIMM_DQ_BY13_B2 AA10 DDR2_DIMM_DQ_CB0_7_B6 P22

DDR2_DIMM_DQ_BY13_B3 Y10 DDR2_DIMM_DQ_CB0_7_B6_N N20

DDR2_DIMM_DQ_BY13_B4 AD6 DDR2_DIMM_DQ_CB0_7_B7 R23

DDR2_DIMM_DQ_BY13_B5 AE6 DDR2_DIMM_DQ_CB8_15_B0 U22

DDR2_DIMM_DQ_BY13_B6 AE9 DDR2_DIMM_DQ_CB8_15_B1 U21

DDR2_DIMM_DQ_BY13_B7 AF9 DDR2_DIMM_DQ_CB8_15_B2 U23

DDR2_DIMM_DQ_BY14_B0 AA26 DDR2_DIMM_DQ_CB8_15_B3 V23

DDR2_DIMM_DQ_BY14_B0_N Y26 DDR2_DIMM_DQ_CB8_15_B3_N U25

DDR2_DIMM_DQ_BY14_B1 AB26 DDR2_DIMM_DQ_CB8_15_B4 V26

DDR2_DIMM_DQ_BY14_B1_N Y25 DDR2_DIMM_DQ_CB8_15_B5 V25

DDR2_DIMM_DQ_BY14_B2 AB25 DDR2_DIMM_DQ_CB8_15_B6 T21

DDR2_DIMM_DQ_BY14_B2_N V20 DDR2_DIMM_DQ_CB8_15_B7 T20

DDR2_DIMM_DQ_BY14_B3 AB24 DDR2_DIMM_RAS_N E1

DDR2_DIMM_DQ_BY14_B3_N W20 DDR2_DIMM_READ_VALID_FAST A3

DDR2_DIMM_DQ_BY14_B4 AC24 DDR2_DIMM_READ_VALID_FAST B3

DDR2_DIMM_DQ_BY14_B5 AC23 DDR2_DIMM_READ_VALID_SLOW C5

DDR2_DIMM_DQ_BY14_B6 AD23 DDR2_DIMM_READ_VALID_SLOW E10







DDR2_DIMM_RESET_N L1 DDR2_DIMM_SCL A17

DDR2_DIMM_SA0 B10 DDR2_DIMM_SDA B17

DDR2_DIMM_SA1 A10 DDR2_DIMM_WE_N M5

DDR2_DIMM_SA2 B12

DDR2 Component Memory Interface

DDR2_A1 E13 DDR2_DM_BY3 M1

DDR2_A2 D11 DDR2_DQS_BY0_L_N A7

DDR2_A3 C11 DDR2_DQS_BY0_L_P A8

DDR2_A4 E14 DDR2_DQS_BY1_N K25

DDR2_A5 D15 DDR2_DQS_BY1_P K26

DDR2_A6 F15 DDR2_DQS_BY2_N N19

DDR2_A7 F16 DDR2_DQS_BY2_P M19

DDR2_A8 F11 DDR2_DQS_BY3_N T1

DDR2_A9 F12 DDR2_DQS_BY3_P U1

DDR2_A10 D16 DDR2_DQ_BY0_B0 D9

DDR2_A11 F13 DDR2_DQ_BY0_B1 C8

DDR2_A12 F14 DDR2_DQ_BY0_B2 C10

DDR2_A13 C16 DDR2_DQ_BY0_B3 D10

DDR2_BA0 AD13 DDR2_DQ_BY1_B0 L19

DDR2_BA1 AC13 DDR2_DQ_BY1_B1 K20

DDR2_BY0_CS0_N G19 DDR2_DQ_BY1_B2 L21

DDR2_BY0_CS1_N F19 DDR2_DQ_BY1_B3 L20

DDR2_BY1_CS_N E23 DDR2_DQ_BY1_B4 K24

DDR2_BY2_3_CS_N E22 DDR2_DQ_BY1_B5 K23

DDR2_CAS_N AA11 DDR2_DQ_BY1_B6 L24

DDR2_CK0_N AB14 DDR2_DQ_BY1_B7 L23

DDR2_CK0_P AA14 DDR2_DQ_BY2_B0 M25

DDR2_CK1_N AC11 DDR2_DQ_BY2_B1 M24

DDR2_CK1_P AC12 DDR2_DQ_BY2_B2 M21

DDR2_CK2_N AA15 DDR2_DQ_BY2_B3 M20

DDR2_CK2_P AA16 DDR2_DQ_BY2_B4 M23

DDR2_CK3_N AD14 DDR2_DQ_BY2_B5 M22

DDR2_CK3_P AC14 DDR2_DQ_BY2_B6 N25

DDR2_CKE AC16 DDR2_DQ_BY2_B7 N24

DDR2_DM_BY0 J2 DDR2_DQ_BY3_B0 R8

DDR2_DM_BY1 K3 DDR2_DQ_BY3_B1 R7

DDR2_DM_BY2 M2 DDR2_DQ_BY3_B2 V4





FPGA #2 PinoutR

DDR2 Component Memory Interface (cont’d)

DDR2_DQ_BY3_B3 U4 DDR2_RAS_N AA12

DDR2_DQ_BY3_B4 T8 DDR2_READ_VALID_LOOPBACK D8

DDR2_DQ_BY3_B5 U7 DDR2_READ_VALID_LOOPBACK F10

DDR2_DQ_BY3_B6 U6 DDR2_READ_VALID_LOOPBACK_BANK9

J21

DDR2_DQ_BY3_B7 U5 DDR2_READ_VALID_LOOPBACK_BANK9

L26

DDR2_ODT D14 DDR2_WE_N AC15


DDR2_CK0_N AB14 DDR2_CKE AC16

DDR2_CK0_P AA14 DIRECT_CLK_TO_FPGA2_N A15

DDR2_CK1_N AC11 DIRECT_CLK_TO_FPGA2_P A16

DDR2_CK1_P AC12 EXT_CLK_TO_FPGA2_N B14

DDR2_CK2_N AA15 EXT_CLK_TO_FPGA2_P B15

DDR2_CK2_P AA16 SYNTH_CLK_TO_FPGA2_N C14

DDR2_CK3_N AD14 SYNTH_CLK_TO_FPGA2_P C15

DDR2_CK3_P AC14


FPGA2_FPGA4_MII_TX_CLK AE14 FPGA4_FPGA2_MII_TX_CLK AF12

FPGA2_FPGA4_MII_TX_DATA_B0 AD10 FPGA4_FPGA2_MII_TX_DATA AB10

FPGA2_FPGA4_MII_TX_DATA_B1 AD17 FPGA4_FPGA2_MII_TX_DATA AB17

FPGA2_FPGA4_MII_TX_DATA_B2 AD16 FPGA4_FPGA2_MII_TX_DATA AC17

FPGA2_FPGA4_MII_TX_DATA_B3 AD12 FPGA4_FPGA2_MII_TX_DATA AF11


FPGA2_FPGA4_MII_TX_ERR AE10 FPGA4_FPGA2_MII_TX_ERR AC10

FPGA2_FPGA4_MII_TX_SPARE AD11 FPGA4_FPGA2_MII_TX_SPARE AF10


FPGA_CNFG_M0 W15 FPGA_PROGB H15

FPGA_CNFG_M1 Y15 FPGA_TCK W12

FPGA_CNFG_M2 W14 FPGA_TDO Y13

FPGA_DIN G12 FPGA_TMS Y11

FPGA_DONE H14 FPGA_VBATT Y16

FPGA_INIT G15 SYS_RESET_IN_N K1


FPGA2_TEST_HDR_BY0_B0 A12 FPGA2_TEST_HDR_BY0_B2 B13

FPGA2_TEST_HDR_BY0_B1 A11









QDR II Memory Interface

QDR2_BW_BY0_N L21 QDR2_D_BY1_B3 M23

QDR2_BW_BY1_N L20 QDR2_D_BY1_B4 M22

QDR2_BW_BY2_N T20 QDR2_D_BY1_B5 N25

QDR2_BW_BY3_N Y25 QDR2_D_BY1_B6 N24

QDR2_BW_BY4_N K5 QDR2_D_BY1_B7 N23

QDR2_BW_BY5_N K4 QDR2_D_BY1_B8 N22

QDR2_BW_BY6_N V1 QDR2_D_BY2_B0 U20

QDR2_BW_BY7_N Y2 QDR2_D_BY2_B1 T19

QDR2_CK_BY0_3_N AE18 QDR2_D_BY2_B2 V26

QDR2_CK_BY0_3_P AF18 QDR2_D_BY2_B3 V25

QDR2_CK_BY4_7_N AD21 QDR2_D_BY2_B4 V21

QDR2_CK_BY4_7_P AE21 QDR2_D_BY2_B5 V22

QDR2_CQ_BY0_3_N T23 QDR2_D_BY2_B6 W25

QDR2_CQ_BY0_3_P T24 QDR2_D_BY2_B7 W26

QDR2_CQ_BY4_7_N T1 QDR2_D_BY2_B8 W21

QDR2_CQ_BY4_7_P U1 QDR2_D_BY3_B0 Y22

QDR2_DLL_OFF_N AF19 QDR2_D_BY3_B1 AC22

QDR2_D_BY0_B0 J21 QDR2_D_BY3_B2 AB22

QDR2_D_BY0_B1 J20 QDR2_D_BY3_B3 AB23

QDR2_D_BY0_B2 J23 QDR2_D_BY3_B4 AA23

QDR2_D_BY0_B3 J22 QDR2_D_BY3_B5 AD22

QDR2_D_BY0_B4 K22 QDR2_D_BY3_B6 AD23

QDR2_D_BY0_B5 K21 QDR2_D_BY3_B7 AC23

QDR2_D_BY0_B6 J26 QDR2_D_BY3_B8 AC24

QDR2_D_BY0_B7 L19 QDR2_D_BY4_B0 J7

QDR2_D_BY0_B8 K20 QDR2_D_BY4_B1 J6

QDR2_D_BY1_B0 L26 QDR2_D_BY4_B2 J5

QDR2_D_BY1_B1 M21 QDR2_D_BY4_B3 J4

QDR2_D_BY1_B2 M20 QDR2_D_BY4_B4 K7



FPGA #3 PinoutR

QDR II Memory Interface (cont’d)

QDR2_D_BY4_B5 K6 QDR2_DLL_OFF_N AF19

QDR2_D_BY4_B6 J2 QDR2_K_BY0_3_N R23

QDR2_D_BY4_B7 L7 QDR2_K_BY0_3_P R24

QDR2_D_BY4_B8 L6 QDR2_K_BY4_7_N R1

QDR2_D_BY5_B0 M4 QDR2_K_BY4_7_P R2

QDR2_D_BY5_B1 M6 QDR2_Q_BY0_B0 K23

QDR2_D_BY5_B2 M5 QDR2_Q_BY0_B1 K26

QDR2_D_BY5_B3 N3 QDR2_Q_BY0_B2 K25

QDR2_D_BY5_B4 N2 QDR2_Q_BY0_B3 M19

QDR2_D_BY5_B5 N5 QDR2_Q_BY0_B4 N19

QDR2_D_BY5_B6 N4 QDR2_Q_BY0_B5 L24

QDR2_D_BY5_B7 P3 QDR2_Q_BY0_B6 L23

QDR2_D_BY5_B8 P2 QDR2_Q_BY0_B7 M25

QDR2_D_BY6_B0 T8 QDR2_Q_BY0_B8 M24

QDR2_D_BY6_B1 U7 QDR2_Q_BY1_B0 N21

QDR2_D_BY6_B2 U6 QDR2_Q_BY1_B1 N20

QDR2_D_BY6_B3 U5 QDR2_Q_BY1_B2 P25

QDR2_D_BY6_B4 W2 QDR2_Q_BY1_B3 P24


QDR2_D_BY6_B6 V6 QDR2_Q_BY1_B5 P22

QDR2_D_BY6_B7 V5 QDR2_Q_BY1_B6 R26


QDR2_D_BY7_B0 AB3 QDR2_Q_BY1_B8 P19

QDR2_D_BY7_B1 AC5 QDR2_Q_BY2_B0 R20

QDR2_D_BY7_B2 AB5 QDR2_Q_BY2_B1 R19

QDR2_D_BY7_B3 AC2 QDR2_Q_BY2_B2 T26

QDR2_D_BY7_B4 AC1 QDR2_Q_BY2_B3 U26

QDR2_D_BY7_B5 AF3 QDR2_Q_BY2_B4 U23

QDR2_D_BY7_B6 AE3 QDR2_Q_BY2_B5 V23

QDR2_D_BY7_B7 AD2 QDR2_Q_BY2_B6 U25

QDR2_D_BY7_B8 AD1 QDR2_Q_BY2_B7 U22







QDR2_Q_BY2_B8 U21 QDR2_Q_BY6_B3 T3

QDR2_Q_BY3_B0 AB25 QDR2_Q_BY6_B4 T7

QDR2_Q_BY3_B1 AA24 QDR2_Q_BY6_B5 T6

QDR2_Q_BY3_B2 Y24 QDR2_Q_BY6_B6 U3

QDR2_Q_BY3_B3 AC25 QDR2_Q_BY6_B7 V4

QDR2_Q_BY3_B4 AC26 QDR2_Q_BY6_B8 U4

QDR2_Q_BY3_B5 AB26 QDR2_Q_BY7_B0 AA3

QDR2_Q_BY3_B6 AA26 QDR2_Q_BY7_B1 Y4

QDR2_Q_BY3_B7 AD25 QDR2_Q_BY7_B2 Y3

QDR2_Q_BY3_B8 AD26 QDR2_Q_BY7_B3 Y6

QDR2_Q_BY4_B0 K2 QDR2_Q_BY7_B4 Y5

QDR2_Q_BY4_B1 L4 QDR2_Q_BY7_B5 AB1

QDR2_Q_BY4_B2 L3 QDR2_Q_BY7_B6 AA1

QDR2_Q_BY4_B3 M8 QDR2_Q_BY7_B7 AC4

QDR2_Q_BY4_B4 L8 QDR2_Q_BY7_B8 AB4

QDR2_Q_BY4_B5 L1 QDR2_R_N AF5

QDR2_Q_BY4_B6 K1 QDR2_READ_VALID_FAST_LOOPBACK AD19

QDR2_Q_BY4_B7 M2 QDR2_READ_VALID_FAST_LOOPBACK AB21

QDR2_Q_BY4_B8 M1 QDR2_READ_VALID_LOOPBACK AE4

QDR2_Q_BY5_B0 N7 QDR2_READ_VALID_LOOPBACK_BANK7 V20

QDR2_Q_BY5_B1 M7 QDR2_READ_VALID_LOOPBACK_BANK7 W20

QDR2_Q_BY5_B2 P5 QDR2_READ_VALID_LOOPBACK AF4

QDR2_Q_BY5_B3 P4 QDR2_READ_VALID_SLOW_LOOPBACK Y17

QDR2_Q_BY5_B4 P8 QDR2_READ_VALID_SLOW_LOOPBACK AA20

QDR2_Q_BY5_B5 N8 QDR2_SA0 AD4

QDR2_Q_BY5_B6 R4 QDR2_SA1 AC6

QDR2_Q_BY5_B7 P7 QDR2_SA2 AB6

QDR2_Q_BY5_B8 P6 QDR2_SA3 AF8

QDR2_Q_BY6_B0 R8 QDR2_SA4 AF7

QDR2_Q_BY6_B1 R7 QDR2_SA5 AA8

QDR2_Q_BY6_B2 T4 QDR2_SA6 Y8





FPGA #3 PinoutR


QDR2_SA7 Y10 QDR2_SA13 AD6

QDR2_SA8 AA10 QDR2_SA14 AF9

QDR2_SA9 AC7 QDR2_SA15 AE9

QDR2_SA10 AC9 QDR2_SA16 AD8

QDR2_SA11 AB9 QDR2_SA17 AC8

QDR2_SA12 AE6 QDR2_W_N AF6

FCRAM II Memory Interface

FCR2_A0 A22 FCR2_DQ_BY0_B2 D9

FCR2_A1 A21 FCR2_DQ_BY0_B3 C8

FCR2_A2 D24 FCR2_DQ_BY0_B4 A8

FCR2_A3 C24 FCR2_DQ_BY0_B5 A7

FCR2_A4 G19 FCR2_DQ_BY0_B6 F10

FCR2_A5 F19 FCR2_DQ_BY0_B7 E10

FCR2_A6 E23 FCR2_DQ_BY0_B8 A6

FCR2_A7 E22 FCR2_DQ_BY1_B0 G10

FCR2_A8 F20 FCR2_DQ_BY1_B1 G9

FCR2_A9 E20 FCR2_DQ_BY1_B2 F8

FCR2_A10 D23 FCR2_DQ_BY1_B3 G8

FCR2_A11 C23 FCR2_DQ_BY1_B4 B7

FCR2_A12 H20 FCR2_DQ_BY1_B5 C7

FCR2_A13 G20 FCR2_DQ_BY1_B6 A9

FCR2_BA0 H22 FCR2_DQ_BY1_B7 B9

FCR2_BA1 H21 FCR2_DQ_BY1_B8 A3

FCR2_CK0_N F23 FCR2_DQ_BY2_B0 C17

FCR2_CK0_P F24 FCR2_DQ_BY2_B1 D17

FCR2_CK1_N D25 FCR2_DQ_BY2_B2 C20

FCR2_CK1_P D26 FCR2_DQ_BY2_B3 B20

FCR2_CS0_N F26 FCR2_DQ_BY2_B4 B18

FCR2_CS1_N E26 FCR2_DQ_BY2_B5 A18

FCR2_DQ_BY0_B0 D10 FCR2_DQ_BY2_B6 E17

FCR2_DQ_BY0_B1 C10 FCR2_DQ_BY2_B7 F17






FCRAM II Memory Interface (cont’d)

FCR2_DQ_BY2_B8 C21 FCR2_DS_BY0_1 E9

FCR2_DQ_BY3_B0 G18 FCR2_DS_BY2_3 C19

FCR2_DQ_BY3_B1 G17 FCR2_FN H24

FCR2_DQ_BY3_B2 B24 FCR2_PD_N H23

FCR2_DQ_BY3_B3 B23 FCR2_QS_BY0_1 B6

FCR2_DQ_BY3_B4 F18 FCR2_QS_BY2_3 A24

FCR2_DQ_BY3_B5 E18 FCR2_READ_VALID_LOOPBACK C4

FCR2_DQ_BY3_B6 A20 FCR2_READ_VALID_LOOPBACK_BANK5 H25

FCR2_DQ_BY3_B7 A19 FCR2_READ_VALID_LOOPBACK_BANK5 H26

FCR2_DQ_BY3_B8 D22


SYNTH_CLK_TO_FPGA3_N C14 DIRECT_CLK_TO_FPGA3_P A16

SYNTH_CLK_TO_FPGA3_P C15 EXT_CLK_TO_FPGA3_N B14

DIRECT_CLK_TO_FPGA3_N A15 EXT_CLK_TO_FPGA3_P B15


FPGA4_FPGA3_MII_TX_CLK AF12 FPGA3_FPGA4_MII_TX_CLK AE14



FPGA4_FPGA3_MII_TX_DATA_B2 AC17 FPGA3_FPGA4_MII_TX_DATA_B2 AD16

FPGA4_FPGA3_MII_TX_DATA_B3 AF11 FPGA3_FPGA4_MII_TX_DATA_B3 AD12


FPGA4_FPGA3_MII_TX_ERR AC10 FPGA3_FPGA4_MII_TX_ERR AE10

FPGA4_FPGA3_MII_TX_SPARE AF10 FPGA3_FPGA4_MII_TX_SPARE AD11


FPGA_CCLK G14 FPGA_PROGB H15

FPGA_CNFG_M0 W15 FPGA_TCK W12

FPGA_CNFG_M1 Y15 FPGA_TDO Y13

FPGA_CNFG_M2 W14 FPGA_TMS Y11

FPGA_DIN G12 FPGA_VBATT Y16

FPGA_DONE H14 SYS_RESET_IN_N K3

FPGA_INIT G15





FPGA #3 PinoutR


FPGA3_TEST_HDR_BY0_B0 A12 FPGA3_TEST_HDR_BY0_B4 A10

FPGA3_TEST_HDR_BY0_B1 A11 FPGA3_TEST_HDR_BY0_B5 B10

FPGA3_TEST_HDR_BY0_B2 B13 FPGA3_TEST_HDR_BY0_B6 B17

FPGA3_TEST_HDR_BY0_B3 B12 FPGA3_TEST_HDR_BY0_B7 A17

Clock Synthesizer Control Signals

FPGA1_SYNTH_S_CLK F14 FPGA3_SYNTH_S_CLK D15

FPGA1_SYNTH_S_DATA F13 FPGA3_SYNTH_S_DATA E14

FPGA1_SYNTH_S_LOAD F12 FPGA3_SYNTH_S_LOAD C11

FPGA2_SYNTH_S_CLK F16 FPGA4_SYNTH_S_CLK D16

FPGA2_SYNTH_S_DATA F15 FPGA4_SYNTH_S_DATA C16

CLOCK_SYNTH_MASTER_RESET D12 FPGA4_SYNTH_S_LOAD E13

FPGA2_SYNTH_S_LOAD D14









RLDRAM II Memory Interface

RLD2_A0 A22 RLD2_QVLD_BY2_3 B21

RLD2_A1 A21 RLD2_WE_N G1

RLD2_A2 D24 RLD2_READ_VALID C4

RLD2_A3 C24 RLD2_READ_VALID D4

RLD2_A4 G19 RLD2_CK_BY0_1_P E3

RLD2_A5 F19 RLD2_CK_BY0_1_N E2

RLD2_A6 E23 RLD2_DK_BY0_1_P D2

RLD2_A7 E22 RLD2_DK_BY0_1_N D1

RLD2_A8 F20 RLD2_CK_BY2_3_P F24

RLD2_A9 E20 RLD2_CK_BY2_3_N F23

RLD2_A10 D23 RLD2_DK_BY2_3_P D26

RLD2_A11 C23 RLD2_DK_BY2_3_N D25

RLD2_A12 H20 RLD2_QK_BY0_P B6

RLD2_A13 G20 RLD2_QK_BY0_N C6

RLD2_A14 F26 RLD2_QK_BY1_P G10

RLD2_A15 E26 RLD2_QK_BY1_N G9

RLD2_A16 H24 RLD2_QK_BY2_P A24

RLD2_A17 H23 RLD2_QK_BY2_N A23

RLD2_A18 G26 RLD2_QK_BY3_P G18

RLD2_A19 G25 RLD2_QK_BY3_N G17

RLD2_BA0 H22 RLD2_DQ_BY0_B0 D10

RLD2_BA1 H21 RLD2_DQ_BY0_B1 C10

RLD2_BA2 E25 RLD2_DQ_BY0_B2 D9

RLD2_CS_BY0_1_N H5 RLD2_DQ_BY0_B3 C8

RLD2_CS_BY2_3_N G2 RLD2_DQ_BY0_B4 A8

RLD2_DM_BY0_1_N H4 RLD2_DQ_BY0_B5 A7

RLD2_DM_BY2_3_N H3 RLD2_DQ_BY0_B6 F10

RLD2_REF_N H6 RLD2_DQ_BY0_B7 E10

RLD2_QVLD_BY0_1 A5 RLD2_DQ_BY0_B8 A6



FPGA #4 PinoutR

RLDRAM II Memory Interface (cont’d)

RLD2_DQ_BY1_B0 E9 RLD2_DQ_BY2_B6 E17

RLD2_DQ_BY1_B1 F9 RLD2_DQ_BY2_B7 F17

RLD2_DQ_BY1_B2 F8 RLD2_DQ_BY2_B8 C21

RLD2_DQ_BY1_B3 G8 RLD2_DQ_BY3_B0 C19

RLD2_DQ_BY1_B4 B7 RLD2_DQ_BY3_B1 D18

RLD2_DQ_BY1_B5 C7 RLD2_DQ_BY3_B2 B24

RLD2_DQ_BY1_B6 A9 RLD2_DQ_BY3_B3 B23

RLD2_DQ_BY1_B7 B9 RLD2_DQ_BY3_B4 F18

RLD2_DQ_BY1_B8 A3 RLD2_DQ_BY3_B5 E18

RLD2_DQ_BY2_B0 C17 RLD2_DQ_BY3_B6 A20

RLD2_DQ_BY2_B1 D17 RLD2_DQ_BY3_B7 A19

RLD2_DQ_BY2_B2 C20 RLD2_DQ_BY3_B8 D22

RLD2_DQ_BY2_B3 B20 RLD2_READ_VALID_LOOPBACK_BANK5 HD25

RLD2_DQ_BY2_B4 B18 RLD2_READ_VALID_LOOPBACK_BANK5 HD26

RLD2_DQ_BY2_B5 A18

Z-DOK+ Connector Interface

DBG_LED0 M24 CPLD_6 J26

DBG_LED1 L26 CPLD_7 J25

DBG_LED2 M26 CPLD_8 L19

DBG_LED3 M21 CPLD_9 K20



CPLD_0 J21 CPLD_12 K24




CPLD_CLK T24 CPLD_16 M19

CPLD_DGATE_EN U23 CPLD_17 N19

CPLD_GSR V23 LVDS_TX0 J7

CPLD_4 K22 LVDS_TX1 J6

CPLD_5 K21 LVDS_TX2 J5






LVDS_TX3 J4 TXPCLKN R5

LVDS_TX4 K7 SFP0_TXP R8

LVDS_TX5 K6 SFP0_TXN R7

LVDS_TX6 J2 SFP1_TXP T4

LVDS_TX7 J1 SFP1_TXN T3

LVDS_TX8 L7 SFP2_TXP T7

LVDS_TX9 L6 SFP2_TXN T6

LVDS_TX10 K5 XEN_TX0P V4

LVDS_TX11 K4 XEN_TX0N U4

LVDS_TX12 K3 XEN_TX1P V2

LVDS_TX13 K2 XEN_TX1N V1

LVDS_TX14 L4 XEN_TX2P T8

LVDS_TX15] L3 XEN_TX2N U7

LVDS_TX16 M8 XEN_TX3P U6

LVDS_TX17 L8 XEN_TX3N U5

LVDS_TX18 L1 LVDS_RX0 W2

LVDS_TX19 K1 LVDS_RX1 W1

LVDS_TX20 M2 LVDS_RX2 V6


LVDS_TX22 M4 LVDS_RX4 W7


LVDS_TX24 N7 LVDS_RX6 W6

LVDS_TX25 M7 LVDS_RX7 W5

LVDS_TX26 P5 LVDS_RX8 Y2


LVDS_TX28 P8 LVDS_RX10 AA4

LVDS_TX29 N8 LVDS_RX11 AA3



TXPICLKN R2 LVDS_RX14 AB1

TXPICLKP R1 LVDS_RX15 AA1

TXPCLKP R6 LVDS_RX16 AC4





FPGA #4 PinoutR

Z-DOK+ Connector Interface (cont’d)

LVDS_RX17 AB4 LVDS_RX17 AB4

LVDS_RX18 AC5 LVDS_RX18 AC5

LVDS_RX19 AB5 LVDS_RX19 AB5

SFP1_TXN T3 LVDS_RX20 AC2

SFP2_TXP T7 LVDS_RX21 AC1

SFP2_TXN T6 LVDS_RX22 AF3

XEN_TX0P V4 LVDS_RX23 AE3

XEN_TX0N U4 LVDS_RX24 AF4

XEN_TX1P V2 LVDS_RX25 AE4

XEN_TX1N V1 LVDS_RX26 AD3

XEN_TX2P T8 LVDS_RX27 AC3

XEN_TX2N U7 LVDS_RX28 AF6

XEN_TX3P U6 LVDS_RX29 AF5

XEN_TX3N U5 LVDS_RX30 AA9

LVDS_RX0 W2 LVDS_RX31 Y9

LVDS_RX1 W1 RXP0CLKP_C2 Y4

LVDS_RX2 V6 RXP0CLKN_C2 Y3

LVDS_RX3 V5 LVDS_CLKEXT_P AD2

LVDS_RX4 W7 LVDS_CLKEXT_N AD1

LVDS_RX5 V7 LVDS_CLKEXT_P AC6

LVDS_RX6 W6 LVDS_CLKEXT_N AB6

LVDS_RX7 W5 SFP0_RXP AF8

LVDS_RX8 Y2 SFP0_RXN AF7

LVDS_RX9 Y1 SFP1_RXP AA8

LVDS_RX10 AA4 SFP1_RXN Y8

LVDS_RX11 AA3 SFP2_RXP Y10

LVDS_RX12 Y6 SFP2_RXN AA10

LVDS_RX13 Y5 SMA_RXP AC7

LVDS_RX14 AB1 SMA_RXN AB7

LVDS_RX15 AA1 XEN_RX0P AC9

LVDS_RX16 AC4 XEN_RX0N AB9






Z-DOK+ Connector Interface (cont’d)

XEN_RX1P AE6 XEN_RX2N AE9

XEN_RX1N AD6 XEN_RX3P AD8

XEN_RX2P AF9 XEN_RX3N AC8


SYNTH_CLK_TO_FPGA4_N C14 EXT_CLK_TO_FPGA4_P B15

SYNTH_CLK_TO_FPGA4_P C15 DIRECT_CLK_TO_FPGA4_N A15

EXT_CLK_TO_FPGA4_N B14 DIRECT_CLK_TO_FPGA4_P A16


FPGA4_FPGA1_MII_TX_CLK F14 FPGA4_FPGA3_MII_TX_SPARE AD11

FPGA4_FPGA1_MII_TX_DATA0 F11 FPGA1_FPGA4_MII_TX_CLK D15

FPGA4_FPGA1_MII_TX_DATA1 F16 FPGA1_FPGA4_MII_TX_DATA0 D11

FPGA4_FPGA1_MII_TX_DATA2 F15 FPGA1_FPGA4_MII_TX_DATA1 D16

FPGA4_FPGA1_MII_TX_DATA3 D14 FPGA1_FPGA4_MII_TX_DATA2 C16

FPGA4_FPGA1_MII_TX_EN F13 FPGA1_FPGA4_MII_TX_DATA3 E13

FPGA4_FPGA1_MII_TX_ERR F12 FPGA1_FPGA4_MII_TX_EN E14

FPGA4_FPGA1_MII_TX_SPARE D13 FPGA1_FPGA4_MII_TX_ERR C11

FPGA4_FPGA2_MII_TX_CLK AA14 FPGA1_FPGA4_MII_TX_SPARE D12

FPGA4_FPGA2_MII_TX_DATA0 AC11 FPGA2_FPGA4_MII_TX_CLK AC14

FPGA4_FPGA2_MII_TX_DATA1 AA16 FPGA2_FPGA4_MII_TX_DATA0 AA11

FPGA4_FPGA2_MII_TX_DATA2 AA15 FPGA2_FPGA4_MII_TX_DATA1 AC16

FPGA4_FPGA2_MII_TX_DATA3 AB13 FPGA2_FPGA4_MII_TX_DATA2 AC15

FPGA4_FPGA2_MII_TX_EN AB14 FPGA2_FPGA4_MII_TX_DATA3 AC13

FPGA4_FPGA2_MII_TX_ERR AC12 FPGA2_FPGA4_MII_TX_EN AD14

FPGA4_FPGA2_MII_TX_SPARE AA13 FPGA2_FPGA4_MII_TX_ERR AA12

FPGA4_FPGA3_MII_TX_CLK AE14 FPGA2_FPGA4_MII_TX_SPARE AD13

FPGA4_FPGA3_MII_TX_DATA0 AD10 FPGA3_FPGA4_MII_TX_CLK AF12

FPGA4_FPGA3_MII_TX_DATA1 AD17 FPGA3_FPGA4_MII_TX_DATA0 AB10

FPGA4_FPGA3_MII_TX_DATA2 AD16 FPGA3_FPGA4_MII_TX_DATA1 AB17

FPGA4_FPGA3_MII_TX_DATA3 AD12 FPGA3_FPGA4_MII_TX_DATA2 AC17

FPGA4_FPGA3_MII_TX_EN AE13 FPGA3_FPGA4_MII_TX_DATA3 AF11

FPGA4_FPGA3_MII_TX_ERR AE10 FPGA3_FPGA4_MII_TX_EN AE12





FPGA #4 PinoutR

FPGA #4 MII Link Interface (cont’d)

FPGA3_FPGA4_MII_TX_ERR AC10 FPGA3_FPGA4_MII_TX_SPARE AF10


FPGA_CNFG_M0 W15 FPGA_PROGB H15

FPGA_CNFG_M1 Y15 FPGA_TCK W12

FPGA_CNFG_M2 W14 FPGA_TDO Y13

FPGA_DIN G12 FPGA_TMS Y11

FPGA_DONE H14 FPGA_VBATT Y16

FPGA_INIT G15 SYS_RESET_IN_N N3


FPGA4_TEST_HDR_B0 A12 FPGA4_TEST_HDR_B4 A10


FPGA4_TEST_HDR_B2 B13 FPGA4_TEST_HDR_B6 B17

FPGA4_TEST_HDR_B3 B12 FPGA4_TEST_HDR_B7 A17

System ACE Interface

SYSACE_CTRL0 W21 SYSACE_MPA6 W22

SYSACE_CTRL1 W26 SYSACE_MPD0 AB26

SYSACE_CTRL2 W25 SYSACE_MPD1 AC25

SYSACE_CTRL3 V22 SYSACE_MPD2 Y24

SYSACE_CTRL4 V21 SYSACE_MPD3 AA24

SYSACE_MPA0 Y26 SYSACE_MPD4 AB21

SYSACE_MPA1 Y25 SYSACE_MPD5 AC21

SYSACE_MPA2 V20 SYSACE_MPD6 AB25

SYSACE_MPA3 W20 SYSACE_MPD7 AB24

SYSACE_MPA4 W24 SYSACE_CLK AC26

SYSACE_MPA5 W23 FPGA_DONE AA26

LCD Signals

LCD_DB0 AF19 LCD_DB5 AE23

LCD_DB1 AF20 LCD_DB6 Y20

LCD_DB2 Y19 LCD_DB7 Y21

LCD_DB3 W19 LCD_RS AA18

LCD_DB4 AF23 LCD_R_WB Y18






LCD Signals (cont’d)

LCD_E AF24 LCD_CSB AD20

LCD_BL_ON AE24 LCD_RSTB AD20

RS-232 Signals

RS232_CTS AC23 RS232_TX AB20

RS232_RTS AC24 RS232_RX AC20

Voltage Margin Control Signals

VMARGIN_UP_VCC1V2_N N21 VMARGIN_DN_3V3_N R20

VMARGIN_DN_VCC1V2_N N20 I2C_CLK T26

VMARGIN_UP_SSTL18_N P25 I2C_DATA U26

VMARGIN_DN_SSTL18_N P24 CPLD_DGATE_EN U23

VMARGIN_UP_SSTL2_N P23 CPLD_GSR V23

VMARGIN_DN_SSTL2_N P22 ENABLE0 U22

VMARGIN_UP_HSTL_N R26 ENABLE1 U21

VMARGIN_DN_HSTL_N R25 ENABLE2 T21

VMARGIN_UP_VCC2V5_N P20 SI_SEL1 T20

VMARGIN_DN_VCC2V5_N P19 MODE” U20

LOOP_FILTER_UP R24 SEL0 T19

LOOP_FILTER_DOWN R23 LOAD V26

VMARGIN_UP_3V3_N T23 SCLK V25





R

Appendix B

LCD Interface

This appendix describes the LCD interface for the Virtex-4 ML461 Development Board.

GeneralThe Virtex-4 ML461 Development Board board has a full graphical LCD display. This display has been chosen because of its possible use in embedded systems. A character-type display also can be connected because the graphical LCD has the same interface as the character-type LCD panels.

A hardware character generator must be designed in order to display characters on the screen.

Display Hardware DesignThe FPGA (I/O functioning at 2.5V) is connected to the graphic LCD display through a set of voltage-level converting devices. These switches translate the 2.5 I/O voltage to a 3.3V voltage for the LCD display.

A graphics-based LCD panel from DisplayTech (64128EFCBC-XLP) is used on the Virtex-4 ML461 Development Board. The control for this LCD panel is based on the KS0713 controller from Samsung. The KS0713 is a 65-column, 132-segment driver-controller device for graphic dot matrix LCD display systems. The chip accepts serial or parallel display data. The 8-bit parallel interface is compatible with most LCD panel manufacturers. The serial connection mode is write only.

Extra features added to the interface in addition to the normal parallel signals are:

• Intel or Motorola compatible interface

• External reset of the chip

• External chip select

The interface also contains the following built-in options for the display and controller:

• On-chip oscillator circuitry

• On-chip voltage converter (x2, x3, x4, and x5)

• A 64-step electronic contrast control function



Appendix B: LCD InterfaceR

Table B-1 summarizes the controller specifications.

The on-chip RAM size is 65x132 = 8580 bits.

Hardware Schematic Diagram

Table B-1: Display Controller Specifications

Parameter Specification

Supply voltage 2.4V to 3.6V (VDD)

LCD driving voltage 4V to 15V (VLCD = V0 - VDD)

Power consumption 70 μA typical (VDD = 3V, x4 boost, V0 = 11V, internal supply = ON)

Sleep mode 2 μA

Standby mode 10 μA

Figure B-1: Display Schematic Diagram

3.3V

LCD_D[7:0]

ENA, R/W, RSEL, CS1B

LCD-BUS

DIP1_4

3.3V

Rst GndVcc- +LED

MI

3.3V

3.3V

68xx

68xx

Default = 68xxDefault = Resistor to Gnd

Backlight ON/OFF

IC19

IC22

IC23

Sam

Arr

ay

ug079_b_01_081005



Hardware Schematic DiagramR

Peripheral Device KS0713

Figure B-2 shows only the signals of interest for the LCD controller. Download the data sheet from the Samsung web pages for a complete signal listing.

Figure B-2: KS0713 Block Diagram

V/CCircuit

V/RCircuit

V/FCircuit

PaggeAddressCircuit

LineAddressCircuit

Display Data RAM65 x132 = 8580 Bits

132 SegmentDriver

Circuits

33 CommonDriver

Circuits

33 CommonDriver

Circuits

Column AddressCircuit

Segment Controller Common Controller

I/OBuffer

KS0713 Samsung

VDD

VSS

CS

1B

RS

E_R

D

RW

_WR

PS

RE

SE

TB

MI

DB

7 (SID

)

MPU Interface (Parallel & Serial)

Bus Holder

Oscillator

DisplayTiming

GeneratorCircuit

Status Register

Instruction Decoder

Instruction Register

DB

6 (SC

LK)

DB

5

DB

4

DB

3

DB

2

DB

1

DB

0

ug079_b_02_081005




Figure B-3: 64128EFCBC-XLP Block Diagram

Con

trol

ler

KS

0713

LCD Panel

LED Backlight

C64

S128

Jumper J3 Parallel, Serial Selection. Default is parallel.

ug079_b_03_081005

1 Vss2 Vdd3 MI4 DB75 DB66 DB57 DB48 DB39 DB210 DB111 DB012 E13 R/W14 RS15 RST16 CS1B17 LED+18 LED-

Figure B-4: 64128EFCBC-XLP Dimensions

128 x 64 DOTS

56.00

2.50

2.54

69.00

74.00

ug079_b_04_081005

36.7

0

41.7

0

1 2

30 1

17 18

LED

J1J2

8.00 MaxDimensions in mm




Controller – Operation

The pixels for the LCD panel are stored in the controller data RAM. This RAM is a 65-row by 132-column array. Each display pixel is represented by a single bit in the RAM array.

The interface to the RAM array goes through the 8-bit (DB0 – DB7) LCD interface. Therefore, the 65-bit rows are split into eight pages of eight lines. The ninth page is a single line page (DB0 only).

Interface designs can read from or write to the RAM array.

The display page is changed through the 4-bit page address register.

The column address (line address) is set with a two-byte register access. The line address corresponds to the first line that is going to be displayed on the LCD panel. This address is located in a 6-bit address register.

The RAM array is configured such that there are two characters per row (page), where each character pair uses eight rows of the display panel. Table B-2 shows the input data bytes, address lines, ADC control, and LCD outputs (segments).

Table B-2: LCD Panel

DB3 DB2 DB1 DB0 DataLine

Address

0 0 0 0

DB0

Page 0

00H

DB1 01H

DB2 02H

DB3 03H

DB4 04H

DB5 05H

DB6 06H

DB7 07H

0 0 0 1

DB0

Page 1

08H

DB1 09H

DB2 0AH

DB3 0BH

DB4 0CH

DB5 0DH

DB6 0EH

DB7 0FH




0 0 1 0

DB0

Page 2

10H

DB1 11H

DB2 12H

DB3 13H

DB4 14H

DB5 15H

DB6 16H

DB7 17H

0 0 1 1

DB0

Page 3

18H

DB1 19H

DB2 1AH

DB3 1BH

DB4 1CH

DB5 1DH

DB6 1EH

DB7 1FH

0 1 0 0

DB0

Page 4

20H

DB1 21H

DB2 22H

DB3 23H

DB4 24H

DB5 25H

DB6 26H

DB7 27H

0 1 0 1

DB0

Page 5

28H

DB1 29H

DB2 2AH

DB3 2BH

DB4 2CH

DB5 2DH

DB6 2EH

DB7 2FH

Table B-2: LCD Panel (Continued)


Address




When a page is addressed, all the bits representing dots on the LCD panel can be accessed in that page. An array of 8x132 bits is available. The line address dictates what line of the RAM is going to be displayed on the first line of the glass panel.

Controller – LCD Panel Connections

The controller die, KS0713, connects to the LCD glass panel and user connection pins via a small PCB. Other necessary pins have default connections on the PCB. Table B-3 shows how all pins of the die are connected. The pins in blue connect to default values on the PCB, and the other pins connect to the user-accessible connectors.

0 1 1 0

DB0

Page 6

30H

DB1 31H

DB2 32H

DB3 33H

DB4 34H

DB5 35H

DB6 36H

DB7 37H

0 1 1 1

DB0

Page 7

38H

DB1 39H

DB2 3AH

DB3 3BH

DB4 3CH

DB5 3DH

DB6 3EH

DB7 3FH

1 0 0 0 DB0 Page 8

Column Address

ADC = 0 0 1 2 3 4 5 6 7 8 9 A B 7E 7F 80 81 82 83

ADC = 1 83 82 81 80 7F 7E 7D 7C 7B 7A 79 78 5 4 3 2 1 0

LCD Output

Seg 1

Seg 2

Seg 3

Seg 4

Seg 5

Seg 6

Seg 7

Seg 8

Seg 9

Seg 10

Seg 11

Seg 12

Seg 127

Seg 128

Seg 129

Seg 130

Seg 131

Seg 132

Table B-2: LCD Panel (Continued)


Address




Table B-3: KS0713 Pin Connections

Connector J1 Connector J2PCB

ConnectionConnected to

Signal Name

Description

16 16 1 CS1B Chip enable is active-LOW

15 15 2 RESETB Initialize the LCD

14 14 3 RS Register select

13 13 4 RW_WR Read/Write

12 12 5 E_RD Enable/Read

11 11 6 DB0 8-bit bidirectional data bus.

In serial mode, DB0-DB5 are high impedance, DB6 is the serial clock input, and DB7 is the serial data input.

10 10 7 DB1

9 9 8 DB2

8 8 9 DB3

7 7 10 DB4

6 6 11 DB5

5 5 12 DB6

4 4 13 DB7

3 3 14 MI Processor mode select

15 PS Parallel or Serial

1 1 16 VSS Ground

2 2 17 VDD Power Supply

LCD Control Pins

VDD CS2 Active-High chip enable

VDD DUTY0 LCD driver duty ratio. Set to 1/65.

VDD DUTY1

VDD MS Master / Slave operation. Set to Master.

VDD CLS Built-in oscillator enable

VSS TEMPS Set to -0.05%/°C

VDD INTRS Internal resistors used

VSS HPM Normal mode set

VDD BSTS Voltage converter input is VDD (2.4<VDD<3.6)

OPEN DISP Only used in Master/Slave

OPEN CL Display clock input

OPEN M Only used in Master/Slave




OPEN FRS Only used in Master/Slave

Voltage Converter and Control

18 VOUT Voltage converter in or out

19 C3+ Voltage pump capacitors

20 C3-

21 C1+

22 C1-

23 C2+

24 C2-

25 V0 LCD driver supply.

The relationship of the voltages is V0>V1>V2>V3>V4>VSS.

When the internal power supply is active, these voltages are generated.

26 V1

27 V2

28 V3

29 V4

30 VSS1

VSS DCDC5B Power Supply Control

OPEN VR V0 Adjustment pin

Table B-3: KS0713 Pin Connections (Continued)

Connector J1 Connector J2PCB

ConnectionConnected to

Signal Name

Description




Controller – Power Supply Circuits

Figure B-5 shows the power supply circuits. The power supply is used in the five times boost mode, where VDD is 3.3V and VOUT is 16.5V. VOUT is the operating voltage of the operational amplifier delivering the operating voltage, V0, for the LCD panel.

The LCD operating voltage, V0, is set with two resistors RA and RB. INTRS is driven Low when the resistors are external. INTRS is driven High when the resistors are internal. For the Virtex-4 ML461 Development Board, internal resistors are selected.

The LCD operating voltage (V0) and the Electronic Volume Voltage (VEV) can be calculated in units of V with these formulae:

Equation 1:

Equation 2:

In Equation 2, VREF is equal to 2.0V at 25 °C.

The values of the reference voltage parameter, α, and the ratio RA/RB are determined with bit settings in the LCD controller’s instruction registers. Thus, it is possible to change

Figure B-5: Power Supply Circuits

DUTY1

DUTY2

BSTS

VR

MS

INTRS

17 VDD

18 VOUT

25

26

27

28

29

30 VSS1

2

1

VDD

VSS

VOUT

5 x VDD

VDD

VSS

16 VSS

DCDC5B

ug077_b_05_081005

V0 1RBRA------+⎝ ⎠

⎛ ⎞ VEV×=

VEV 1 63 α–300---------------–⎝ ⎠

⎛ ⎞ VREF×=




physical operating parameters of the LCD through register bit settings, controlling the operating voltage, and the electronic volume level.

The voltage and contrast settings must be configured before the LCD panel is ready for operation. Figure B-6 shows the initialization procedure required to set up the LCD controller.

Operation Example of the 64128EFCBC-3LPThe KS0713 LCD controller has several default settings of operation on the LCD panel display PCB. Some settings are forced through direct bonding on the chip. The default settings are:

• Master mode

• Parallel mode

• Internal oscillator

• Duty cycle ratio is set to 1/65

• Voltage converter input is between 2.4V ≤ VDD ≤ 3.6V, where VDD connects to 3.3V

Figure B-6: LCD Controller Initialization Flow

End Initialization

Regulator Resistor Select Set Reference Voltage

FPGA Configured and Application RunningRESETB Pin is Taken High

Start FPGA ConfigurationRESETB Pin is Kept Low

RESETB Pin is Kept Low

Setup Instruction Flow

Wait longer than 1 ms between each instruction to let the voltages stabilize.

The on-chip resistors are used. Therefore, the selection MUST be set to 101.

Setting Reference Voltage is a two-pass instruction: - Set Reference Voltage Mode - Set Reference Voltage Register

LCD BiasDUTY0, 1 is "11"LCD Bias 0 = 1/7LCD Bias 1 = 1/9SHL Select

- SHL = 0 COM1 --> COM64 - SHL = 1 COM64 --> COM1

ADC Select - ADC = 0 SEG1 --> SEG132 - ADC = 1 SEG132 --> SEG1

Board Power Supply Start

Power ON

Voltage Converter ON Voltage Regulator ON Voltage Follower ON

ADC Select SHL Select

LCD Bias Select

ug079_b_06_082807




• Internal voltage divider resistors

• Temperature coefficient is set to -0.05%/°C

• Normal power mode is set

• The voltage follower and voltage regulator are set to:

♦ Five times boost mode

♦ The V4, V3, V2, V1, and V0 outputs depend on the bias settings of 1/9 or 1/7.

Because of these default settings, the following display controller connections are not used:

• DISP: Turns into an output when Master mode is selected

• FRS: Static driver segment output

• M: Used in Master/Slave display configurations

• CL: Clock pin used in Master/Slave display configurations

When RESETB is Low, the display controller is initialized as indicated in Table B-4.

When RESETB is High, the display must be initialized. The first steps to be taken to guarantee correct operation of the display and the controller are:

• Configure the ADC bit. This bit determines the scanning direction of the segments.

♦ When the RESETB signal is active, ADC is reset to 0, meaning that the segments are scanned from SEG1 up to SEG132.

♦ When ADC is set to 1, the segments are scanned in opposite direction.

Table B-4: Display Controller Initialization (RESETB is Low)

Parameter Initial Value

Display OFF

Entire display OFF

ADC select OFF

Reverse display OFF

Power control 0,0,0 (VC, VR, VF)

LCD bias 1/7

Read-modify-write OFF

SHL select OFF

Static indicator mode OFF

Static indicator register 0,0 (S1, S0)

Display start 0 (First line)

Column address 0

Page address 0

Regulator select 0,0,0 (R2, R1, R0)

Reference voltage OFF

Reference voltage register 1,0,0,0,0,0 (SV5, SV4, SV3, SV2, SV1, SV0)




• Configure the SHL bit. This bit sets the scanning direction of the COM lines.

♦ When the RESETB signal is active, SHL is reset to 0, meaning that the segments are scanned from COM1 up to COM64.

♦ When SHL is set to 1, the common lines are scanned in opposite direction.

After the SHL bit is configured, these settings normally are not changed.

• Select the LCD bias settings.

♦ The duty cycle is selected as 1/65 by hardwiring the controller IC pads on the display PCB.

♦ The LCD bias is set to:

- 1/7: when the BIAS bit is 0

- 1/9: when the BIAS bit is 1

The following steps are performed next:

• Start the onboard converter, regulator, and follower

• Set the Regulator Resistor values (see Table B-5)

• Configure the reference voltage register parameters (see Table B-6)

At startup of the LCD controller (after RESETB operation), the resistor and reference voltage values are:

• Resistor selection is: 0,0,0

• Reference voltage is: 1,0,0,0,0,0

The Resistor selection value MUST be set to 101b when using this LCD panel.

After the display is brought to operational mode, it is best to wait at least 1 ms to ensure the stabilization of power supply levels. After this time, all other necessary display initializations can be performed.

Table B-5: Resistor Value Settings

3-Bit Data Settings (R2 R1 R0)

000 001 010 011 100 101 110 111

1+(Rb/Ra) 1.90 2.19 2.55 3.02 3.61 4.35 5.29 6.48

Table B-6: Reference Voltage Parameters

SV5 SV4 SV3 SV2 SV1 SV0 Reference Voltage Parameter (α)

0 0 0 0 0 0 0

0 0 0 0 0 1 1

..

..

..

..

…

..

..

..

..

..

..

..

..

..

1 1 1 1 1 0 62

1 1 1 1 1 1 63




Instruction SetTable B-7 shows the instruction set for the LCD panel.

Table B-7: Display Instructions

Instruction RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Read display data 1 1 Read Data

8-bit data specified by the column and page address can be read from the Display Data RAM. The column address is increased automatically, thus data can be read continuously from the addressed page.

Write display data 1 0 Write Data

8-bit data can be written into a RAM location specified by the column and page address. The column address is increased automatically, thus data can be written continuously to the addressed page.

Read status 0 1 BUSY ADC ONOFF RESETB 0 0 0 0

BUSY: Device is BUSY when internal operation or reset. (0=active, 1 =busy).

ADC: Indicates the relationship between RAM column address and segment driver.

ONOFF: Indicates display ON or OFF status.

RESETB: Indicates if initialization is in progress.

Display ON/OFF 0 0 1 0 1 0 1 1 1 DON

Turn display ON or OFF. (1=ON, 0 = OFF)

Initial display line 0 0 0 1 ST5 ST4 ST3 ST2 ST1 ST0

Sets the line address of the display RAM to determine the initial line of the LCD display.

ST5 ST4 ST3 ST2 ST1 ST0

0 0 0 0 0 0 Line address 0


.. .. .. .. .. .. ..






Set reference voltage mode 0 0 1 0 0 0 0 0 0 1

Set reference voltage register 0 0 x x SV5 SV4 SV3 SV2 SV1 SV0

This is a two-byte instruction. The first instruction sets the reference voltage mode. The second instruction sets the reference voltage parameter.

SV5 SV4 SV3 SV2 SV1 SV0

0 0 0 0 0 0 0

0 0 0 0 0 1 1

.. .. .. .. .. .. ..

1 1 1 1 1 0 62

1 1 1 1 1 1 63

Set page address 0 0 1 0 1 1 P3 P2 P1 P0

This instruction sets the address of the display data page. Any RAM data bit can be accessed when its page address and column address are specified. Changing the Page Address does not affect the display status.

P3 P2 P1 P0

0 0 0 0 page 0

0 0 0 1 page 1

.. .. .. .. ...

0 1 1 1 page 7

1 0 0 0 page 8

Table B-7: Display Instructions (Continued)





Set column address MSB 0 0 0 0 0 1 Y7 Y6 Y5 Y4

Set column address LSB 0 0 0 0 0 0 Y3 Y2 Y1 Y0

This instruction sets the address of the display data RAM. When a read or write to or from the display data RAM occurs, the addresses are automatically increased.

Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

0 0 0 0 0 0 0 0Col

Addr 0

0 0 0 0 0 0 0 1Col

Addr 1

.. .. .. .. .. .. .. .. ...

1 1 1 1 1 1 1 0Col

Addr 130

1 1 1 1 1 1 1 1Col

Addr 131

ADC select 0 0 1 0 1 0 0 0 0 ADC

This instruction changes the relationship between RAM column address and segment driver.

ADC = 0, SEG1 --> SEG132 default modeADC = 1, SEG132 --> SEG1

Reverse display ON/OFF 0 0 1 0 1 0 0 1 1 REV

REV RAM bit data = '1' RAM bit data = '0'

0 Pixel ON Pixel OFF

1 Pixel OFF Pixel ON

Entire display ON/OFF 0 0 1 0 1 0 0 1 0 EON

This instruction forces the display to be turned on regardless the contents of the display data RAM. The contents of the display data RAM are saved. This instruction has priority over reverse display.

LCD bias select 0 0 1 0 1 0 0 0 1 BIAS

This instruction selects the LCD bias.

Duty ratio

Bias = 0 Bias = 1

1/65 1/7 1/9






Read/Write Characteristics (6800 Mode)

Set modify-read 0 0 1 1 1 0 0 0 0 0

This instruction stops the automatic incrementing of the column address by a read operation. The automatic increment is still done with a write operation.

Reset modify-read 0 0 1 1 1 0 1 1 1 0

This instruction resets the changed modify-read to the normal.

Reset 0 0 1 1 1 0 0 0 1 0

This instruction resets the LCD controller registers to the default values. The instruction CANNOT initialize the LCD power supply initialized with RESETB.

SHL select 0 0 1 1 0 0 SHL x x x

This instruction sets the COM output scanning direction.

SHL = 0, COM1 ----> COM64 (default)SHL = 1, COM64 ----> COM1

Power Control 0 0 0 0 1 0 1 VC VR VF

This instruction selects one of the eight power circuit functions. In the case of the DisplayTech 64128EFCBC display, these must be kept at 000.

Regulator resistor select 0 0 0 0 1 0 0 R2 R1 R0

This instruction selects the resistor ratio Rb/Ra.

Set static indicator mode 0 0 1 0 1 0 1 1 0 SM

Set static indicator register 0 0 x x x x x x S1 S0

This is a two-byte instruction. The first instruction enables the second instruction. The second instruction update the contents of the static indicator register.



Table B-8: Read/Write Characteristics in 6800 Mode

Parameter Signal Symbol Min Typ Max Unit

Address setup timeRS

TAS 13 - - ns

Address hold time TAH 17 - - ns

Data setup timeDB7 to DB0

TDS 35 - - ns

Data hold time TDH 13 - - ns

Access time TACC - - 125 ns

Output disable time TOD 10 - 90 ns

System cycle time RS TCYC 400 - - ns

Enable pulse width Read/write E_RDTPWR 125 - ns

TPWW 55 - ns




Design Examples

LCD Panel Used in Full Graphics Mode

The LCD controller RAM has eight 132-byte pages (in fact, there are nine pages; page 9 is special). Each page is one byte wide. If all the pages are put in one memory block, then the needed space is 8 pages x 8 bits x 132 pixels or 8448 bits (1056 bytes).

One Virtex-4 block RAM can be configured as 8+1 by 2048.

One block RAM can be used to store one complete pixel view of the LCD panel. There is enough space left for commands.

The ninth bit in the block RAM memory indicates whether the data in the block RAM is real data to be displayed or is a command for the controller.

The interface to the LCD panel is slow. The E signal can be used as the controller clock signal. This signal has a minimum cycle time of 400 ns for displaying 8 bits (equal to 8 dots) on the LCD. One full page of the display takes up to 132 x 400 ns = 52.8 μs. Updating the full display takes 52.8μs x 8 = 423μs.

If using the dual port and data width capabilities of the block RAM, then writes to the block RAM can be 32 bits (+4 control bits), and reads from the block RAM on the LCD side can be 8 bits (1 control bit). An entire LCD page is updated in 33 write operations.

The interface on the LCD panel side sequentially reads the block RAM, and thus, updates the screen contiguously (like a television screen). The controller (microcontroller or other) side of the block RAM can be written at any time.

Figure B-7: Read/Write Timing Waveforms (6800 Mode)

RS

RW

CS1B

E

WRITEDB0-DB7

READ

ug079_b_07_081005

TAS TAH

TCYC

TPWR

TACC TOD

TPWW

TDS TDH




The write operation happens on the rising edge of the clock and the read (LCD update) happens on the falling edge of the clock. Normally write and read operations at the same address give corrupt read data when the read and write clock edges do not respect the clock-to-clock setup timing. This problem is solved by using both edges of the clock.

A state machine is used to provide correct timing of the signals on the LCD panel side. The panel can be used in write-only mode or in read/write mode. Most of the time LCD panels operate in write-only mode.

At first, the block RAM must be initialized with some data (instructions to the LCD) to make the LCD operate correctly. See Figure B-8 for a general block diagram.

LCD Panel Used in Character Mode

This design example requires a byte representing a command or data to be displayed as input.

• When the Enable signal is Low, nothing happens. The display interface design is locked.

• When the Enable signal is High and the data_or_command control signal is Low, the byte written is a display command.

Figure B-8: General Block Diagram of Panel in Full Graphics Mode

ug037_b_08_081005

Block RAM

IorD = '1' Instruction'0' Data

Design for Full Graphics Interface, Attached to CoreConnect Bus

Enable

Write

Address

WData (32+4)

RData (8+gnd)

ena

Clock

read

Addr

IorD (bit 9)

DataIn (8)

DataOut (8)

RW

E

Clock

Reset

Clock

Reset

ClockE

TC

RS

CS1B

DB (8)

Cor

eCon

nect

StateMachine

Clock




• When the Enable signal and the data_or_command control signal are High, the byte written is the ASCII character code of the character to be put on the display.

Display Command Byte

The command set of the display can be found in Table B-7.

When the LCD interface is enabled for the first time, a set of command bytes is sent to the LCD. This command set provides the basic initialization of the LCD display controller. When this initialization is done, the normal LCD display interface is freed for normal use. Command bytes from the valid command set can be sent to the display (controller).

A detailed description of the LCD controller interface can be found in the Toplevel.vhd.txt file.

Display Data Byte

The supplied byte must be a valid ASCII representation of a character as shown in Figure B-9.

Figure B-9: ASCII Character Representations

ug079_b_09_081005




The character set is stored in block RAM (used as ROM). For the layout of the block RAM character set, see the CharacterSet.xls file. The block RAM (see Figure B-10) is organized as small arrays of eight bytes, which is easy for address calculation.

When presenting byte value 30 hex, character 0 must be displayed. Shifting the value 00110000b (30h) up three positions gives the value 180h or 348d.

Because each character uses eight byte locations, character 0 in the character set starts from memory location 348 decimal.

For example, character X has byte value 58h or 01011000b. Shifting this value three positions gives the value 2C0h or 704d.

Figure B-11 shows a block diagram of the LCD character generator controller. Character data is latched and then shifted left three positions. This shifted value is the start byte for a counter that outputs an address to the block RAM. The result is a stream of bytes representing a character for the display.

A small second counter determines when a new character is loaded into the block RAM address counter.

Figure B-10: Block RAM Organization

F0 - FF

The RAM array is divided inpages of eight bytes by 16,forming an array of 128 bytes.This array represents onecolumn of standard ASCII table.A character is stored as:

E0 - EF

D0 - DF

C0 - CF

B0 - BF

A0 - AF

Not Used

Not Used

70 - 7F

60 - 6F

50 - 5F

40 - 4F

30 - 3F

20 - 2F

10 - 1F

Not Used

2047

12801279

10241023

N-x

NN-1 Shift

direction

Addr

00 1 2 3 4 5 6 7 Data

256255

0

Addr[10:0]

Data[7:0]

RAMB16_S9

ug037_c8_10_062903




A state machine manages the processing order.

A minimum cycle time of 400 ns on the E signal used as a reference. The 200-MHz system clock frequency is used as reference system clock. One E cycle uses at least 80 system clock cycles when the design is running at 200 MHz. The E pulse is part of the state machine, and the design only depends on the system clock. Timing is met as long as the system clock does not exceed 200 MHz.

This design can be adapted easily to fit the MicroBlaze™ processor or IBM PowerPC® 405 core connect bus system.

Figure B-11: LCD Character Generator Controller

TC

L

Addr

DI

E E

RAMB16_S9

Counter B

Counter A

PositionRegister

Clk

Ena

DataIn

Ena

E Load

Clk

Clk

Clk

We

DO

Ssr

8

3

11 11 8

Count to 8.Stop both counters at TC.Send character position andline to the LCD.Load new value in counter A.Switch to character ROM.Enable counters.

8

Clk

Ena State Machine

Page

Rst

Rst

DisplayRegister

DesRst

DesRst DesRst

DesRst

DesRst

DesRst

8

Clk

LUT-ROMDisplayInitialization

RS

RW

Data

E

1

0

ug079_b_11_081005




Array Connector Numbering

UCF Information# FPGA 4 # Bank 7 / LCD-BUS # # NET " " LOC ="Y21 "; # LCD_D7 IO_L20N_VREF_7 # NET " " LOC ="Y20 "; # LCD_D6 IO_L20P_7 # NET " " LOC ="AE23 "; # LCD_D5 IO_L19N_7 # NET " " LOC ="AF23 "; # LCD_D4 IO_L19P_7 # NET " " LOC ="W19 "; # LCD_D3 IO_L18N_7 # NET " " LOC ="Y19 "; # LCD_D2 IO_L18P_7 # NET " " LOC ="AF20 "; # LCD_D1 IO_L17N_7 # NET " " LOC ="AF19 "; # LCD_D0 IO_L17P_7 # NET " " LOC ="AA18 "; # LCD_RS IO_L21P_7 # NET " " LOC ="Y18 "; # LCD_RW IO_L21N_7 # NET " " LOC ="AF24 "; # LCD_ENA IO_L22P_7 # NET " " LOC ="AE24 "; #LCD_BL_ON IO_L22N_7 # NET " " LOC ="AE20 "; # LCD_CS1B IO_L23P_VRN_7 # NET " " LOC ="AD20 "; # LCD_RSEL IO_L23N_VRP_7 #

Figure B-12: LCD Connections (Bank 0)

Bank 0

Connector Pin FPGA Pin

A B C D E F G H ID9 LCD_D0 AF19

10D7 LCD_D4 AF23

9D5 LCD_D5 AE23

8D3 LCD_D6 Y20

7D1 LCD_D7 Y21

6E10 LCD_RST AA18

5E8 LCD_D1 AF20

4E6 LCD_D2 Y19

3E4 LCD_D3 W19

2E2 LCD_ENA AF24

1F5 LCD_R/W Y18

F3 LCD_RSEL AD20

Connector J32F1 LCD_CS1B AE20

UG079_B_12_081005





Documents

Xilinx UG079 Virtex-4 ML461 Memory Interfaces Development ... · R Virtex-4 ML461 Memory Interfaces Development Board User Guide UG079 (v1.1) September 5, 2007