Topic 10 - Memory circuits - Imperial College London

Topic 10 - 1 Nov-22-10 E4.20 Digital IC Design © Prentice Hall 1995/2000

Topic 10 Memory Circuits

Peter Cheung Department of Electrical & Electronic Engineering

Imperial College London

URL: www.ee.ic.ac.uk/pcheung/ E-mail: [email protected]

Reading: Weste Ch 8.3.1-8.3.2, Rabaey Ch.10, p.551-595


Semiconductor Memory Classification


Memory Architecture: Decoders


Array-Structured Memory Architecture


Hierarchical Memory Architecture


Memory Timing: Definitions


Memory Timing: Approaches


MOS NOR ROM


MOS NOR ROM Layout


MOS NOR ROM Layout


MOS NAND ROM


MOS NAND ROM Layout


Decreasing Word Line Delay


Precharged MOS NOR ROM


Floating-Gate Transistor Programming


Flash EEPROM


Cross-sections of NVM cells

EPROM Flash Courtesy Intel


Characteristics of State-of-the-art NVM


Read-Write Memories (RAM)


Basic RAM Cell


6-transistor CMOS SRAM Cell


SRAM Read/Write


RAM Cell Design


6T-SRAM — Layout

VDD

GND

Q Q

WL

BL BL

M1 M3

M4 M2

M5 M6


More Cell Layout


Resistance-load SRAM Cell


Dual Port RAM


Multiport RAM Cell


3-Transistor DRAM Cell


3T-DRAM — Layout

BL2 BL1 GND

RWL

WWL

M3

M2

M1


1-Transistor DRAM Cell


DRAM Cell Observations


1-T DRAM Cell


SEM of poly-diffusion capacitor 1T-DRAM


Advanced 1T DRAM Cells

Cell Plate Si

Capacitor Insulator

Storage Node Poly

2nd Field Oxide

Refilling Poly

Si Substrate

Trench Cell Stacked-capacitor Cell

Capacitor dielectric layer Cell plate Word line

Insulating Layer

Isolation Transfer gate Storage electrode


Address Transition Detection


Row Decoders

Collection of 2M complex logic gates Organized in regular and dense fashion

(N)AND Decoder

NOR Decoder


Dynamic Decoders


A NAND decoder using 2-input pre-decoders


4 input pass-transistor based column decoder

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.

BL 0 BL 1 BL 2 BL 3

D

A 0

A 1

S 0 S 1

S 2

S 3 2 i n p u

t N O R

d e c o d

e r

Advantage: speed (t pd does not add to overall memory access time)

Disadvantage: large transistor count only 1 extra transistor in signal path


4-to-1 tree based column decoder


Decoder for circular shift-register


Bitline I/O Circuit - Read


Bitline I/O Circuit - Write


Write Drivers


Alternative Write Circuit


Bitline Multiplexing


Bitline Mux - Option 1


Bitline Mux - Option 2


Sense Amplifiers


Sense Amp Circuit


Latch-Based Sense Amplifier


Single-to-Differential Conversion


Open bitline architecture


DRAM Read Process with Dummy Cell


Single-Ended Cascode Amplifier


Programmable Logic Array


Pseudo-Static PLA


Dynamic PLA


Clock Signal Generation for self-timed dynamic PLA


PLA Layout


PLA versus ROM

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Topic 10 - Memory circuits - Imperial College London