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Topic 10 - 1 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
Topic 10 Arithmetic Circuits &
Datapaths
Peter Cheung Department of Electrical & Electronic Engineering
Imperial College London
URL: www.ee.ic.ac.uk/pcheung/ E-mail: [email protected]
Topic 10 - 2 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
Bit-Sliced Design
Topic 10 - 3 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
Full-Adder
Topic 10 - 4 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
The Binary Adder
Topic 10 - 5 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
Express Sum and Carry as a function of P, G, D
Define 3 new variable which ONLY depend on A, B Generate (G) = AB Propagate (P) = A ⊕ B Delete = A B
Can also derive expressions for S and C o based on D and P
Topic 10 - 6 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
The Ripple-Carry Adder
Topic 10 - 7 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
Complimentary Static CMOS Full Adder
Topic 10 - 8 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
Inversion Property
Topic 10 - 9 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
Minimize Critical Path by Reducing Inverting Stages
Topic 10 - 10 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
The better structure: the Mirror Adder
Generate (G) = AB Propagate (P) = A ⊕ B Delete = A B
Topic 10 - 11 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
The Mirror Adder
• The NMOS and PMOS chains are completely symmetrical. This guarantees identical rising and falling transitions if the NMOS and PMOS devices are properly sized. A maximum of two series transistors can be observed in the carry-generation circuitry.
• When laying out the cell, the most critical issue is the minimization of the capacitance at node Co. The reduction of the diffusion capacitances is particularly important.
• The capacitance at node Co is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell .
• The transistors connected to Ci are placed closest to the output. • Only the transistors in the carry stage have to be optimized for optimal speed. All transistors in the sum stage can be minimal size.
Topic 10 - 12 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
Quasi-Clocked Adder
Topic 10 - 13 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
Manchester Carry Chain
Topic 10 - 14 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
Sizing Manchester Carry Chain
Topic 10 - 15 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
Carry-Bypass Adder
Topic 10 - 16 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
Manchester-Carry Implementation
Topic 10 - 17 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
Carry-Bypass Adder (cont.)
Topic 10 - 18 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
Carry Ripple versus Carry Bypass
Topic 10 - 19 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
Carry-Select Adder
Topic 10 - 20 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
Carry Select Adder: Critical Path
Topic 10 - 21 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
Linear Carry Select
Topic 10 - 22 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
Square Root Carry Select
Topic 10 - 23 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
Adder Delays - Comparison
Topic 10 - 24 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
LookAhead - Basic Idea
Topic 10 - 25 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
Look-Ahead: Topology
Topic 10 - 26 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
The Array Multiplier
Topic 10 - 27 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
The MxN Array Multiplier — Critical Path
Critical Path 1 & 2
Topic 10 - 28 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
Carry-Save Multiplier
Topic 10 - 29 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
Adder Cells in Array Multiplier
Topic 10 - 30 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
Multiplier Floorplan
Topic 10 - 31 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
Multipliers —Summary
Topic 10 - 32 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
The Binary Shifter
Topic 10 - 33 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
The Barrel Shifter
Area Dominated by Wiring
Topic 10 - 34 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
4x4 barrel shifter
Widthbarrel ~ 2 pm M
Topic 10 - 35 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
Logarithmic Shifter
Topic 10 - 36 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
A 3
A 2
A 1
A 0
Out3
Out2
Out1
Out0
0-7 bit Logarithmic Shifter
Topic 10 - 37 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
Design as a Trade-Off
Topic 10 - 38 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
Layout Strategies for Bit-Sliced Datapaths
Topic 10 - 39 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
Layout of Bit-sliced Datapaths
Topic 10 - 40 Nov-27-09 E4.20 Digital IC Design © Prentice Hall
Layout of Bit-sliced Datapaths
