© PACT XPP AG 2V1.0/08.04.03

Today’s Mega Trends

§ Conversion of voice, audio, video & data

§ Global Mobility

§ Increasing functionality in devices

§ Changing standards

§ Growing barriers of leading edge silicon

© PACT XPP AG 3V1.0/08.04.03

Today’s Challenges

§ Time to market

§ Development risk

§ Cost – Cost – Cost

§ User driven product (2G, 2.5G, WiFi, Games)

§ Support for multiple standards

§ Evolving standards in the market

§ Product life cycle

§ Market insecurity

© PACT XPP AG 4V1.0/08.04.03

Reconfigurable Computing

THE solution

© PACT XPP AG 5V1.0/08.04.03

Reconfigurable Computing – BUT…

§ Many false starts

§ Broken promises

§ No products available

§ High cost

§ High efforts (I.e. programming)

© PACT XPP AG 6V1.0/08.04.03

PACT XPP Technology

§ Programmable Hardware Platform§ No ASIC NRE cost§ Low risk§ Time to market§ Reusable for multiple products§ Reusable over multiple generations

§ Standard Software Base & Libraries§ Leverage know-how of existing designs§ Reuse existing code

§ XPP / µP Coupling§ Use and leverage 100.000s lines of existing code§ Easy and cost efficient migration of today‘s code to

reconfigurable hardware platforms

PACT XPP Technology

© PACT XPP AG 8V1.0/08.04.03

Sequential Processor Model

Conventional processors use the sequential model:Each operation takes one clock cycle.Multiple operations are computed consecutively.

RegisterOperation 1

Time

Operation 2

Operation 3

Operation 4

Operation 5

© PACT XPP AG 9V1.0/08.04.03

A New Parallel Processor Paradigm

Multiple computations are configured as code sections onto a two dimensional array.

Time

x

yData Buffer

© PACT XPP AG 10V1.0/08.04.03

Parallel Processor Model

Multiple code sections are computed sequentially.

Time

y

xOperation 2

Section 1

Section 2

Section 3

© PACT XPP AG 11V1.0/08.04.03

Dataflow Performance

Traditional Microprocessor XPP Architecture

SHIFT

InstructionMemory and cache

ConfigurationMemory and cache

MULT

One operation per cycle

Many operations per cycleFFT

Viterbi

Basic machine operationsperformed on single words

Complex Functionsperformed on data streams

ADD

Register

One word

ALU Buffer

Stream of words

Array of ALUs

Filter

© PACT XPP AG 12V1.0/08.04.03

XPP - Modular and Scalable Architecture

XPPs are arrays built from a small number of standardized PAE-elements and are available from 16 to over 100 PAE-elements

§ I/O-Element

§ RAM - PAE

§ ALU - PAE

All PAEs include:

+ Automatic DataFlow Synchronization

+ Event Network

+ Reconfiguration Handling

§ Configuration Manager

© PACT XPP AG 13V1.0/08.04.03

XPP ultra low power technology

49 mW cycle / MHz

176 cycles

12 mW cycle / MHz40 cycles

Real 16 Tap FIR Filter (40 Samples)

453 mW cycle / MHz

1619 cycles

360 mW cycle / MHz1200 cycles

256-point FFT

51 mW cycle / MHz

181 cycles / block

19 mW cycle / MHz

64 cycles/ blockMPEG Video 2D DCT (8x8)

High End DSPXPP16Algorithm

DCT 8x8 (10blocks) 16-tap FIR (400

samples) 256-point FFT

XPP16

SC1400

100

200

300

400

500

600

mW

cyc

le /

MH

z

§ XPP16 and High End DSP have equal gate count

§ XPP needs less clock frequency due to high parallelism

§ XPP has less overhead for:

§ opcode fetch

§ data transfer to register/cache/memory

§ Fine grained clock gating per PAE

Applications and Market Segments

© PACT XPP AG 15V1.0/08.04.03

ME

M C

TR

ARMCORE

SRAM

BOOTROM

ICACHE

ITCM

DCACHE

DTCM

RF SYSTEM

Baseband Chip

FLASH / SRAM

LCD DISPLAY

ANALOGAUDIO

DIGITALAUDIO

ENERGYMANAGEMENT

SD/MMC

CMOS Camera

XPP4x4

System+ ARM7

EJS

MM

C

SS

C

CCIR656 SSC

RX/TX

D / ADRS

SC

UA

RT

I2S

I2SXRAM

DSPCORE

YRAM

PRAMA

UD

IO I

IF RF

IIF

SD

/MM

C IF

BA

TT

ER

Y

Application Example: SMeXPP Multimedia Handset Solution

© PACT XPP AG 16V1.0/08.04.03

XPP4x4

SRAM1Mbit

SRAM1Mbit

SRAM1Mbit

AHBMaster

AHBSlave

AHBSlave

AHBMaster

DMA

AHBBridge ARM7 EJS

APBBridge

SRAM1Mbit

DMA InterruptCtrl

XPP Cfg& Event

Timer UART JTAG GPIO RTC

PowerMng.

PLL

PLL

AH

B/A

HB

Bri

dge

Gim

mik

I/F

CA

M.

SS

C1

ROM32Kbit ETM

ARM Clock Domain

AHB/XPP Clock Domain

ARM7 BUS APB BUS

AH

B B

USAHB Bus Layer #3

AHB Bus Layer #0

AHB Bus Layer #1

AHB Bus Layer #2

IRQFIQ

SMeXPP Block Diagram

© PACT XPP AG 17V1.0/08.04.03

16 MB0

6 MBit4 MBit

1x> 16x

208 MHz13 MHz

0,5 – 0,8 mW/MHz< 0,4 mW/MHz

416

500 MIPS2000 MIPS

Application Processor

SMeXPP

Off Chip Memory

On Chip Memory

Battery Lifetime

Frequency

Power

# MACs

Performance

SMeXPP Technical Benefits

© PACT XPP AG 18V1.0/08.04.03

Application Performance

ARM7+XPP16, 4x4 ALU array, 8 RAM elements:

§ 15 fps QCIF MPEG4 Encode @ 13 MHz: < 22 mW

§ 15 fps H.263 Video Conferencing @ 26 MHz: < 60 mW

§ 15 fps CIF MPEG4 Encode @ 52 MHz: < 90 mW

§ 30 fps VGA MPEG4 Encode @ 52 MHz: < 110 mW

SMeXPP cost : < 10$

© PACT XPP AG 19V1.0/08.04.03

SDR / Multimedia – Complete Solution

2.4 GHz5 GHzCDMAGSMEDGE

FLASH / SRAM

LCD DISPLAY

ANALOGAUDIO

DIGITALAUDIO

ENERGYMANAGEMENT

SD/MMC

CMOS SENSOR

MM

C

CCIR656 SSC

RX/TX

D / ADR

I2S

BA

TT

ER

Y

ARM11

PACTXPP

Timers Peripherial

Camera I/F Display I/F

RF System I/FGSMEDGECDMA

Audio I/F

Memory I/FSD/MMC

internalmemory

© PACT XPP AG 20V1.0/08.04.03

SdRXPP Block Diagram

XPP8x6

SRAM2Mbit

SRAM2Mbit

SRAM2Mbit

AHBI/F

DMA

AHBBridge

AP

BB

ridg

eInterrupt

CtrlXPP Cfg& Event

3G SystemTimer SIM JTAG GPIO RTC

PowerMng.

PLL

PLL

AH

B/A

HB

Bri

dge

SS

C2

SS

C1

ETM

ARM Clock Domain

AHB/XPP Clock Domain

APB BUS

AH

B B

US

AHB Bus Layer #3

AHB Bus Layer #0

AHB Bus Layer #1

AHB Bus Layer #2

IRQFIQ

AHBI/F

AHBI/F

AHBI/F

AHBI/F

AHBI/F

AHBI/F

AHBI/F

MC

IR

F

ETB

DSP Extension

I-Cache D-Cache

D-TCMI-TCM

AHB I/F

ARM1136-JS

© PACT XPP AG 21V1.0/08.04.03

XPP Baseband Solution

Traditional PACT SDRXPPARM11

PACTXPP

Timers Peripherial

GSM RF UMTS RF

SC120

HWAccelerator

SC120

HWAccelerator

GSM CDMA

GSM RF UMTS RF

ARM926Timers Peripherial

ARM926HW

Accelerator

ModemControl

ApplicationProcessor

SC

120

§Programming complicatedMultiple µPs/DSPs Communication Debugging

§Large memory required§Huge die, dual chip solution§Application space limited

Fixed HW accelerators

§Easy to programOne master µP + one slave coprocessor

§Less memory required§Small die, single chip solution§Large application space

Reconfigurable HW accelerator

SDRXPP cost : < 25$

Software Tools and Programming

© PACT XPP AG 23V1.0/08.04.03

XPP integrated C-based tool chain

C-CodeC-Code

µC

PreprocessorµC

C-CompilerXPP

C-Compiler

µCDebugger

XPPDebugger

Integrated debug environment

NML Library

Multi-LayerAMBA

§XPP tools integrated in host processors tools

§One source code for XPP and µC§Code exchanged by

-Annotation-Library subroutine calls

§Automatic insertion of interface routines for µC and XPP intercommunication

§Integrated debug environment

Silicon Implementation

IP Package

© PACT XPP AG 25V1.0/08.04.03

XPP64A Layout & Features

§ 64 ALU-PAEs§ 16 RAM-PAEs§ 24-bit architecture§ Split (12,12)-bit opcodes§ complex addition§ complex multiplication§ conditional sign-flip

§ JTAG debug interface

§ 0.13µ silicon from STMicro, Crolles

§ Wafer Out: 03/03/03

© PACT XPP AG 26V1.0/08.04.03

XPP64A Development Platform

ExpansionModule

XPP64 Development Platform & XDS Toolsuite supports evaluation and software development for XPPs arrays in sizes from 16 to 64 elements (i.e. XPP16, XPP32, XPP48)