Three-Level TAIPEI Rectifier Yungtaek Jang, Milan M. Jovanović, and Juan M. Ruiz

Power Electronics Laboratory Delta Products Corporation

5101 Davis Drive, Research Triangle Park, NC, USA

Abstract— A new low-cost, three-phase, four-switch, three-level, zero-voltage-switching (ZVS), discontinuous-current-mode (DCM), power-factor-correction (PFC) boost rectifier, for short named the three-level TAIPEI rectifier, that achieves a low input-current total-harmonic-distortion (THD) and features ZVS of all the switches is introduced. In the proposed rectifier, the voltage stress of the four switches is equal to one-half of the output voltage. Consequently, the rectifier can utilize switches with a lower voltage rating, which, generally, have lower conduction losses. The performance was evaluated on a three-phase 6-kW prototype for the line-to-line voltage range from 340 V to 520 V. The proposed rectifier exhibits efficiency in the 96-98% range, achieves less than 5% input-current THD over the entire input and above 10% load range.

I. INTRODUCTION Achieving high efficiency in high-voltage applications is

a major design challenge that requires the optimization of conduction and switching losses through a careful selection of the converter topology and switching device characteristics. Namely, higher voltage-rated semiconductor switches such as MOSFETs and IGBT switching devices exhibit larger conduction losses compared to their counterparts with a lower voltage rating.

Generally, switching losses can be reduced and even eliminated by resorting to a variety of resonant or soft-switching topologies [1]-[3]. However, the approaches for reducing the conduction losses are limited. An approach that can further decrease the conduction losses is to employ a topology that can utilize switches with a lower voltage rating and, consequently, a lower conduction loss. Since in the class of circuits known as multilevel converters [4]-[6] switches operate with a voltage stress that is much less than the input and output voltage, the multilevel converters are a natural choice in high-voltage applications.

Recently, a low-cost, three-phase, two-switch, zero-voltage-switching (ZVS), discontinuous-current-mode (DCM), power-factor-correction (PFC) boost rectifier, for short named the TAIPEI rectifier, that achieves a low input-current total-harmonic-distortion (THD) and features ZVS of all the switches without any additional soft-switching circuitry was introduced [7]. When operating in the line-to-line voltage range from 180 V to 260 V where 650-V MOSFETs can be used for the two switches, this minimum-component rectifier exhibits excellent performance with the input-current THD below 5% and efficiency in the 96-97% range, as reported in [8]. However, since the voltage stress of the switches is equal to the output voltage, the rectifier cannot maintain this efficiency when the input voltage is extended above 260 V. Namely, for rectifiers operating in the three-phase 380-480-VL-L, RMS input range, the output voltage is typically around 800 V. As a result, the two-switch, ZVS,

DCM, PFC boost rectifier operating in this voltage range requires switches with a voltage rating of at least 1000 V, which are currently much less efficient than 650-V rated MOSFETs.

In this paper, the concept employed to achieve PFC and ZVS of the switches in three-phase, two-switch, ZVS, DCM, PFC boost rectifier is extended to obtain a low-cost, three-level rectifier that can utilize switches with a lower voltage rating. In this three-level rectifier, which employs only four switches, the voltage stress across all the switches is clamped to one half of the output voltage. When designed for the line-to-line voltage range from 340 V to 520 V, the proposed rectifier exhibits efficiency in the 97-98% range, achieves less than 5% input-current THD over the entire input and above 10% load range, and features ZVS of all the switches. Moreover, the proposed rectifier has automatic voltage balancing across the two output capacitors connected in series with each capacitor having less than 400 V. As a result, downstream isolated converters implemented with 600-V-rated switches can be connected across the capacitors without creating a voltage imbalance. In addition, the common-mode electro-magnetic interference (EMI) of the proposed rectifier is low. The evaluation was performed on a three-phase 6-kW prototype operating from the line voltage range of 340-520-VL-L, RMS.

II. THREE-PHASE THREE-LEVEL TAIPEI RECTIFIER Figure 1 shows the proposed three-phase three-level

ZVS PFC DCM boost rectifier. The input of the circuit consists of three boost inductors L1, L2, and L3 coupled to three capacitors C1, C2, and C3 connected in the Y (“star”) configuration and the three-phase input terminals through an EMI filter (not shown in Fig. 1). The common point of the capacitors N is connected to the mid-point between serially-

L 1

L 2

L 3

D1 D2 D3

D4 D5 D6

R V O

+

C1 C2 C3

L C

CO1

CO2

CR

N

DC1

DC2

V A

V B

V C

0 CC

S2

S3

S1

S4

RPR

Fig. 1. Proposed three-phase three-level ZVS PFC DCM boost rectifier.

978-1-4799-2325-0/14/$31.00 ©2014 IEEE 943

connected switch pairs S1 - S2 and S3 - S4 and also to the mid-point of split output capacitors CO1 and CO2. The mid-point of serially-connected switches S1 - S2 is connected to output capacitor CO1 through clamping diode DC1 so that the voltage across switch S2 is clamped to the voltage across capacitor CO1, which is one half of output voltage VO. Similarly, the mid-point of serially-connected switches S3 - S4 is connected to output capacitor CO2 through clamping diode DC2 and the voltage across switch S3 is also clamped to one-half of output voltage VO. Clamping capacitor CC is connected between the mid-points of the two pairs of serially-connected switches and it is pre-charged to its steady-state average voltage of one-half of the output voltage through the loop consisting of capacitor CO2, the body diode of switch S2, pre-charge resistor RPR, and a winding of coupled inductor LC. Capacitor CR that is used to reset the inductor currents is connected across the serially-connected pairs of switches and is decoupled from the output by coupled inductor LC. Its average voltage is equal to the output voltage since the average voltage across the windings of LC is zero. The voltages across switches S1 and S4 are clamped to the difference of the voltages across capacitor CR and CC through the body diodes of switch S4 and switch S1, respectively. Since this difference is equal to one-half of the output voltage, the voltages across all four switches in the circuit in Fig. 1 are clamped to one-half of the output voltage. Generally, any kind of switch that is capable of

conducting current in both directions and blocking voltage in one direction such as for example a MOSFET or an IGBT with an antiparallel diode is suitable for this application.

To achieve a low input-current THD, high PF, and a wide-load-range soft-switching of the switches, the circuit in Fig. 1 must operate in DCM with a low-bandwidth output-voltage control. This control can be implemented in a variety of ways. Figure 2(a) shows timing waveforms of the four switches of the circuit in Fig. 1 for variable switching-frequency control. In the variable-frequency control in Fig. 2(a), two pairs of switches S1-S2 and S3-S4 are switched in a complementary fashion with a small dead time td between their commutation instants to enable the pair of switches that is about to turn on to achieve ZVS. Since dead time td is very small in comparison with switching period TS, the effect of the dead time is negligible, i.e., it can be assumed that the duty cycle of each switch is approximately 50%. Because the switches of each pair operate with the same gate signal as shown in Fig. 2(a), the control circuit is identical to that of the two-level two-switch, ZVS, DCM, PFC boost rectifier [8].

Figure 2(b) shows another control method of the circuit in Fig. 1. In this control, switches S1 and S4 are switched at a constant frequency in a complementary fashion with a small dead time, i.e., with approximately 50% duty ratio. The duty ratio of switches S2 and S3, whose turn-on instants are synchronized with the turn on instants of S1 and S4, respectively, is pulse-width modulated to provide regulation of the output. While the rectifier output voltage can be fully regulated by this constant-frequency pulse-width modulation (PWM) control, the rectifier exhibits high input-current THD and loses ZVS when the duty cycle becomes small. However, by properly combining variable switching-frequency and PWM control, low THD and a wide ZVS range can be achieved with a reduced frequency range. Namely, since in the output-voltage-regulated converter in Fig. 1 the switching frequency increases as the load decrease, the frequency range can be reduced by employing variable switching-frequency control over the range from full load to light load and resorting to constant-frequency control at light loads.

Figure 2(c) shows a phase-shift control method of the circuit in Fig. 1. Two pairs of switches S1-S4 and S2-S3 are switched at a constant frequency in a complementary fashion with a fixed duty ratio of approximately 50%. The control is achieved by a phase shift of the switching instants of the S1-S4 pair with respect to the corresponding switching instants of the S2-S3 pair. In this phase-shift control, the output voltage is zero when the phase shift is zero and is maximum when phase shift is 1800, i.e., TS/2. Similarly, combining variable switching-frequency control and phase-shift control provides low THD and a wide ZVS range as well as a narrow switching frequency range over the entire load and input range.

It should also be noticed that coupled inductor LC plays a major role in attenuating the output common-mode noise. Moreover, because of the presence of coupled inductor LC, a parallel operation of rectifiers is also possible.

S3

S4

S1

S2

Ts

tOFFON

tOFFON

tOFF ON

tOFF ON

td

(a)

S 3

S 4

S 1

S 2

Ts

tOFFON

tOFFON

tOFF ON

tOFF ON

DTs

DTs

td

(b)

S3

S4

S1

S2

Ts

tOFFON

tOFFON

tOFF ON

tOFF ON

tdDTs

DTs

(c)

Fig. 2. Gating waveforms of switches S1 – S4: (a) frequency control; (b) pulse-width-modulation (PWM); (c) phase-shift PWM.

944

III. ANALYSIS OF OPERATION Figure 3 shows a simplified model of the circuit in

Fig. 1 along with reference directions of currents and voltages. To simplify the analysis of operation, it is assumed that ripple voltages of the input and output filter capacitors shown in Fig. 1 are negligible so that the voltage across the input and output filter capacitors can be represented by constant-voltage source VAN, VBN, VCN, VO1, and VO2. Also, it is assumed that in the on state, semiconductors exhibit zero resistance, i.e., they are short circuits. However, the output capacitances of the switches are not neglected in this analysis. Coupled inductor LC in Fig. 1 is modeled as a two-winding ideal transformer with magnetizing inductance LM and leakage inductances LLK1 and LLK2. It should be noted that the average voltage across flying capacitor CR is equal to output voltage VO = VO1 + VO2 and the average voltage across clamping capacitor CC is equal to one half of output voltage VO. The circuit diagram of the simplified rectifier is shown in Fig. 3. The reference directions of currents and voltages in Fig. 3 correspond to the 60-degree segments of a line cycle when VAN > 0, VBN < 0, and VCN < 0.

To further facilitate the explanation of the operation, Fig. 4 shows topological stages of the circuit in Fig. 3 during a switching cycle, whereas Fig. 5 shows the power-stage key waveforms. As can be seen from the gate-drive timing diagrams of switches S1 - S4 in Fig. 5, the control used in this explanation is a combination of variable-frequency control and phase-shift control. In Fig. 5, switches S1 and S4 and switches S2 and S3 operate in a complimentary fashion with a short dead time between their commutation instants, i.e., with a fixed duty ratio of approximately 50%. This gating strategy enable ZVS of the switches that are about to turn on. The output-voltage regulation is primarily done by frequency control, except at light loads and/or high input voltages where phase-shift control is used.

As shown in Figs. 4(a) and 5, before switch S2 is turned off at t=T1, inductor current iL1 flows through switches S1 and S2. The slope of inductor current iL1 is equal to VAN/L1 and the peak of the inductor current at t=T1 is approximately

S1

AN)PK(1L DT

LVI ×= , (1)

where VAN is the line-to-neutral voltage and TS is the switching period. Because the dead time between turn-off of switch S1 and turn-on of switch S4 is very small in comparison with switching period TS, the effect of the dead time is neglected in Eq. (1). During the time period between T0 and T1, current iO1 decreases at a rate of -VO1/(LM+LLK1) while current iO2 increases at a rate of (VCR-VO1)/(LM+LLK2). Magnetizing current iM is the difference between currents iO1 and iO2. It should be noted that the magnetizing inductance value of coupled inductor LM is designed to be sufficiently large so that the ripple current of the coupled inductor does not significantly affect rectifier operation. As shown in Fig. 1, the two windings of inductor LC are coupled in such a way as to cancel the magnetic fluxes from the differential current of the two windings so that the large magnetizing inductance can be obtained by a small gap in the core without saturation. Since the effect of the current ripple of currents iO1 and iO2 is negligible, they are not further discussed, although they are shown in the topological stages in Fig. 4.

At t=T1, when switch S2 is turned off, inductor current iL1 starts charging the output capacitance of switch S2, as shown in Fig. 4(b). Because the sum of the voltages across switch S2 and switch S3 is clamped to clamping capacitor voltage VCC, the output capacitance of switch S3 discharges at the same rate as the charging rate of the output capacitance of switch S2. This period ends when the output capacitance of switch S2 is fully charged and clamping diode DC1 starts to conduct at t=T2, as shown in Fig. 4(c) and Fig. 5. After t=T2, switch S3 is turned on with ZVS.

Because clamping diode DC1 is forward biased, inductor current iL1 begins to linearly decrease. The slope of inductor current iL1 is equal to (VAN-VO1)/L1 and the inductor current at t=T3 is approximately

( )S

1

1OAN3Tt1L T

L2VD21Vi ×−−== , (2)

At t=T3, when switch S1 is turned off, inductor current iL1 starts charging the output capacitance of switch S1, as shown in Fig. 4(d). Because the sum of the voltages across switch S1 and switch S4 is clamped to the voltage difference between flying capacitor voltage VCR and clamping capacitor voltage VCC, the output capacitance of switch S4 discharges at the same rate as the charging rate of the output capacitance of switch S1. This period ends when the output capacitance of switch S4 is fully discharged and the anti-parallel body diode of switch S4 starts to conduct at t=T4, as shown in Fig. 4(e) and Fig. 5. At t=T5, switch S4 is turned on with ZVS and inductor current iL1 is commutated from the antiparallel body diode of switch S4 to the switch, as illustrated in Fig. 4(f). Because the body diode of switch S4 is forward biased and switch S3 is on, inductor currents iL2 and iL3 begin to linearly increase after t=T4. At t=T5, switch S4 is turned on with ZVS and inductor currents iL2 and iL3 are commutated from the antiparallel body diode of switch S4 to the switch, as illustrated in Fig. 4(f). This period ends when inductor

L 1

L 2

D1

i L1

V BN

D5

V O1

V O2

CR

N 1

L M

i L2

i O1

i O2

i DC1 V AN

V CN

L 3 D6 i L3

N

N 2

L LK1

L LK2

i M

O V +

S1

S2

i S1

i S2

S3

S4

i S3

i S4

DC1

DC2

i DC2

V CR

V CC CC

Fig. 3. Simplified circuit diagram of proposed three-phase boost power

stage showing reference directions of currents and voltages. The model is valid for 600-segment where VAN > 0 and VBN < VCN < 0.

945

current iL1 decreases to zero at t=T6. To maintain DCM operation, minimum voltage VCR (MIN) across “flying” capacitor CR, which is equal to output voltage VO, is

( ) RMS,LL)PK(AN

)MIN(CR VD13

2D1

VV −×

−=

−= (3)

where VAN-PK is the peak line-to-neutral voltage. It also should be noted that because during the T4-T6

interval inductor currents iL2 and iL3 flow in the opposite direction from inductor current iL1, the average current through switches S3 and S4 is reduced so that the switches in the proposed rectifier exhibit reduced power losses.

i L1

i O1

V BN

V O1

V O2

V CR V AN

V CN

NO V

+

i O2

V CC

i O i O1

i O2

V BN

V O1

V O2

V CR V AN

V CN

NO V

+V CC

i O

i L1 i O1 i L1

i O2

i O

V BN

V O1

V O2

V CR V AN

V CN

NO V

+V CC

(a) [T0-T1] (b) [T1-T2] (c) [T2-T3]

V BN

V O1

V O2

V CR V AN

V CN

NO V

+V CC

i O1

i O2

i O

i L1

i O2

i L1

i L3

i L2

i O

i O1

V BN

V O1

V O2

V CR V AN

V CN

NO V

+V CC

i O2

i L1

i L3

i L2

i O

i O1

V BN

V O1

V O2

V CR V AN

V CN

NO V

+V CC

(d) [T3-T4] (e) [T4-T5] (f) [T5-T6]

i O2

i O1

i L3

i L2

V BN

V O1

V O2

V CR V AN

V CN

NO V

+i O

V CC

i O2

i L2

i O

V BN

V O1

V O2

V CR V AN

V CN

NO V

+V CC

i O1

i L3

i O2

i O1

i L3

i L2

i O

V BN

V O1

V O2

V CR V AN

V CN

NO V

+V CC

(g) [T6-T7] (h) [T7-T8] (i) [T8-T9]

i O2

i O1

i L2

i O

V BN

V O1

V O2

V CR V AN

V CN

NO V

+V CC

i O2

i O1

i L2

i O

V BN

V O1

V O2

V CR V AN

V CN

NO V

+V CC

i O1

i O2

i L1

i L2

i O

V BN

V O1

V O2

V CR V AN

V CN

NO V

+V CC

(j) [T9-T10] (k) [T10-T11] (l) [T11-T12]

i O1

i O2

i L1

i L2

V BN

V O1

V O2

V CR V AN

V CN

NO V

+i O

V CC i O1

i O2

i L1

V BN

V O1

V O2

V CR V AN

V CN

NO V

+i O

V CC

(m) [T12-T13] (n) [T13-T14]

Fig. 4. Topological stages of proposed rectifier when VAN > 0, VBN < 0, and VCN < 0.

946

During the time period between t=T6 and t=T7, inductor currents iL2 and iL3 continue to flow through switches S3 and S4, as illustrated in Fig. 4(g). As shown in Fig. 5, the slopes of inductor currents iL2 and iL3 during this period are equal to -VBN/L2 and -VCN/L3, respectively. The peaks of the inductor currents at the moment when switch S3 turns off at t=T7 are approximately

S2

BN)PK(2L DT

LVI ×−= and (4)

S3

CN)PK(3L DT

LVI ×−= . (5)

As it can be seen in Eqs. (1), (4), and (5), the peak of each inductor current is proportional to its corresponding input voltage as long as duty cycle D and switching period TS are constant during one half of the line cycle.

After switch S3 is turned off at t=T7, inductor currents iL2 and iL3 start to simultaneously charge the output capacitance of switch S3 and discharge the output capacitance of switch S2, as shown in Fig. 4(h). This period ends at t=T8 when the output capacitance of switch S3 is fully charged and clamping diode DC2 starts to conduct at t=T8, as shown in Fig. 4(i) and Fig. 5. After t=T8, switch S2 is turned on with ZVS.

Because clamping diode DC2 is forward biased, inductor currents iL2 and iL3 begin to linearly increase. This period ends when inductor current iL3 reaches zero at t=T9. The slopes of inductor currents iL2 and iL3 are equal to (-VBN+VO2)/L2 and (-VCN+VO2)/L3, respectively. Inductor current iL2 at t=T10 when switch S4 turns off is approximately

( )S

2

2OBN10Tt2L T

L2VD21Vi ×−+−== . (6)

At t=T10, when switch S4 is turned off, inductor current iL2 starts charging the output capacitance of switch S4, as shown in Fig. 4(k). Because the sum of the voltages across switch S1 and switch S4 is clamped to the voltage difference between flying capacitor voltage VCR and clamping capacitor voltage VCC, the output capacitance of switch S1 discharges at the same rate as the charging rate of the output capacitance of switch S4. This period ends when the output capacitance of switch S1 is fully discharged and the anti-parallel body diode of switch S1 starts to conduct at t=T11, as shown in Fig. 4(l) and Fig. 5. At t=T12, switch S1 is turned on with ZVS and inductor currents iL2 is commutated from the antiparallel body diode of switch S1 to the switch, as illustrated in Fig. 4(m). Because switches S1 and S2 are on, inductor current iL1 begins to linearly increase after t=T11. During period T12-T13, increasing inductor current iL2 continues to flow through switches S1 and S2, as shown in Fig. 4(m). Finally, after inductor current iL2 reaches zero at t=T13, a new switching cycle begins, as shown in Fig. 4(n).

Since in the circuit shown in Fig. 1 the charging current of each boost inductor during the time when the related switch is on is proportional to its corresponding phase voltage and its discharging current proportional to the difference of “flying” capacitor voltage VCR and the corresponding phase voltage, as shown in the inductor-current waveforms in Fig. 5, average inductor current <IL (AVG)>Ts of each boost inductor during a switching cycle is

×=L32

TI STs)AVG(L

( )⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

ω−

−−ω×+

−

−

tsinV2V

V)D21(tsinV2VD412

RMS,NLCR

2CR

2RMS,NLCR

2

, (7)

where L= L1=L2=L3, and ω is the angular frequency of the line voltage. For maximum duty cycle DMAX=0.5, average inductor current <IL (AVG)>Ts, D=0.5 of each boost inductor during a switching cycle is

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

ω−

ω×=

−

−= tsinV2V

tsinV2VL8

TIRMS,NLCR

RMS,NLCRS5.0D,Ts)AVG(L . (8)

By defining input-to-output voltage conversion ratio M as

RMS,NL

O

V2VM

−= (9)

and recalling that the voltage across flying capacitor CR is equal to output voltage VO, i.e., VCR =VO, average inductor current <IL (AVG)>Ts in Eq. (7) can be rewritten as

t

i L3

t

t1

t

t6 t10 t2 t3 t0 t4 t5 t7 t8

i L2

i S1

T S S1

t

VS1

i L2 i L3

i L1

t

S2

ZVS

i L1 VAN L 1 L 1

VAN -VCR

-VBN L 2

L 2

VCR -VBN

-VCN L 3

L 2

VCR -VBN VAN L 1

+

S4 S1 S1 S4 S4

S3

ON ON ON ON

S3 S3 S2 ON ON S2 ON ON

t9 t11 t13

DTS

-V /2 L 1

VAN O

+V /2 L 2

-VBN O+V /2

L 3

-VCN O

t

VS2 ZVS VO 2

VO 2

VCR -

t

VLC

-VO 2

VO 2

VCR -

VAN L 1

-V /2 L 1

VAN O

t

i S2 VAN L 1

t

i Dc1-V /2

L 1

VAN O

t12 t14

L 2

VCR -VBN VAN L 1

+

Fig. 5. Key waveforms of proposed rectifier when VAN > 0, VBN < 0, andVCN < 0.

947

( )⎟⎟⎠

⎞⎜⎜⎝

⎛

ω−−−ω+=

tsinMM)D21(tsinD412

L32TVI

22SO

Ts)AVG(L , (10)

i.e., for D MAX =0.5,

⎟⎠⎞

⎜⎝⎛

ω−ω=

= tsinMtsin

L8TVI SO

5.0D,Ts)AVG(L . (11)

The current distortion of the average inductor current in Eq. (11) is brought about by the denominator term (M – sinωt) and it is dependent on voltage-conversion ratio M. It should be noted that the current distortion of the average inductor current is also dependent on duty cycle D if duty cycle D is less than 0.5 as shown in Eq. (10).

Figure 6 shows calculated average boost inductor current <IL-AVG>Ts with duty cycle D=0.5, D=0.2, and D=0.1 for various input-to-output voltage conversion ratios M. The harmonic content of the average inductor currents shown in Fig. 6 is summarized in Table I. As can be seen from Table I, the 3rd harmonic is the dominant distortion component. However, since in the three-wire power systems, the neutral wire is not available (or not connected) the line currents cannot contain the triplen harmonics (the 3rd harmonic and the odd multiples of the 3rd harmonic). As a result, the proposed circuit exhibits a very low THD and high PF since according to Table I the remaining harmonics contribute less than 3% of total current distortion up to D=0.2. It should be noted that since the line currents cannot contain the third harmonic, the 3rd harmonic of the inductor currents flow through filter capacitors C1-C3.

Finally, it should be noted that the proposed rectifier automatically balances the voltages across the two output capacitors, i.e., no additional voltage-balancing circuit is required. Natural voltage-balancing is achieved because in the circuit in Fig. 1 the average voltages across serially connected switch pairs S1-S2 and S3-S4 are equal to average voltages VO1 and VO2 across capacitors CO1 and CO2, respectively, since the average voltages across the windings of inductor LC are zero. The switch pairs are operated symmetrically and their average voltages are equal to VCR/2 so that VO1 = VO2 =VCR/2.

IV. EXPERIMENTAL RESULTS The performance of the proposed rectifier was evaluated

on a 6-kW prototype circuit that was designed to provide an 800-V output from a three-phase 340-520 VL-L, RMS input that covers the standard input range of 380-480 VL-L, RMS with 10% margin. Figure 7 shows the power-stage schematics of the experimental prototype circuit along with component information.

Figures 8(a) and (b) show the measured input-current waveforms of the experimental circuit operating at full power from 340 VL-L, RMS and 520 VL-L, RMS input, respectively. The measured THDs of the input current are approximately 0.75% and 2.9% at 340-VL-L, RMS and

M = 2.8

L=89 μH, VO=780 V, fL=50 Hz, PO=6 kW

M = 1.8M = 2

M = 2.2

M = 2.6

<IL>Ts

[A]

M = 2.4

Time [second]

D = 0.5

(a)

M = 2.8

L=89 μH, VO=780 V, fL=50 Hz, PO=6 kW

M = 1.8M = 2

M = 2.2

M = 2.6

<IL>Ts

[A]

M = 2.4

Time [second]

D = 0.2

(b)

M = 2.8

L=89 μH, VO=780 V, fL=50 Hz, PO=6 kW

M = 1.8

M = 2

M = 2.2

M = 2.6

<IL>Ts

[A]

M = 2.4

Time [second]

D = 0.1

(c)

Fig. 6. Calculated average boost inductor current <IL-AVG>Ts for various input-to-output voltage conversion ratios M and: (a) D=0.5; (b)D=0.2; (c) D=0.1.

TABLE I THD and harmonics of average boost inductor currents shown in Fig. 6.

M

D=0.5 D=0.2 D=0.1

THD [%]

3rd

[%] 5th-99th

[%] THD [%]

3rd

[%] 5th-99th

[%] THD [%]

3rd

[%] 5th-99th

[%]

1.8 14.93 14.75 1.14 25.04 24.27 1.81 40.21 36.98 8.16

2 12.64 12.53 0.67 24.08 23.38 2.06 40.52 36.92 10.56

2.2 10.97 10.9 0.6 23.44 22.79 2.1 39.28 35.55 11.26

2.4 9.7 9.65 0.72 22.84 22.25 1.58 35.0 31.97 11.04

2.6 8.7 8.66 0.78 22.11 21.57 1.85 28.45 26.84 6.87

2.8 7.89 7.85 0.81 21.15 20.65 2.11 23.9 23.0 4.26

948

520-VL-L, RMS, respectively. Figure 9 shows the measured current waveforms of boost inductors L1, L2, and L3 at full power. The measured waveforms and the ideal waveforms in Fig. 5 differ during the time intervals when the inductor currents are supposed to be zero. This difference is caused by the parasitic resonance of the junction capacitances of the reverse-biased input bridge diodes with the boost inductors. This ringing current affects the THD of the input current. However, even with these non-ideal input bridge diodes D1-D6, the measured THD was well below 5% over entire input voltage and load range. By selecting diodes with smaller junction capacitances, the quality of the input currents can be improved further.

Figure 10 shows the full-power waveforms of the drain current of switches S1 and S2, as well as the waveform of current iDC1 that flows through clamp diode DC1. It can be

L 1

L 2

L 3

D1 D2 D3

D4 D5 D6

V O

+ V A

V B

V C

S2

S3

C1 C2 C3

L C CO1

CO2

CR

N

S1 DC1

S4

DC2

CR4 x1uF/875 V

D1-D6 C4D20120D

S1 - S4IPW65R041CFD

L1, L2, L3PQ50/50-3C96

Litz 0.1mmx400 36T, 89 uH

C1-C32.2uF/630 V

Lc : ETD59-3C96Litz 0.1mmx200,

55T:55TLm=1.2 mH, Llk=347uH

4x470uF/450 V

4x470uF/450 V

Dc1, Dc2 RHRP1560

1.2nF/1kV

1.2nF/1kV

1.2nF/1kV

1.2nF/1kV

CC

1uF/875 V

Fig. 7. Experimental prototype circuit of proposed rectifier.

VIN=340 VL-L, VO=789 V, PO=5.9 kWfS=40 kHz, η=96.4%, PF=0.9996

iA

iB

iC

iA[20 A/div]

iB[20 A/div]

iC[20 A/div]

THDA=0.75%

THDB=0.72%

THDC=0.68%

5 msec/div

(a)

VIN=520 VL-L, VO=823 V, PO=5.9 kWfS=87 kHz, η=98.2%, PF=0.9951

iA

iB

iC

iA[20 A/div]

iB[20 A/div]

iC[20 A/div]

THDA=2.90%

THDB=2.76%

THDC=2.58%

5 msec/div

(b)

Fig. 8. Measured input-current waveforms at full power for three-phase line-to-line RMS input voltage: (a) 340 VL-L; (b) 520 VL-L. Time scale is 5 mS/div.

iLa

[20 A/div]

iLb

[20 A/div]

iLc

[20 A/div]

iLa

iLc

iLb

VIN=340 VL-L, VO=789 V, PO=5.9 kW, fS=40 kHz

5 μsec/div

(a)

iLa

[20 A/div]

iLb

[20 A/div]

iLc

[20 A/div]

iLa

iLc

iLb

VIN=520 VL-L, VO=823 V, PO=5.9 kW, fS=87 kHz

2 μsec/div

(b)

Fig. 9. Measured waveforms of inductor currents iL1, iL2, and iL3 at fullpower for three-phase line-to-line RMS input voltage: (a) 340 VL-L;(b) 520 VL-L.

iS1

[50 A/div]

iS2

[50 A/div]

iDC1

[10 A/div]

iS1

iDC1

iS2

VIN=340 VL-L, VO=789 V, PO=5.9 kW, fS=40 kHz

5 μsec/div

(a)

iS1

[20 A/div]

iS2

[20 A/div]

iDC1

[20 A/div]

iS1

iDC1

iS2

VIN=520 VL-L, VO=823 V, PO=5.9 kW, fS=87 kHz

2 μsec/div

(b)

Fig. 10. Measured waveforms of drain currents iS1 and iS2 of switches S1 andS2 and current iDC1 of clamp diode DC1 at full power for three-phaseline-to-line RMS input voltage: (a) 340 VL-L; (b) 520 VL-L.

949

seen that the drain currents of switches S1 and S2 start to flow in the negative direction, which indicates that the body diodes of switches S1 and S2 are conducting and the voltages across the switches are zero before gating. The waveforms of

S3 and S4 are similar to those of switches S1 and S2. Figure 11 shows the waveforms of the drain voltages of switches S1 - S4. It can be seen that all the switch voltages are well clamped to one half of output voltage VO. Finally, the measured efficiencies of the proposed rectifier as a function of the output power for 380 VL-L, RMS and 480 VL-L,

RMS input are plotted in Fig. 12. The measured full-load efficiency at 480 VL-L, RMS is 98.1%, whereas the full-load efficiency at 380 VL-L, RMS is 97.2%.

V. SUMMARY In this paper, a new three-phase four-switch three-level

ZVS PFC DCM boost rectifier has been introduced. The voltage across all the switches is clamped to one- half of the output voltage. The proposed rectifier achieves less than 5% input-current THD over the entire input range and above 10% load, as well as features complete ZVS of the switches. The performance evaluation was done on a three-phase 6-kW prototype operating in the 340-520-VL-L, RMS line-voltage range. The measured input-current THD at 380 VL_L, RMS and 480 VL_L, RMS were 0.75% and 2.9%, respectively. The measured full-load efficiency was in the 97-98% range.

REFERENCES [1] E. H. Ismail and R. W. Erickson, "A Single Transistor Three Phase

Resonant Switch for High Quality Rectification," IEEE Power Electronics Specialists Conf. (PESC) Record, 1992, pp. 1341 - 1351.

[2] S. Gataric, D. Boroyevich, and F. C. Lee, "Soft-Switched Single-Switch Three-Phase Rectifier with Power Factor Correction," IEEE Applied Power Electronics Conference (APEC) Proc., 1994, pp. 738 - 744.

[3] Y. Jang and M. M. Jovanović, "Design Considerations and Performance Evaluation of A 6-kW, Single-Switch, Three-Phase, High-Power-Factor, Multi-Resonant, Zero-Current-Switching Buck Rectifier,” IEEE Int’l Telecommunications Energy Conf. Proc., 1997, pp. 715 - 722.

[4] J. R. Pinheiro and I. Barbi, “The three-level zvs-pwm dc-to-dc converters,” IEEE Transactions on Power Electronics, vol. 8, No. 4, pp. 486-492, Oct. 1993.

[5] X. Ruan, L. Zhou, and Y. Yan, “Soft-switching pwm three-level converters,” IEEE Trans. Power Electronics, vol. 16, no. 5, pp. 612 – 622, 2001.

[6] P. M. Barbosa, F. Canales, J. M. Burdio, and F. C. Lee, “The three-level converter and its application to power factor correction,” IEEE Transactions on Power Electronics, vol. 20, No. 6, pp. 1319-1327, Nov. 2005.

[7] Y. Jang and M. M. Jovanović, “The Taipei rectifier – a new three-phase two-switch zvs pfc dcm boost rectifier,” IEEE Transactions on Power Electronics, vol. 28, No. 2, pp. 686-694, Feb. 2013.

[8] Y. Jang, M. M. Jovanović, Y. H. Chang, K. H. Fang, and J. X. Zhu “Design Considerations and Performance Evaluation of Three-Phase Two-Switch ZVS PFC DCM Boost Rectifier (Taipei Rectifier) for Telecom Applications”, Record of the 34th IEEE International Telecommunications Energy Conference, Scottsdale, Arizona, Sep. 30 - Oct. 4, 3-2, 2012.

VS1

[500 V/div]

VS2

[500 V/div]

VS3

[500 V/div]

VS4

[500 V/div]

VS1

VS2

VS3

VS4

VIN=340 VL-L, VO=789 V, PO=5.9 kW, fS=40 kHz

4 μs/div

(a)

VS1

[500 V/div]

VS2

[500 V/div]

VS3

[500 V/div]

VS4

[500 V/div]

VS1

VS2

VS3

VS4

VIN=520 VL-L, VO=823 V, PO=5.9 kW, fS=87 kHz

2 μs/div

(b)

Fig. 11. Measured full-power waveforms of switch voltages VS1, VS2, VS3,and VS4 for three-phase line-to-line RMS input voltage: (a)340 VL-L; (b) 520 VL-L.

1.2 2 3 4.5 6

Output Power [kW]

94

95

96

97

98

99

Effic

ienc

y [%

]

V =800 VO DC

V = 380 VIN L-L, RMS

V = 480 VIN L-L, RMS

Fig. 12. Measured efficiencies of experimental prototype as functions ofoutput power.

950