The IC/System Implementation Challenges for Future Applications

莊英宗 Ph.D, Deputy Director

TSRI/NARL

25/3, 2021

Outline

TSRI簡介

人工智能與晶片技術發展

晶片技術發展挑戰

Conclusions

MOST

President

Board of Directors

Vice President

Headquarter Laboratories

Human Resources Office

Administration Office

Finance & Accounting Office

Planning & Evaluation Office

Business Development Office

Auditing Office

National Center for High-performance Computing (NCHC)

National Center for Research on Earthquake Engineering (NCREE)

National Laboratory Animal Center (NLAC)

National Space Organization (NSPO)

Science & Technology Policy Research and Information Center (STPI)

Taiwan Instrument Research Institute (TIRI)

Taiwan Ocean Research Institute (TORI)

Taiwan Semiconductor Research Institute (TSRI)

Organization of NARLabs

• Post-Si chip technologies that cover cutting-edge CMOS/MEMS (bio/photonic) sensor

• Heterogeneous integration for IoTs

• Wearable electronics • Biochips

Logic Device

Memory Device

Sensor

FinFET(3D) Nanowire/GAA

Small scale circuit

Ge(Sn), III-V, 2D, Graphene

4

DO V DD

V SS

DL

DO_B DL_B

SW

SAEN

The Trend of Semiconductor Moore’s Law

SiPh

1988 – National Sub-micron Device Laboratories Founded

1988

1992 – National Chip Implementation Center (CIC) Founded

1992

2002 – Renamed National Nano Device Laboratories (NDL)

2002 2003

2003 – Affiliated to NARLabs

2018 – CIC+NDL Joint Operation

30 Anniversary

Taiwan Semiconductor Research Institute(TSRI) (CIC+NDL)

2019 2018

台灣半導體研究中心

引入業界應用及人才培育需求：台積電、聯電、旺宏、友達、茂迪、光寶、富士康、奇景光電、光程、創王、奈米碳素、宜特、Apple台灣分公司、台中榮總、成大醫院…等團隊

先進的半導體製造研究環境

完整的晶片/系統 設計與下線製作服務 引入業界應用及人才培育需求：Synopsys、NVIDIA、Cadence、ARM…等研究團隊

tsmc 0.35m CMOS

tsmc 0.18m CMOS

tsmc 90nm CMOS

tsmc 40nm CMOS

tsmc 28nm CMOS

tsmc 16nm FinFET

tsmc 0.18um HV CMOS

tsmc 0.5um UHV CMOS

tsmc 0.18m SiGe BiCMOS

UMC 0.18m CMOS

UMC 0.18m CMOS MEMS

Multi-Optional MEMS

WIN 0.15m GaAs pHEMT

WIN 0.25m GaN HEMT

GaN-on-Si

Si-Photonic

基礎設施及服務

半導體中心台南基地 半導體中心新竹基地

Class 10-10,000 Clean Room (~3200m2) (24 hours) 協助國內超過50所大學院校、550個以上教授研究群從事先進半導體技術研究

Outline

TSRI簡介

人工智能與晶片技術發展

晶片技術發展挑戰

Conclusions

Smart City – Better Life to Future

2018 CES宣稱是 IoT元年, but!?

Google、Amazon、IBM

What is the important showcase?!

Watson or Alexa

晶片系統商走弱 軟體社群公司做晶片 晶片商轉型設計代工

Big Data

端點AI

現階段/未來ICT技術圖譜

異質運算核心

模組化AI學習平台

Smart home Health care

Smart Energy 電競/視聽娛樂 自駕及無人載具

PC、平板… Wearable

AR/VR/ADAS AI Robot

Smart Charger (整合MEMS/PIC/特殊材料)

BT/OIO 5G/6G Wireless 高效能近距 (整合SiPh、GaN)

Cloud Services

Intel、IBM Nvidia、MTK…

Apple、 Samsung…

Amazon、 Google…

T bps optical link 高效能長距

利基型機器學習

48/380V to home 綠電系統

Smart Energy (整合GaN/SiC)

QC、DS(OIO) 6G/LiFi (整合SiPh/GaN/ Cryo CMOS)

未來晶片應用發展挑戰 AIoT發展需求

Multi-sensor integration

Chiplet solution for AIoT

硬體資安/CIM for AI

自駕/電動車快速發展 Compact LiDAR solution

IR/SPAD、GaN/SiC

Smart Energy High reliability FI GaN-on-Si

光電整合技術 銅導線傳輸限制/OIO

Optical Interposer for EIC/PIC、光源整合微模組技術

5G/6G Cold CMOS/High performance RF FinFET

MW/THz power module、Low K材料/天線模組整合

量子技術發展 Cryo CMOS/量子電路系統架構及IP

低應力/適用於低溫系統及特殊材料之異質整合技術

物聯網智慧終端需求 • For future smart world there are trillion AIoT devices

• 不同智慧感測晶片系統有不同的感測器及電路系統需求，沒有

標準規格

新創事業 新興應用 創新產品

智慧耳機

智慧螺絲

工廠監控

神經刺激器

氣體感測

智慧牙套

Source: ITRI, TDK-Micronas , web 12

物物聯網的三大關鍵

高速、寬頻通訊網絡

Service oriented wire/wireless network

便利AIoT元件整合開發

Chiplet like/Multi-chip IP

軟硬體資安有效解決方案

Centralized/distributed

14

感測器及低功耗感測系統電路IP

需求: 光機電感測、省電、系統微小化、客製化

微模組化及系統電路IP技術

Source: ICSense

光機電感測器IP

低功耗讀取電路IP

類比數位轉換電路IP

處理器及RF電路IP

電源管理及獵能IP

A D

處理器

記憶體

無線傳輸

動作 感測器

環境 感測器

電源管理

環境 感測器

動作感測器 處理器 記憶體

無線傳輸 電源管理

TSMC System Integration

3DFabric

Source; TSMC

Focus Issues of HIR Roadmap 2019

HI for Market Applications Design

High Performance Computing and Data Center Co-Design

Mobile Simulation

IoT Cross Cutting topics

Medical, Health and Wearables Materials & Emerging Research Materials

Automotive Emerging Research Devices

Aerospace & Defense Supply Chain

Heterogeneous Integration Components Security

Single Chip and Multi Chip (including substrates) Thermal Management

Integrated Photonics Test

Integrated Power Electronics Integration Processes

MEMS and Sensor Integration SiP and Module

RF and Analog Mixed Signal 3D & Interconnect

WLP (fan in and fan out)

• IEEE announced HIR on Oct. (IEEE Electronic Packaging Society)

Source: HIR 2019

17

TSRI CoCoP for AIoT

特殊材料、先進製程、光機電感測元件

EDA整合驗證環境

高效能介面驗證

IPD/2.5D/TSV

Sensor/Memory on CMOS

SiPh w Optical Interposer

All GaN Platform TSRI Interposer

PCB/SiP

GaN Platform

磁性材料

Advance memory Gas sensor

CMOS MEMS Platform Advance

IPD/interposer

PCB/SiP SiPh Platform

Sensor/Memory on CMOS

SiPh Platform GaN Platform

Advance IPD

Platform

2020 2021 2022

2.5D

Integration

Circuit

Application

Example

TSRI 2.5D/3D Integration Roadmap

5um Cu RDL,

150 μm bump

4.5 fF/μm2, 5um Cu

(AIPD)

4.5 fF/μm2,5 μm Cu,w/ TSV

0.35-μm backend, w/ TSV 40 μm μbump

Readout, Temp. control

IoT, optical detection,

GaN power module

Gas sensor w/ readout

& T.C. ckt chip module

Readout, Temp.

control, MCU, memory

Multi-sensor IoT,

good power integrity

Gas/humidity sensor with

calibration

Readout, Temp. control,

MCU, memory, RF, AI

Wireless AIoT

Food or environmental

monitor chip module

INFO w/ TIV

0.35-μm backend, w/ TSV w/ AIPD

Comparisons

2.5D/3D Platform Comparison

InFO

CoWoS

SoIC

CoWoP

AIoT, Prototype HPC, Mobile

2.5D

3D

Source: TSMC, Europractice, CMP

Why silicon photonics?

21

Transmitter ( light source, coupling, modulation, …) Receiver (PD, ..)

Optics Since 90’s Metro & Long Haul 0.1 – 80

km

Optics Since2000

Rack to Rack 1 to

100m

Optical

• Except for the light source, all other components can be presented using silicon photonics technology

Current step

Board to Board 50 – 100cm

Chip to Chip

1 – 50cm Optics

beyond

Billions

Thousands

Vo

lum

es

Millions

Courtesy: Intel Decreasing Distances ->

• Silicon photonics supports artificial intelligence (AI), Internet of Things (IoT), 5G,…

Cladding Core Laser EIC integration

High bit rate Power efficiency

Form factor

IPD製程整合多感測晶片模組 • 完成包含微型線圈及整流器電路之無線能量擷取晶片

• 完成TSMC 0.18 m及UMC 0.18 m測試晶片與IPD整合試做，大小約0.9x1 cm2

TSRI CONFIDENTIAL - P.22

自主供電無線傳輸感測晶片模組

UMC 0.18 m 晶片

TSMC 0.18 m 晶片

2.5D Gas Sensor & Readout/Temp. Control Chip Integration • Sensing chip integration module (6x6 mm2)

interposer

Gas sensor

IC

Silicon Photonics PIC and EIC Integration

1. silicon photonics 400Gbit/s 3. Flip chip integration 2. High-speed EIC TX/RX

4. Packaging

24 Target: 400Gbps, 4Channel, with silicon photonics PIC and EIC integration chip

25

Device technology

SOI, 220nm 製作環境建置 設計能量

整合技術開發

TSRI 自主Silicon Photonic開發

TSRI silicon photonic technology and service platform

grating edge O/E test

Chip implementation environment and tape

out service

Include EDA/Testing/Design More than 8 Silicon photonics training

courses

Complete optical coupling technology and optoelectronic

chip performance test environment

From components to system application

design environment

26

56Gb/s PAM4 optical RX testing

1

2

3

4-1

4-2

BER 10-4 BER 10-4 IEEE, 100GBASE-LR4, 4 SM Fibers, 10km – 40km, 4x25.78125 Gb/s, ≤ 10-12

BER 10-12

Competing QC Platforms

Source: T. Meunier , ESSCIRC (2020)

• Top three qubit technologies addressed by NAS in 2019: – Trapped ions

– Superconductor

– Photons

Quantum Computing:Key Concepts

Source: Intel

Quantum Supremacy • Google: Quantum supremacy using a programmable

superconducting processor (Oct. 23th, ‘19).

• Sycamore with 54 transmon qubits (one fail, 53 qubits (253 ≈ 9 × 1015)

• Sample the resulting probability distribution: 200 sec vs. 10,000 years

(classical, Summit)

• IBM disagreed: 2.5 days by adding the memories

https://www.nature.com/articles/s41586-019-1666-5

現階段量子系統架設方式

32

Cryo-CMOS控制電路次系統

量子位元晶片

• 單一量子位元即需要一條(或以上)的微波控制線路，目前微波線路由系統外(室溫)拉至系統中(極低溫)，將無法實現大規模量子電腦(超過百萬位元)

• 故不論量子位元平台為何，皆需要微型微波晶片，能提供多工(分時或分頻)且能在低溫下運作(以減少雜訊、延遲等)

量子運算單元

33

One-qubit gate (rotation) + Two-qubit gate (CNOT)

• 2 qubit 是實現量子運算的基本單元

Building Blocks of a Quantum Computer

Source: QuTech

Classic/Quantum Hybrid

Entanglement Sub-set Control Hybrid

A Full-stack Scalable Approach to Quantum Systems

應用需求規格 1Mqbit?

系統整合

工程整合

System Architecture Study

• 基本情境

– 以十年為基礎，單晶片是不可能的選項

– 對量子系統整合而言，矽基、超導、光子都需依靠異質系統整合技術

– 量子運算須結合古典運算機制，但需要全新的電路單元

– 利基型運算系統及關鍵技術才是台灣真正未來!?

Source: QuTech

System Integration

Source: https://arxiv.org/pdf/1912.01299v1, ISSCC 2020

Cryo-CMOS控制電路次系統開發 建立具拓展性的Cryo-CMOS控制電路晶片架構

37

NCO

Digital Controller

PANCO

PLLLPF IDAC

QDAC LPF

BPF

LOCLK

Control System

TIAADC

Qubits4K mK

MU

X

NCO

16 channels

• 評估多量子位元之Cryo-CMOS控制電路晶片架構，包含：分頻多工架構(FDM)和分時多工架構(TDM)

• 規劃一個控制電路可控制及驅動16個量子位元

以分頻多工架構(FDM)為例之Cryo-CMOS控制電路架構圖

Technology Integration

Source: https://arxiv.org/pdf/1912.01299v1, ISSCC 2021

1~2K For 64~128qbs Single module

3~300K For1k~1M QC

QC

Module

Sub-module

QB

Technology Integration Considerations

Source: M. Vinet et al., IEDM (2018); L.M.K. Vandersypen et al., npj Quant. Inf. (2017); M. Veldhorst et al., Nature Comm. (2017); R. Li et al., Science express (2017)

• Purposes – Micro-module

– RDL and micro-bump from QB to sub-module and module

• Issues – Form factor

– Thermal heating & cooling

– Stress

Full-Scale 量子電腦探索：~ 2030?

40

台灣 IBM/Google

超導體

UNSW

半導體

Outline

TSRI簡介

人工智能與晶片技術發展

晶片技術發展挑戰

Conclusions

學校

技術加值

42

產學研整合及產業開發新思維 • 從垂直分工到網絡分工

– 產業 : 量產技術及整合營運、法人 : 多平台整合、學界 : IP及新創驗證

• 從量產獲利模式到創新服務獲利模式

產學技術

聯盟

國研院

異質系統整合平台

研究群:

數個學門教授及多個學研單位

數十個業界

夥伴

• 提供感測及讀取電路相關IP

• 提供業界先期開發驗證

• 整合提供產、學感測晶片系統開發解決方案

• 建構整合性CMOS及封裝製程

• Flexible IP integration & library

• 異質系統IP整合驗證平台

• 提供感測及讀取電路相關IP

• 提供整合製程及封裝之解決方案

• 提供電路系統及儀器模組整合方案

Thanks for your attention!