3D-IC Fabrication Challenges - SEMATECHsematech.org/meetings/archives/3d/8510/pres/Ramm.pdf3D-IC Fabrication Challenges for More Than Moore Applications. Armin Klumpp and Peter Ramm

Workshop Manufacturing and Reliability Challenges for 3D ICs Using TSVs, San Diego, Sept 26, 2008

Peter Ramm, Fraunhofer IZM Munich

3D-IC Fabrication Challenges for More Than Moore Applications

Armin Klumpp and Peter Ramm

Fraunhofer IZM, MunichHansastrasse 27d, 80686 Munich, Germany

[email protected]

mailto:[email protected]

Peter Ramm, Fraunhofer IZM Munich Workshop Manufacturing and Reliability Challenges for 3D ICs Using TSVs, San Diego, Sept 26, 2008

Definition:Fabrication of stacked and vertically interconnected device layers

Motivations:

Form Factor• Reduced volume and weight• Reduced footprint

Performance• Improved integration density• Reduced interconnect length• Improved transmission speed• Reduced power consumption

“More than Moore” Applications• Integration of heterogeneous technologies

3D Integration


Beyond CMOS

BiochipsFluidics

SensorsActuators

HVPowerAnalog/RF Passives

More than Moore : Functional Diversification

130nm

90nm

65nm

45nm

32nm

Λ...22nm

Mor

e M

oore

: Sc

alin

g

Baseline CMOS: CPU, Memory, Logic

Moore’s Law Scaling alone can not maintain the Progress of Smart Systems


Sensors Actuarors System in

Package

Auto-motive

Data ProcOffice

CommunicationWireline Wireless

Power

ConsumerPortable Stationary

Markets

Legend:

Technologies

RF / AMS

CMOS LP

CMOS HP

Memory

Industrial Medical

Analog / HV

Bubble size = driver impact

More Moore(scaling)

More than Moore(non-scaling)

mixed

Technologies serve different applications

Ref.: A.J. van Roosmalen, ETP Nanoelectronics, 2007


Humanbrain

Humansensing

& interaction with

environment

‘Beyond CMOS’

e-CUBES

e-CUBES®

Self organising wireless sensor networks to monitor the environment

e-CUBE

e-cube application layer(s)

e-cube radio

e-cube Power

Antenna

rf circuit

Processing unit

Radio digital baseband

Sensor Function

Power Management

Energy Scavenging(e.g. vibration,solar)

Power storage

e-CUBE

e-cube application layer(s)

e-cube radio

e-cube Power

Antenna

rf circuit

Processing unit

Radio digital baseband

Sensor Function

Power Management

Energy Scavenging(e.g. vibration,solar)

Power storage


Wireless Sensor Networks

3D Integration

Electronic Cubes– e-CUBES

Smart Dust (UC Berkeley)

3D Integrationwill enable

• Ultra Miniaturization• Low Cost Fabrication


European Commission Integrated Project “e-CUBES”


Aeronautics eAeronautics e--CUBES demoCUBES demoTHALES aeronautical

demo: carrier frequency

>15GHz, 1cm3, extreme

shock, temperature

& humidity

cds.

•• SensorsSensors::•• accelerationacceleration•• temperaturetemperature•• humidityhumidity•• pressurepressure

••

Low power electronics, Low power electronics, wakewake--up blocksup blocks•• MemoryMemory•• RF com & antennaRF com & antenna•• RechargRecharg. Battery . Battery •• Energy scavengingEnergy scavenging•• Hermetic packageHermetic package

Photo:Courtesy NASA.


––

MEMS sensorMEMS sensor––

A/D converterA/D converter––

MicrocontrollerMicrocontroller––

DSP layerDSP layer––

MemoryMemory––

RF TransceiverRF Transceiver––

AntennaAntenna––

Power supplyPower supply

EPFL’s

space

demo, self-localization and reliable long distance communics: <10cm3, 100MHz-2GHz, 100m-few km.

Falling

e-CUBES scenario

Fixed

e-CUBES scenario

Space eSpace e--CUBES demoCUBES demo


Health/fitness eHealth/fitness e--CUBES demoCUBES demoPhilips’s: volume max 0.5 cm3, through

body < 2.45GHz, no

through body: 17GHz, communication distance:1-5m, in air.

•• Sensors: Sensors: Heart rate monitorHeart rate monitorActivity monitoringActivity monitoring

•• Low power electronicsLow power electronics•• Antenna and RF interfaceAntenna and RF interface


Infineon’s TPMS demonstrator: <1cm3, 2.4GHz ISM band.

––

MEMS sensor dieMEMS sensor die––

Signal Signal conditcondit. IC. IC––

Transceiver ICTransceiver IC––

AntennaAntenna––

Power supplyPower supply

Drawing: Courtesy Infineon.

Automotive eAutomotive e--CUBES demoCUBES demo


3D Integration Technologies for e-CUBES

•

IZM-M: ICV-SLID•

(TSV Technology)3D-PLUS:

WDoD, HiPPiP, …(Stacking of Packages)

Bottom-Chip

IMEC/IZM-B: UTCS, TCI(Die Stacking without TSVs)

and more: LETI´s µ-Insert, Tyndall´s SW-ACF, SINTEF´s MEMS Integration, ...


Concept Categories:

•

Stacking of Packages(or substrates)

•

Die Stackingwithout TSVs

•

3D-IC Integration(TSV Technology, Vertical System Integration)with TSVs-

“vias last” (post thinning/stacking)-

“vias first” (prior to thinning/stacking)prior FEOL, prior BEOL, post BEOL

3D Integration Technologies


Source: Yole (Ref.: May issue “3D IC, WLP & TSV Packaging Newsletter”)


2D SoCmonolithic

Integration2D SoC

monolithic

Integration

3D ICstacked dieswith

TSVs

3D ICstacked

dieswith

TSVs

3D SiPstacked

packages

stacked

dies

without

TSVs

Per

form

ance

Per

form

ance

C o s tC o s t


Process Technology needed:

•

Robust and precise thinning process

•

Handling concept for thin Si substrates

•

Inter-Chip-Vias for electrical interconnects through thinned Si substrates (TSVs)

-

Deep via etching

-

Deep via dielectric isolation

-

Deep via metal filling

•

Suitable high efficient bonding process

•

Wafer level assembly

Requirements for TSV Technology


Bonding Approaches for 3D ICs

Chip 1

Chip 2

Chip 1

Chip 2

Adhesive

Adhesive

Chip 1

Chip 2

Direct

Oxide Bonding Direct

Metal Bonding Adhesive

Bonding

Metal

Metal


Cu - Cu Fusion Bonding

Roughness (RMS < 1.0 nm) Cleanliness ( no particulate) Flatness (< 4 µm / 200 mm wafer)Bonding Conditions = 400 °C / 30 minContact Pressure = 4000 mBarPost-Bonding Anneal: 400°C / 30 min

ILD recessed

2 μm

No seam

Wafer 1 Wafer 2

Intel

Ziptronix DBI™

CMP simultaneously polishes metal and SiO2 - no ILD recess

D2W or W2W oxide (ZiBond®) bond at ambient T & P post-bond Cu-Cu bond formation in oven anneal


Courtesy: Qimonda (Ref.: H. Hedler et al., 3D-SIC 2008, Tokyo)


Contact under pressure and heat~ 5 bar, 260 – 300 °C (Sn-melt)

Sn, liquid

Cu - interdiffusion

Formation of intermetallic compound; Tmelt > 600 °C

Cu3 SnIMC

Patterned electrodeposition

Cu

Sn

TiW

Simultaneous formation of electrical and mechanical connections

alternative approaches: SnAg, InAu

SLID: Solid-Liquid

Inter-Diffusion


•

Thin SLID layer (approx. 10 µm) providing large area metal bond

•

Modular concept•

Optimized for chip-to-wafer stacking of known good dies

Process flow

–

Post backend-of-line „vias first“ TSV process

–

Fabrication of TSVs

with standard wafer process sequence

–

Simultaneous formation of electrical and mechanical connection

Multiple Device Stacks by ICV-SLID Technology


W-filled TSV

Al

Top-Chip (17 µm)

Cu

Cu3Sn

Cu

2 µm

W-filled TSV

Al

Top-Chip (17 µm)

Cu

Cu3Sn

Cu

2 µm

Bottom Device

Al

Top-Chip (17 µm)

Cu

Cu

Cu3Sn

AlILD

12 µm

Bottom Device

Al

Top-Chip (17 µm)

Cu

Cu

Cu3Sn

AlILD

12 µm

Results of focused ion beam analysis (FIB) on chip-stack formed by ICV-

SLID technology

Cross section of ICV-SLID interconnect between bottom device-

chip and top-chip (Al on the top is used for rewiring)

Detail of Cross section ICV-SLID interconnect between bottom device-

chip and top-chip (Al-pad on the bottom chip) Armin Klumpp, Josef Weber, Robert Wieland

Fraunhofer IZM Munich


3D-IC/Sensor stack for TPMS

Microcontroller

BAR

Pressure sensor

Au stud bumps

SLID bond

RF transceiver

Source: Infineon, SINTEF and Fraunhofer IZM-M


TSV technology for automotive application (deep trench etching)

TSV

SEM of 54 µm deep TSV, 10x3 µm (nominal size) etched in product testchip of IFX

Process steps done:

- Removal of ~ 8 µm polyimide (H2 O-plasma strip)

- Removal of passivation layer (Si3 N4 ), by RIE etch

-

Deposition of O3 /TEOS planarization by SACVD

- TSV lithography, 2,7 µm resist

- Etching of ~ 2,2 µm oxides

- Etching of 6 dielectric layers of FSG/Nitride,~ 4µm thickness

- special etching due to test-chip

- 47 µm Si deep trench etch (STS Pegasus)

- H2 0 Strip

No attack of uper AlSiCu-metal (M7)

Positive taper

(Source: e-CUBES)


Post Backend-of-Line

TSV Process

DisadvantageBEOL intermetal-dielectrics

have

to be

etched

prior

to silicon

via etch

For 3D Integration of various „More than Moore“products there is no cost-effective optionComponents are usuallyavailable as completelyfabricated devices only


TSV technology for automotive application (metallization of trenches by CVD tungsten)

(Source: e-CUBES)


ACA Failure

3D-Integrated System

Thin Die Crack

Delamination

at Interfaces

Failure in Through Silicon Via

Si

10 µm

Al

W

Cu

Oxide

1.2 µm

IMC Growth,

Solder Fatigue

Fatigue Crack

at UBM

Failure Mechanisms of 3D-IC Integration

Ref.: P. Ramm, J. Wolf and B. Wunderle in „Handbook of 3D Integration“, Wiley 2008


0

50

100

150

Stre

ss [M

Pa]

STD Low T Tck Si Cu

0

1

2

3

4

Pl. S

trai

n [%

]

STD Low T Tck Si Cu

Simulation: Critical

Locations

Top: AlSiCu with SiO2 /W

ICV Centre: W or Cu with SiO2

Bottom: Cu with W/Cu3 Sn

0

50

100

150

200

Stre

ss [M

Pa]

STD Low T Tck Si Cu

High stress due to Cu filler (CTE!)

Low T process & Cu promising

no periodic plasticity

Cu promising

Ref.: P. Ramm, J. Wolf and B. Wunderle in „Handbook of 3D Integration“, Wiley 2008


Overview of Deposition Processes for Metallization of TSVs

Ref.: A. Klumpp, S.E. Schulz in „Handbook of 3D Integration“, Wiley 2008


Copper

•

Fabrication

of Tungsten-filled

Inter-Chip Vias

on Top Substrate

ILD 5-7 µm

IsolationTungsten

Plug Si 10-50 µm

Passivation•

Via Opening

and Metallization

•

Thinning

•

Opening

of Plugs

•

Through

Mask

Electroplating

•

Chip/Wafer

Alignment

and SolderingSnCu3

Sn

Chip-to

Wafer

Stacking

by

ICV-SLID Technology



-

SLID: Isothermal solidification at temperature set point; variation between melting point and up to 300 °C (Sn, mpt. 230 °C)

-

µ-bumps: Melting point of eutectic material composition e.g. 220 °C for AgSn-

Cu-Cu: Bonding temperature 200 (?) …

400 °C

Materials of interest and their thermal expansion coefficient α

[ppm

/ K] Aluminium, 25; Copper, 17; Gold, 14; Silver, 20; Silicon, 2.6; SiO2, 0.75

•

“Freezing”

of different dimensions takes place at the moment of interconnect solidification.

•

Depending on the technology, this temperature can be far above room temperature or operating temperature of the devices:

IC multilevel metallization (MLM):Metal/ILD compound (e.g. 56% dielectrics and 44% metal)

Length variation due to temperature increase

thinned Si device chip

thick Si device wafer

Mechanical Stress Issues for 3D-IC Stacks



179,21155,32125,450,5836,2210 µm

50,5743,8335,400,8753,6950 µm

Stress S [ MPa]; Young`s

Modulus Silicon: 169 GPa1,651,431,150,9862,72500 µm

0,001060,000920,000740,5836,2210 µm

0,000300,000260,000210,8753,6950 µm

Strain: Delta L / Length [5000 µm]0,000010,000010,000010,9862,72500 µm

5,304,603,710,5836,2210 µm

1,501,301,050,8753,6950 µm

calculated for chip size of 5000 µm 0,050,040,030,9862,72500 µm

Delta of expansion length [µm]0000,9902,69700 µm

320280230

process temperature [°C]relative amount of silicon

effective α

silicon thickness

•

Even at comparatively low temperatures high mechanical stress can be built into a 3D-IC stack

for comparison: mobility of electrons is at 500 MPa

increased by 15% (linear dependency from 0 to 500 MPa); ref:

Simulation of 110 nMOSFETs

with a Tensile Strained Cap Layer, F.M. Bufler; Institut für Integrierte Systeme, ETH Zürich,

•

Bonding of 3D-IC stacks at RT is favourable



Typical impact of high stress:a)

Delamination

of dielectrics (redistribution layer)b)

Delamination

of complete SLID-padc)

Local cracking of silicon substrate

a)

b)

c)

“Failure Archive”

(without process optimization)


3D Interconnects

-

Quo Vadis

?

Miniaturization

Low Temperature

- Wires-

Microbumps- Cu-Cu- SLID...

Nanoscale

enhanced structures-

Carbon

Nanotubes-

µ-Inserts

(CEA-Leti)- SW-ACF (Tyndall)-

NanoLawn

(Fraunhofer IZM)


Formation of NanoLawn

Interconnects

NanoLawn

on bothcontact

padsAligned

contact Bonding at RT

K. Neumeier, R. Wieland Fraunhofer IZM Munich


Gold NanoLawn

Contact

Pads

Au

Au

K. Neumeier, R. Wieland Fraunhofer IZM Munich


Conclusions• Motivations for 3D integration are improvement of

Form factor, integration

density

and performanceand-

Cost-effective

fabrication

of

More than Moore products

-

Enabling

of new

applications

(e. g.

ultra-miniaturized wireless sensor systems (e-CUBES))

• Diverse 3D integration

concepts

introduced• Decision

for

application

depends

on products

and costs

•

TSV is considered today as one of the

most promising, high-performance and cost-effective 3D technologies.•

More than Moore systems can show the need of mixed

approaches, taking advantage of a combination of different specific 3D integration technologies.


•

Cost is as a key driver for 3D integrated products but e.g. in case of wireless sensor systems rather

a long term one

(highly dependent on application and markets), while the performance and density of functionality are the short and/or mid term drivers.

•

Producibility and reliability of 3D fabrication processes are the basic requirements !

•

Future key challenges for 3D-IC Stacks:-

Development

of low cost fabrication

-

Fabrication and reliability issues

Conclusions (2)


Thank you

for your attention !

This report is partly based on the e-CUBES projectwhich is supported by the European Commission.Acknowledgements tothe colleagues of the e-CUBES project, especiallyT. Herndl, J. Prainsack

and W. Weber / Infineon,A. Ionescu / EPFL, M. Taklo

and N. Lietaer / SINTEF,T. Seppanen

/ Infineon SensoNor, J. Weber, R. Wieland, R. Merkel and E. Kaulfersch / Fraunhofer IZM

Documents

3D-IC Fabrication Challenges - SEMATECHsematech.org/meetings/archives/3d/8510/pres/Ramm.pdf3D-IC Fabrication Challenges for More Than Moore Applications. Armin Klumpp and Peter Ramm