Test and Diagnosis of Open Defects in Digital CMOS IC

Page 1 Jan. 28, 2002James Chien-Mo Li

Test and Diagnosis of Open Defects in Digital CMOS IC

1

enter for eliable

omputing

CRC

Test and Diagnosis of Open Defects in Digital CMOS ICs

James Chien-Mo LiDepartment of Electrical Engineering

Stanford UniversityPh.D. Orals Presentation

2

OutlineIntroductionResistive and Stuck-open Defects

TestDiagnosis

Tunneling-open DefectsTestDiagnosis

Summary

3

IntroductionOpen defects

Breaks in circuit connectionsTest

Identifying defective chipsDiagnosis

Locate failure site based on test results

4

MotivationEffective testing required

Quality guarantee Happy customers

Precise diagnosis desired Quick yield improvement

Happy boss

other defects

42% open defects

58%

58% of customer returns are open defects! [Needham 98]

5

Big Picture

Fabrication

Test

Diagnosis

Failure Analysis

Feedback for yield improvementor better test

Wafers/chips

Some Failed chips

Defect locations

Design

Passedchips Customer

Customer returns

6

Focus of This ResearchEffective test and precise diagnosis

Three classes of open defectsResistive Opens (RO)Stuck Opens (SO)Tunneling Opens (TO)

Advantest Tester



7

Defect resistance (Rdef) between nodesCracks in wiresBad vias, contacts

Failure analysis pictures

Resistive-open Defects

[Knebel 98] [Nigh 98]

Rdef

8

Stuck-open DefectsNo current path (Rdef ≈ infinity )

Broken wiresMissing vias, contacts

Failure analysis pictures [Soden 89]good Bad (broken wire)

9

Tunneling-open DefectsVery thin oxide at contact or via

incomplete etchroom temperature grown oxide

PolySiO2 SiO2

MetalTunneling Current

10

TerminologyDefect

Imperfection in ICFault

Models effect of failures on logic signalE.g. Single Stuck-at Fault (SSF)

Test setSet of test patterns

1

AB Z 01 1 10 1 11 0

A

B Z

%100×=faultstotalofnumberfaultsdetectedofnumberCoverageFault

11

ContributionsResistive and stuck-open defects

Optimal test conditions and test set [Li ITC’01]Precise diagnosis technique [Li ITC’01,VTS’02]

Tunneling-open defectsEffective test methods [Li ITC’00]

VLV and IDDQ(t) testingPrecise two-stage diagnosis [Li VTS’01]

Others (not in this presentation)IDDQ signature analysis technique [Li IDDQ’98]IDDQ(t) test pattern selection [Li VTS’01]

12


Test [Li ITC’01]Diagnosis


Summary



13

Previous WorkProblems with previous work

Test at specified speed for RO* [Needham 98]One chip only

Cold temperature for RO [Tseng 00]Only for RO in silicide

Low voltage testing for RO [Baker 99]No real data

Test set generation for SO** [Elziq 82][Cox 88]No real data

*RO = Resistive Opens**SO = Stuck Opens 14

Our GoalEvaluate test effectiveness for RO and SO

Test conditionsTest speedTest voltageTest temperature (not presented)

Test sets

15

Test Speed

16

Example CircuitSingle inverter chain

RC delay model

Rtr(VDD): transistor turn-on resistancefunction of VDD

CRVRDelay defDDtr ⋅+≅ ])([

Rdef Rtr

C

In Out

17

Example (spice simulation)TSMC 0.18 µm, Nominal VDD=1.8V, Rdef = 10KΩDelaydefective= 0.44nsDelaygood = 0.21ns

Test effectiveness metric [Chang 96a]Larger DR, more effective test

Delay Ratio (DR)

good

defective

DelayDelay

RatioDelay =

DR = 2.1

18

Strobe Time MattersStrobe time = time to observe output

T, 2T: defect detected 3T: defect not detected (test escape)

Defective out (DR=2.1)

0 T 2T 3T time

Good out

In Out

In

T= Delaygood



19

Test Speed SummaryResistive-open defects

Delay ratio > 1 Strobe time mattersRdef matters

Stuck-open defectsDelay ratio very large

Strobe time not critical

20

Test Voltage

21

Delay vs. VDD

0.00

0.20

0.40

0.60

0.80

0 1 2 3 4VDD

Del

ay in

ns

DefectiveDelay = (Rtr+Rdef)C

GoodDelay = RtrC

Delay Delta= RdefC(Constant)

Simulation (Rdef = 10KΩ)

22

Simulation: Rdef = 10KΩDelay ratio highest @ 3.0V

Optimal test voltage = 3.0V ?Not reallyMultiple paths (next slide)

Test Voltage Determination

VDD DR 3.00 2.7 2.50 2.4

1.80 (nominal) 2.1 1.50 1.9 1.00 1.5

23

Another Example: Three ChainsPath 1: Long wire, few inverters*Path 3: Short wire, many invertersPath 2: in between 1 & 3

Metal wire In1 Out 1

Out 2

Out 3

In2

In3

Path 1

Path 2

Path 3

Similar delay * Exact numbers see [Li ITC’01] 24

Long wireInsensitive to VDD

Delay vs. VDD

Delay = Gate Delay + Wire DelayGate Delay: VDD dependentWire Delay: VDD independent

VDD

Delay 2

1

3

Nominal

Path 2 largest delaymany gates

sensitive to VDD



25

Rdef in Path 1Defective path 1 detectable

VDD higher than nominal

VDD

DelayGood 2

Good 1

Nominal

Defective 1

Delay 1 > Delay 2(defect detectable)

26

Rdef in Path 3Defective path 3 detectable

VDD lower than nominal

VDD

Delay

Good 2

Nominal

Delay 3 > Delay 2(defect detectable)

Good 3Defective 3

27

Test Voltage SummaryResistive-open defects

Path dependent Long wire, few gates

VDD ≥ nominal, effectiveShort wire, many gates

VDD < nominal, effectiveStuck-open defects

All VDD effective

28

Test Set

29

Transition FaultPath delay of all paths through faulty gate

Exceed strobe time Example: NAND

Six transition faultsA slow-to-rise, A slow-to-fallB slow-to-rise, B slow-to-fallZ slow-to-rise, Z slow-to-fall

A

BZ

30

Transition Fault Test PatternsExample: AB=01,11

A slow-to-rise fault detectedZ slow-to-fall fault detected

100% transition fault coverage test set All transition faults in NAND detectedAll RO,SO in NAND detected [Li ITC’01]

A

B

Z1

10

faulty

good



31

Evaluation Summary Resistive open defects

Strobe time mattersTransition fault test set effectiveOptimal test temperature, voltage

Defect material and location dependentStuck-open defects

Transition fault test set effectiveOther conditions irrelevant

32


TestDiagnosis [Li ITC’01][Li VTS’02]

Tunneling-open DefectsTest Diagnosis

Summary

33

Previous WorkStuck open fault simulation [Barzilai 86] [Konuk 96]

Incomplete No experiment

Transition fault simulation [Waicukauski 87]IncompleteNo experiment

SSF based diagnosis [Hora 01] [Venkataraman 00] Sequence dependence not considered

34

Sequence DependenceTest results depend on test pattern orderingNAND example: d stuck open

AB=00,11,01, Z=1,0,0, detectedAB=00,01,11, Z=1,1,0, not detected

Charges stored at Z

A

B

Z

d NAND Truth Table AB Z 00 1 01 1 10 1 11 0

35

Our GoalPrecise diagnosis of SO and RO defects

Sequence dependence consideredReal experimental data

36

Fault 1 AB Z 00 1 11 0 01 1

Diagnosis Flow

Test

Fault Simulation

Failure TracesAB Z 00 1 11 0 01 1

Fault Signatures

DiagnosedFault

Fault 2 AB Z00 1 11 0 01 1

Fault 3 AB Z 00 1 11 0 01 1

Fault 1



37

The “Murphy Test Chip”Test chip description [Franco 95]

0.7µm technology, 5V nominal VDD

25K gates, combinational circuits 5 designs: 2 data path, 3 control Logic 5.5K chips tested

11 sequence dependent failuresSD.1 to SD.11

38

Diagnosis Results7 stuck-open suspect chips diagnosed

More precise results than commercial tool

Commercial SSF diagnosis*

Our diagnosis Chip ID

# of faults # of faults Faulty gate SD.1 3 1 NOR SD.2 1 1 NOR SD.3 4 1 AOI SD.4 4 1 OR SD.5 1 1 AOI SD.6 40 1 NAND SD.7 10 1 OAI

* not perfect match

39

Seven Stuck-open Suspect Chips15-detect SSF test set*, 5V, full speed

All detectedTest voltage irrelevant

6V, 5V, 2.5V, 1.7V (2Vt) All detectedTest speed irrelevant

2/3, 1/3, 1/30 speed All detected Transition fault coverage important

Padding zero between each original patternTransition fault coverage 100%-> 50%3 chips escaped (not detected)

* Detect every SSF 15 times 40

Other Sequence Dependent ChipsMultiple faults [Li VTS’02]

Clustered defects [Koren 94]

defects

Wafer map

41

Resistive OpensDiagnosis Flow

Similar to stuck opens Diagnosis results

One resistive open suspect chipOne inverter diagnosed

26 faults diagnosed by commercial tool

42

Resistive Open Suspect Chip15-detect SSF test set, 5V, full speed

Detected Change test voltage: 6V, 5V, 2.5V, 1.7V

Escaped 2.5V, 1.7VChange test speed: 2/3, 1/3, 1/30 speed

Escaped 1/3, 1/30 speed

Test voltage and speed important for ROConsistent with our analysis



43

Delay vs. VDD

Measured on tester

0

10

20

30

40

50

60

0 2 4 6 8VDD(V)

Cri

tica

l P

ath

Del

ay (

ns) Good

Resistive open

DD = 10 ns

44


TestDiagnosis

Tunneling-open DefectsTest [Li ITC’00]Diagnosis

Summary

45

Tunneling-open DefectsVery thin oxide at contact or via

incomplete etchroom temperature grown oxide

PolySiO2 SiO2

MetalTunneling Current

46

Three Tunneling EffectsFowler-Nordheim (FN) tunneling [Fowler 28]

Strong fieldDirect tunneling

Thin oxideTrap-assisted tunneling (aka. leakage)

Weak field

Field dependent

47

Previous Work and Our GoalPrevious work

[Henderson 91]No test method proposed No theoretical calculation

Our goalEffective testing of tunneling-open defects

Very Low Voltage (VLV) testingIDDQ(t) testing

48

VLV and IDDQ Testing Very Low Voltage (VLV) testing [Hao 93]

Effective for gate oxide short, Vt shift, etc.Optimal VDD 2 to 2.5 Vt [Chang 96b]Test speed characterized by shmoo [Chang 98b]

IDDQ testing Quiescent power supply current measurementOne measurement per test pattern

IDDQ(t) testing [Soden 89] [Maly 88]Continuous measurements per test pattern



49


TestDiagnosis

Tunneling-open DefectsTest [Li ITC’00]

VLV TestingIDDQ(t) Testing

DiagnosisSummary

50

Assumptions (0.7µm technology, Murphy)Tunneling open area = 1µm2; thickness = 12ÅCgate = 40fF

Example Circuit

Tunnelingcurrent

Cgate

Vm Vp VDD

Gnd

tunneling open

metal poly

51

Nominal Voltage (5V) Waveform

0

1

2

3

4

5

0 0.5 1 1.5 2 2.5 3 3.5time (ns)

volta

ge (V

)

Vm

Vp

0.5ns

logicthreshold

Defective circuit function correctly FN & direct tunneling current not negligible

52

Very Low Voltage (1.7V) Waveform

00.5

11.5

22.5

3

0 0.5 1 1.5 2 2.5 3 3.5time (ns)

vo

lta

ge

(V

) Vm

Vp

Logic threshold

Defective circuit fails VLV testing FN and direct tunneling insignificant

Eventually pass (very long wait) Small trap-assisted tunneling current

53

Delay RatioTunneling opens different from other defects

Defects DR @NV

DR @VLV

Tunneling opens ≈1 large Vt shift [Chang 96a] ≈1 3.0

Resistive Opens (8KΩ) [Li ITC’01] 2.1 1.4 Gate oxide shorts (8KΩ) [Chang 96b] ≈1 HF* Metal shorts (5KΩ) [Chang 96b] ≈1 HF

Stuck Opens [Li ITC’01] HF HF * HF = Hard Failure, defective circuits do not work at all

54

Murphy Experimental ResultsNine VLV-only failure Murphy chips found

Passed thorough nominal voltage testingOnly failed VLV testingNumbered VLV.1 to VLV.9



55

Delay vs. VDD (VLV.1,2)Hard failure below 3.5V

Not tunneling opens

1 1.5 2 2.5 3 3.5 4 4.5 5VDD

Cri

tical

Path

Dela

y (

S)

VLV.1,2

Good chip

10-1

10-3

10-2

10-4

10-5

10-6

10-7

10-8

FAIL

56

Delay vs. VDD (VLV.3 to 9)Delay Ratio = 60 to 9.6K (@ VLV=1.7V)

Tunneling open suspect chips

1 1.5 2 2.5 3 3.5 4 4.5 5VDD

Cri

tical P

ath

Dela

y (

S)

VLV.3

Good chip

10-1

10-3

10-2

10-4

10-5

10-6

10-7

10-8

VLV.9

DR=9.6K

DR=60

1.7

*VLV.4-8 are between VLV.3 and VLV.9

DR=1

57


TestDiagnosis

Tunneling-open DefectsTest [Li ITC’00]

VLV TestingIDDQ(t) Testing

DiagnosisSummary

58

IDDQ(t) Drift Over Time

time

time

Tdrift

IDDQ(t)

V(t)VDD Vt

Vm

Vp

0

Vm VpIDDQ

59

IDDQ(t) Experimental ResultsGood circuits

low (<1µA) and constant IDDQVLV.1,2

high (hundreds µA) and constant VLV.3,4

low and constantVLV.5 to 9

IDDQ(t) drift over time

0

10

20

30

40

50

60

0 0.1 0.2 0.3Time (second)

I DD

Q (m

A)

VLV.5

60

Estimate Tunneling CurrentSame assumptions

d = 12 Å, A=1µm2, Cgate = 40fFMeasured

Tdrift = 1 to 0.1 secondCalculated trap-assisted tunneling current

0.8 to 8 µA/cm2

falls in range of typical values



61

Proposed Test FlowTwo-stage testing

VLV testingfail pass

IDDQ(t) testing

high and constantIDDQ(t) drift over time

good

Other defectsTunneling open

Chips pass nominal voltage testing

62


TestDiagnosis

Tunneling-open DefectsTestDiagnosis [Li VTS’01]

Summary

63

Previous Work and Our GoalPrevious work

No diagnosis technique for TO so far

Our goalPrecise diagnosis of tunneling opens

VLV IDDQ(t)

64

Diagnosis FlowTwo Steps

Step 1 – gate list generation VLV testing, failure traces recordedCommercial SSF diagnosis tool

Step 2 – gates list reductionIDDQ(t) testing, IDDQ(t) drift recordedIDDQ(t) diagnosis

Diagnose gates, not faults Modeling issues [Li VTS’01]

65

Diagnosis ResultsExperiment from 5 tunneling open suspects*Fewer gates diagnosed

Easier failure analysis

* VLV.1,2 not TO; VLV.3,4 low IDDQ

Chip ID Commercial SSF diagnosis

Our diagnosis

Reduction

VLV.5 1 1 0% VLV.6 3 3 0% VLV.7 10 7 30% VLV.8 6 1 83% VLV.9 25 3 88%

Average 9 3 67%

Numbers of gates identified

66


TestDiagnosis


Summary



67

Summary (RO and SO)Effective testing

Test conditions and test set evaluatedValidated by Murphy experiments

Precise diagnosisDiagnosis flow presentedResults demonstrated by experiment

7 stuck open and 1 resistive open chips

68

Summary (TO)Effective Testing

TO could pass nominal voltage, fail only VLVIDDQ(t) drift over timeTest flow proposed: VLV + IDDQ(t)TO Murphy suspect chips identified

Behavior match theoretical analysisPrecise Diagnosis

Two stage diagnosis: VLV + IDDQ(t)Number of diagnosed gates reduced by 67%

69

ContributionsResistive and stuck-open defects

Optimal test conditions and test set [Li ITC’01]Precise diagnosis technique [Li ITC’01,VTS’02]

Tunneling-open defectsEffective test methods [Li ITC’00]

VLV and IDDQ(t) testingPrecise two-stage diagnosis [Li VTS’01]

Others (not in this presentation)IDDQ signature analysis technique [Li IDDQ’98]IDDQ(t) test pattern selection [Li VTS’01]

70

Publications (1) Resistive, stuck opens

[Li VTS’02] Li, J. C.M. and E.J. McCluskey, “Diagnosis of Sequence Dependent Chips,” IEEE VLSI Test Symp., 2002. (accepted)

[Li ITC’01] Li, J. C.M., C.W. Tseng, and E.J. McCluskey, “Testing for Resistive and Stuck Opens,” Proc. Int’l Test Conf., pp., 2001.Tunneling opens

[Li VTS’01] Li, J. C.M. and E.J. McCluskey, “Diagnosis of Tunneling Opens,” IEEE VLSI Test Symp., pp.22-27, 2001.

[Li ITC’00] Li, J. C.M. and E.J. McCluskey, "Testing for Tunneling Opens," Proc. Int’l Test Conf., pp. 85-94, 2000.

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Publications (2)Experiments

[Li 02] Li, J.C.M., and et. al. “ELF35 Experimental Results,”Int. Test Conf., 2002. (to be submitted in Feb.)

[Li 99] Li, J.C.M., J.T.-Y. Chang, C.W. Tseng, and E.J. McCluskey, "ELF35 Experiment - Chip and Experiment Design,“ CRC Technical Report 99-3, Oct. 1999.

[Li 98] Li, J.C.M., and E.J. McCluskey, "IDDQ Data Analysis Using Current Signature," Proc. 1998 IEEE International Workshop on IDDQ Testing, pp. 37-42, Nov. 12-14, 1998.

[Chang 98a] Chang, T.Y.J., C.W. Tseng, J.C.M. Li, M. Purtell, and E.J. McCluskey, "Analysis of Pattern-Dependent and Timing-Dependent Failures in an Experimental Test Chip," Proc. 1998 Int. Test Conf., pp. 184-193, Oct. 20-22, 1998.

72

AcknowledgementsAdvisor: Prof. McCluskeyCommittee: Prof. Fan, Prof. Wooley, Prof. SaxenaAdvantest: Mike PurtellFunding: HP, Intel, LSI logic, SRC RATS: Ahmad, Anjana, Catherine, Chao-Wen, Eddie, Edward, Erik, Jonathan, Kan, Mehdi, Moon, Nahmsuk, Philip, Ray, Robert, Sam, Samy, Siegrid, Siyad, Subhasish, Sungroh, Valerie, Vinod, and others Other Professors: Prof. Abraham, Prof. Koren, Prof. Fernandez-Gomez, Prof. Spielman and so onMy Friends: Chien-Chung, Chih-Chien, Li-yi, Tim, Yi-Chang, Yung-Hsiang and so onMy parents, brother, and Ying-Chih



73

Thank You!

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Documents

Test and Diagnosis of Open Defects in Digital CMOS IC