EE4800 CMOS Digital IC Design & Analysis

Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010Analysis 2010

11.11.11

EE4800 CMOS Digital IC Design & Analysis

Lecture 11 Sequential Circuit DesignZhuo Feng


11.11.22

Outline■Sequencing■Sequencing Element Design■Max and Min-Delay■Clock Skew


11.11.33

Sequencing■ Combinational logic

► output depends on current inputs

■ Sequential logic► output depends on current and previous inputs► Requires separating previous, current, future► Called state or tokens► Ex: FSM, pipeline

CL

clk

in out

clk clk clk

CL CL

PipelineFinite State Machine


11.11.44

Sequencing Cont.■ If tokens moved through pipeline at constant speed, no

sequencing elements would be necessary■ Ex: fiber-optic cable

► Light pulses (tokens) are sent down cable► Next pulse sent before first reaches end of cable► No need for hardware to separate pulses► But dispersion sets min time between pulses

■ This is called wave pipelining in circuits■ In most circuits, dispersion is high

► Delay fast tokens so they don’t catch slow ones.


11.11.55

Sequencing Overhead■ Use flip-flops to delay fast tokens so they

move through exactly one stage each cycle.

■ Inevitably adds some delay to the slow tokens

■ Makes circuit slower than just the logic delay► Called sequencing overhead

■ Some people call this clocking overhead► But it applies to asynchronous circuits too► Inevitable side effect of maintaining sequence


11.11.66

Sequencing Elements■ Latch: Level sensitive

► a.k.a. transparent latch, D latch

■ Flip-flop: edge triggered► A.k.a. master-slave flip-flop, D flip-flop, D register

■ Timing Diagrams► Transparent► Opaque► Edge-trigger

D

Flo

p

Latc

h

Q

clk clk

D Q

clk

D

Q (latch)

Q (flop)


11.11.77

Sequencing Elements■ Latch: Level sensitive

► a.k.a. transparent latch, D latch

■ Flip-flop: edge triggered► A.k.a. master-slave flip-flop, D flip-flop, D register

■ Timing Diagrams► Transparent► Opaque► Edge-trigger

D

Flo

p

Latc

h

Q

clk clk

D Q

clk

D

Q (latch)

Q (flop)


11.11.88

Latch Design■Pass Transistor Latch■Pros

+ Tiny+ Low clock load

■Cons►Vt drop►nonrestoring►backdriving►output noise sensitivity►dynamic►diffusion input

D Q

Used in 1970’s


11.11.99

Latch Design■Transmission gate

+ No Vt drop

- Requires inverted clock

D Q


11.11.1010

Latch Design■Inverting buffer

+ Restoring

+ No backdriving

+ Fixes either▼Output noise sensitivity▼Or diffusion input

► Inverted output

D

XQ

D Q


11.11.1111

Latch Design■Tristate feedback

+ Static►Backdriving risk

■Static latches are now essential

QDX


11.11.1212

Latch Design■Buffered input

+ Fixes diffusion input

+ Noninverting

QDX


11.11.1313

Latch Design■Buffered output

+ No backdriving

■Widely used in standard cells+ Very robust (most important)- Rather large- Rather slow (1.5 – 2 FO4 delays)- High clock loading

Q

D X


11.11.1414

Latch Design■Datapath latch

+ Smaller, faster

- unbuffered input

Q

D X


11.11.1515

Flip-Flop Design■ Flip-flop is built as pair of back-to-back latches

D Q

X

D

X

Q

Q


11.11.1616

Enable■ Enable: ignore clock when en = 0

► Mux: increase latch D-Q delay► Clock Gating: increase en setup time, skew

D Q

Latc

h

D Q

en

en

Latc

hDQ

0

1

en

Latc

h

D Q

en

DQ

0

1

enD Q

en

Flo

p

Flo

p

Flo

p

Symbol Multiplexer Design Clock Gating Design


11.11.1717

Reset■ Force output low when reset asserted■ Synchronous vs. asynchronous

D

Q

Q

reset

D

Q

D

reset

Q

Dreset

reset

reset

Synchronous R

esetA

synchronous Reset

Sym

bol Flo

p

D QLa

tch

D Q

reset reset

Q

reset


11.11.1818

Set / Reset■ Set forces output high when enabled■ Flip-flop with asynchronous set and reset

D

Q

reset

setreset

set


11.11.1919

Sequencing Methods■ Flip-flops■ 2-Phase Latches■ Pulsed Latches

Flip-F

lops

Flo

pLa

tch

Flo

p

clk

1

2

p

clk clk

Latc

h

Latc

h

p p

1 12

2-Phase T

ransparent LatchesP

ulsed Latches

Combinational Logic

CombinationalLogic

CombinationalLogic

Combinational Logic

Latc

h

Latc

h

Tc

Tc/2

tnonoverlap tnonoverlap

tpw

Half-Cycle 1 Half-Cycle 1


11.11.2020

Timing Diagrams

Flo

p

A

Y

tpdCombinational

LogicA Y

D Q

clk clk

D

Q

Latc

h

D Q

clkclk

D

Q

tcd

tsetup thold

tccq

tpcq

tccq

tsetup tholdtpcq

tpdqtcdq

tpdLogic Prop. Delay

tcdLogic Cont. Delay

tpcqLatch/Flop Clk-Q Prop Delay

tccqLatch/Flop Clk-Q Cont. Delay

tpdqLatch D-Q Prop Delay

tpcqLatch D-Q Cont. Delay

tsetupLatch/Flop Setup Time

tholdLatch/Flop Hold Time

Contamination and Propagation Delays


11.11.2121

Max-Delay: Flip-Flops

F1

F2

clk

clk clk

Combinational Logic

Tc

Q1 D2

Q1

D2

tpd

tsetuptpcq

setup

sequencing overhead

pd c pcqt T t t


11.11.2222

Max Delay: Pulsed Latches

Tc

Q1 Q2D1 D2

Q1

D2

D1

p

p p

Combinational LogicL1 L2

tpw

(a) tpw > tsetup

Q1

D2

(b) tpw < tsetup

Tc

tpd

tpdq

tpcq

tpd tsetup

setup

sequencing overhead

max ,pd c pdq pcq pwt T t t t t


11.11.2323

Min-Delay: Flip-Flops

holdcd ccqt t t CL

clk

Q1

D2

F1

clk

Q1

F2

clk

D2

tcd

thold

tccq


11.11.2424

Clock Skew■ We have assumed zero clock skew■ Two types of clock skews:

► Negative skew: sending register receives the clock earlier than the receiving register

► Positive skew: receiving register gets the clock earlier than the sending register.

■ Clocks really have uncertainty in arrival time► Decreases maximum propagation delay► Increases minimum contamination delay► Decreases time borrowing


11.11.2525

Skew: Flip-Flops

F1

F2

clk

clk clk

Combinational Logic

Tc

Q1 D2

Q1

D2

tskew

CL

Q1

D2

F1

clk

Q1

F2

clk

D2

clk

tskew

tsetup

tpcq

tpdq

tcd

thold

tccq

setup skew

sequencing overhead

hold skew

pd c pcq

cd ccq

t T t t t

t t t t

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EE4800 CMOS Digital IC Design & Analysis