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EE4800 CMOS Digital IC Design & Analysis
Lecture 1 IntroductionZhuo Feng
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.11
■ Prof. Zhuo Feng► Office: EERC 730► Phone: 487-3116 ► Email: [email protected]
■ Class Website ■ Class Website ► http://www.ece.mtu.edu/~zhuofeng/EE4800Fall2010.html► Check the class website for lecture materials, assignments
and announcementsand announcements
Schedule■ Schedule► TR 12:35pm-13:50pm EERC 227► Office hours: TR 4:30pm – 5:30pm or by appointments
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.22
Topics (tentative)
■ CMOS circuit overview■ Fabrication and layouty■ MOS Transistor I-V Characteristics■ DC & Transient Responses■ Delay and Power Estimation■ Delay and Power Estimation■ Logic Effort■ Interconnect■ Combinational Circuits■ Sequential Circuits■ Clock Distribution■ Memory■ Package, Power, I/O
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.33
Grading Policyg y■ Homework: 40%■ Quizzes 10%■ Quizzes 10%■ Mid-term Exam: 20%■ Final Exam: 30%■ Final Exam: 30%■ Late homework: 50% penalty/day.■ Letter Grades: ■ Letter Grades:
►A: 85~100; AB: 80~84; B: 75~79; BC: 70~74; C: 65~69; D: 60~64; F: 0~59
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.44
Moore’s law in Microprocessors
1000
P610
100
(M
T)
2X growth in 1.96 years!
286386
486Pentium® proc
P6
0 1
1
10
an
sist
ors
40048008
80808085 8086
286
0 001
0.01
0.1
Tra
40040.001
1970 1980 1990 2000 2010Year
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.55
Transistors on Lead Microprocessors double every 2 yearsTransistors on Lead Microprocessors double every 2 years
Courtesy, Intel
Die Size Growth100
486Pentium ® procP6
e (
mm
)
8008
80808085
8086286
386486 ® p
10
Die
siz
e
~7% growth per year2X th i 10 4004
1
1970 1980 1990 2000 2010
~2X growth in 10 years
1970 1980 1990 2000 2010Year
Die size grows by 14% to satisfy Moore’s LawDie size grows by 14% to satisfy Moore’s Law
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.66
Courtesy, Intel
FrequencyFrequency10000
Doubles every
P6Pentium ® proc
100
1000
cy (
Mh
z)
y2 years
Pentium ® proc486
38628680868085
80801
10
Fre
qu
en
c
8080800840040.1
1
1970 1980 1990 2000 20101970 1980 1990 2000 2010Year
Lead Microprocessors frequency doubles every 2 yearsLead Microprocessors frequency doubles every 2 years
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.77
Courtesy, Intel
Power Dissipationp
P6Pentium ®proc
100
486
862868086
10
(W
atts
)
3868085
80808008
4004
1Po
we
r
4004
0.1
1971 1974 1978 1985 1992 20001971 1974 1978 1985 1992 2000Year
Lead Microprocessors power continues to increaseLead Microprocessors power continues to increase
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.88
Courtesy, Intel
Why Scaling?■ Technology shrinks by ~0.7 per generation■ With every generation can integrate 2x more ■ With every generation can integrate 2x more
functions on a chip; chip cost does not increase significantly
■ Cost of a function decreases by 2x■ But …
► How to design chips with more and more functions?► How to design chips with more and more functions?► Design engineering population does not double every two
years…
H d f ffi i t d i th d■ Hence, a need for more efficient design methods► Exploit different levels of abstraction
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.99
Pentium 4■ Deep pipeline (2001)
► Very fast clock$► 256-1024 KB L2$
■ Characteristics► 180 – 65 nm process► 42-125M transistors► 1.4-3.4 GHz► Up to 160 W► Up to 160 W► 32/64-bit word size► 478-pin PGA
U i b■ Units start to becomeinvisible on this scale
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.1010
Pentium M■ Pentium III derivative
► Better power efficiency► 1-2 MB L2$
■ Characteristics► 130 – 90 nm processp► 140M transistors► 0.9-2.3 GHz► 6 25 W► 6-25 W► 32-bit word size► 478-pin PGA
■ Cache dominates chip area
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.1111
Core2 Duo■ Dual core (2006)
► 1-2 MB L2$ / core■ Characteristics
► 65-45 nm process► 291M transistors► 291M transistors► 1.6-3+ GHz► 65 W► 32/64 bit word size► 32/64 bit word size► 775 pin LGA
■ Much better f / performance/power
efficiency
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.1212
Core i7■ Quad core (& more)
► Pentium-style architecture► 2 MB L3$ /► 2 MB L3$ / core
■ Characteristics► 45-32 nm process
731M t i t► 731M transistors► 2.66-3.33+ GHz► Up to 130 W► 32/64 bit word size► 1366-pin LGA► Multithreading
■ On-die memory controller
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.1313
Atom■ Low power CPU for netbooks
► Pentium-style architecture► 512KB+ L2$
■ Characteristics► 45-32 nm process► 47M transistors► 0.8-1.8+ GHz► 1.4-13 W► 32/64-bit word size► 441-pin FCBGA
■ Low voltage (0.7 – 1.1 V) operationg ( ) p► Excellent performance/power
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.1414
Design Abstraction LevelsgSYSTEM
+
MODULE
+
GATE
DEVICE
CIRCUIT
n+n+S
GD
DEVICE
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.1515
Design MetricsDesign Metrics■ How to evaluate performance of a digital
circuit (gate, block, …)?(g )►Cost►Reliability►S l bilit►Scalability►Speed (delay, operating frequency) ►Power dissipation►Power dissipation►Energy to perform a function
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.1616
Cost of Integrated Circuitsg■ NRE (non-recurrent engineering) costs
►design time and effort mask generation►design time and effort, mask generation►one-time cost factor
■ Recurrent costs■ Recurrent costs►silicon processing, packaging, test►proportional to volumep p►proportional to chip area
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.1717
Cost per Transistorp
0.10.111
cost: cost: ¢¢--perper--transistortransistor
Fabrication capital cost per transistor (Moore’s law)
0.00010.0001
0.0010.001
0.010.01
0.00000010.0000001
0.0000010.000001
0.000010.00001
0.00000010.000000119821982 19851985 19881988 19911991 19941994 19971997 20002000 20032003 20062006 20092009 20122012
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.1818
Silicon Lattice■ Transistors are built on a silicon substrate■ Silicon is a Group IV material■ Silicon is a Group IV material■ Forms crystal lattice with bonds to four neighbors
Si SiSi
Si SiSi
Si SiSi
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.1919
Dopants■ Silicon is a semiconductor■ Pure silicon has no free carriers and conducts poorly■ Adding dopants increases the conductivity■ Group V: extra electron (n-type)
G III i i l t ll d h l ( t )■ Group III: missing electron, called hole (p-type)
Si SiSi Si SiSi-
+
+
-As SiSi
Si SiSi
B SiSi
Si SiSi
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.2020
N-type P-type
P-N Junctions■ A junction between p-type and n-type
semiconductor forms a diode.■ Current flows only in one direction
Current flow direction
p-type n-type
anode cathodeElectron flow direction
anode cathode
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.2121
NMOS Transistor■ Four terminals: gate, source, drain, body■ Gate – oxide – body stack looks like a capacitor
► Gate and body are conductors► SiO2 (oxide) is a very good insulator► Called metal – oxide – semiconductor (MOS) capacitor► Called metal – oxide – semiconductor (MOS) capacitor► Even though gate is no longer made of metal
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.2222
Substrate, body or bulk
NMOS Operation■ Body is commonly tied to ground (0 V)■ When the gate is at a low voltage:■ When the gate is at a low voltage:
► P-type body is at low voltage► Source-body and drain-body diodes are OFF► No current flows transistor is OFF► No current flows, transistor is OFF
GateSource DrainPolysilicon
SiO2
0n+
p bulk Si
n+DS
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.2323
NMOS Operation Cont.■ When the gate is at a high voltage:
► Positive charge on gate of MOS capacitor► Negative charge attracted to body► Inverts a channel under gate to n-type► Now current can flow through n-type silicon from source► Now current can flow through n type silicon from source
through channel to drain, transistor is ON
GateSource DrainPolysilicon
SiO2
Polysilicon
1n+
p bulk Si
n+D
1
S
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.2424
PMOS Transistor■ Similar, but doping and voltages reversed
► Body tied to high voltage (VDD)► Gate low: transistor ON► Gate high: transistor OFF► Bubble indicates inverted behavior► Bubble indicates inverted behavior
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.2525
Power Supply Voltagey g■ GND = 0 V■ In 1980’s, VDD = 5V, DD
■ VDD has decreased in modern processes► High VDD would damage modern tiny transistors
L V► Lower VDD saves power
■ VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.2626
Transistors as Switches■ We can view MOS transistors as electrically
controlled switches■ Voltage at gate controls path from source to
draing = 0 g = 1
g
d
g = 0
d
g = 1
d
nMOS OFF ONgs s s
nMOS ON
gs
d d
s
d
pMOS ON OFF
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.2727
s s s
CMOS Inverter
A Y
0VDD
1
A YA Y
GNDA Y
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.2828
CMOS Inverter
A Y
0VDD
1 0
A=1 Y=0
OFFA 1 Y 0
ON
GNDA Y
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.2929
CMOS Inverter
A Y
0 1VDD
1 0
A=0 Y=1
ONA 0 Y 1
OFF
GNDA Y
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.3030
CMOS NAND Gate
A B YA B Y
0 0
0 1 Y0 1
1 0 AY
1 1B
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.3131
CMOS NAND Gate
A B YA B Y
0 0 1
0 1 Y=1ON ON
0 1
1 0 A=0Y=1
OFF1 1 B=0 OFF
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.3232
CMOS NAND Gate
A B YA B Y
0 0 1
0 1 1 Y=1OFF ON
0 1 1
1 0 A=0Y=1
OFF1 1 B=1 ON
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.3333
CMOS NAND Gate
A B YA B Y
0 0 1
0 1 1 Y=1ON OFF
0 1 1
1 0 1 A=1Y=1
ON1 1 B=0 OFF
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.3434
CMOS NAND Gate
A B YA B Y
0 0 1
0 1 1 Y=0OFF OFF
0 1 1
1 0 1 A=1Y=0
ON1 1 0 B=1 ON
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.3535
CMOS NOR Gate
A B YA B Y
0 0 1
0 1 0A
0 1 0
1 0 0 BY1 1 0 Y
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.3636
3-input NAND Gate■ Y pulls low if ALL inputs are 1■ Y pulls high if ANY input is 0
AY
AB
C
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.3737
CMOS FabricationCMOS Fabrication■ CMOS transistors are fabricated on silicon wafer
■ Lithography process similar to printing press
■ On each step, different materials are deposited or etched
■ Easiest to understand by viewing both top and cross-section of wafer in a simplified cross section of wafer in a simplified manufacturing process
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.3838
Inverter Cross-sectionInverter Cross section■ Typically use P-type substrate for NMOS
transistors■ Requires N-well for body of PMOS transistors
► Silicon dioxide (SiO2) prevents metal from shorting to other layerslayers
input AGND
n+ p+
YGND VDD
n+ p+
SiO2
n+ diffusion
p+ diffusionn+
p substrate
p+
n well
n+ p+polysilicon
metal1
MOS t i t MOS t i t
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.3939
nMOS transistor pMOS transistor
Well and Substrate TapsWell and Substrate Taps■ P-type substrate (body) must be tied to GND■ N-well is tied to VDD■ N well is tied to VDD
■ Use heavily doped well and substrate contacts ( taps)► Establish a good ohmic contact providing low resistance for
bidirectional current flow
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.4040
Inverter Mask SetInverter Mask Set■ Transistors and wires are defined by masks
► Inverter can be obtained using six masks: n-well, gpolysilicon, n+ diffusion, p+ diffusion, contacts and metal
■ Cross-section taken along dashed line
A
Y
GND VDD
nMOS transistor pMOS transistor
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.4141
substrate tap well tapnMOS transistor pMOS transistor
Detailed Mask Views■ Six masks
► n-well
Detailed Mask Views
► Polysilicon
► N+ diffusion► P+ diffusion► P+ diffusion► Contact
M l► Metal
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.4242
Fabrication■ Chips are built in huge factories called fabs■ Contain clean rooms as large as football fields
Courtesy of InternationalBusiness Machines (IBM) Corporation. Unauthorized use not permitted.
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.4343
Fabrication StepsFabrication Steps■ Start with blank wafer■ Build inverter from the bottom up■ Build inverter from the bottom up■ First step will be to form the n-well
► Cover wafer with protective layer of SiO2 (oxide)► Remove layer where n-well should be built► Implant or diffuse n dopants into exposed wafer► Strip off SiO2p 2
p substrate
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.4444
OxidationOxidation■ Grow SiO2 on top of Si wafer
►900 – 1200 Celcius with H2O or O2 in oxidation►900 1200 Celcius with H2O or O2 in oxidation furnace
SiO2
p substrate
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.4545
Photoresist■ Spin on photoresist
►Photoresist is a light-sensitive organic polymer►Softens where exposed to light
Photoresist
p substrate
SiO2
Photoresist
p substrate
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.4646
Lithography■ Expose photoresist through n-well mask■ Strip off exposed photoresist
g p y
■ Strip off exposed photoresist
SiO2
Photoresist
p substrate
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.4747
Etch■ Etch oxide with hydrofluoric acid (HF)■ Only attacks oxide where resist has been exposed■ Only attacks oxide where resist has been exposed
Photoresist
p substrate
SiO2
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.4848
Strip PhotoresistStrip Photoresist■ Strip off remaining photoresist
►Use mixture of acids called piranha etch►Use mixture of acids called piranha etch■ Necessary so resist doesn’t melt in next step
SiO2
p substrate
S O2
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.4949
N-well■ N-well is formed with diffusion or ion implantation■ Diffusion
► Place wafer in furnace with arsenic gas► Heat until As atoms diffuse into exposed Si
■ Ion Implantation■ Ion Implantation► Blast wafer with beam of As ions► Ions blocked by SiO2, only enter exposed Si
SiO2
n well
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.5050
Strip OxideStrip Oxide■ Strip off the remaining oxide using HF■ Back to bare wafer with n-well■ Back to bare wafer with n well■ Subsequent steps involve similar series of steps
p substraten well
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.5151
Polysilicono ys co■ Deposit very thin layer of gate oxide (SiO2)
► < 20 Å (6-7 atomic layers)( y )
■ Chemical Vapor Deposition (CVD) of silicon layer► Place wafer in furnace with Silane gas (SiH4)► F ll t l ll d l ili► Forms many small crystals called polysilicon► Heavily doped to be good conductor
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.5252
Polysilicon PatterningPolysilicon Patterning■ Use same lithography process to pattern
polysiliconp y
Polysilicon
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.5353
Self-Aligned ProcessSelf Aligned Process■ Use oxide and masking to expose where n+
dopants should be diffused or implanted■ N-diffusion forms NMOS source, drain, and n-
well contact
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.5454
N-diffusionN d us o■ Pattern oxide and form n+ regions■ Self-aligned process where gate blocks diffusion■ Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing
p substraten well
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.5555
p substrate
N-diffusion cont.■ Historically dopants were diffused■ Usually ion implantation today■ Usually ion implantation today■ But regions are still called diffusion
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.5656
N-diffusion cont.N diffusion cont.■ Strip off oxide to complete patterning step
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.5757
P-Diffusionus o■ Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact
p+ Diffusion
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.5858
Contacts■ Now we need to wire together the devices■ Cover chip with thick field oxide■ Cover chip with thick field oxide■ Etch oxide where contact cuts are needed
Contact
p substrate
Thick field oxide
n well
n+n+ n+p+p+p+
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.5959
Metallization■ Sputter on aluminum over whole wafer■ Pattern to remove excess metal, leaving wires■ Pattern to remove excess metal, leaving wires
M etal
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.6060
Layouty■ Chips are specified with set of masks■ Minimum dimensions of masks determine ■ Minimum dimensions of masks determine
transistor size (and hence speed, cost, and power)F t i f di t b t d ■ Feature size f = distance between source and drain► Set by minimum width of polysilicony p y
■ Feature size improves 30% every 3 years or so■ Normalize for feature size when describing
d ldesign rules■ Express rules in terms of λ = f/2
► E g λ = 0 3 μm in 0 6 μm process
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.6161
► E.g. λ = 0.3 μm in 0.6 μm process
Simplified Design Rulesg■ Conservative rules to get you started
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.6262
Inverter Layouty■ Transistor dimensions specified as Width / Length
► Minimum size is 4λ / 2λ, sometimes called 1 unit► In f = 0.6 μm process, this is 1.2 μm wide, 0.6 μm long
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.6363
Summaryy■ MOS Transistors are stack of gate, oxide, silicon■ Can be viewed as electrically controlled switches■ Can be viewed as electrically controlled switches■ Build logic gates out of switches■ Draw masks to specify layout of transistors■ Now you know everything necessary to start
designing schematics and layout for a simple chip!
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 2010Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Fall 20101.1.6464