Static Cmos

8/2/2019 Static Cmos

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DESIGNING OF COMBINATIONAL

LOGIC GATES IN CMOS

G.SUSMITHA

ROLL NO:06


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COMBINATIONAL VS. SEQUENTIAL LOGIC

CombinationalLogicCircuit

Out In Combinational

LogicCircuit

Out In

State

Combinational Sequential

Output = f (In) Output = F(In, Previous In)


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STATIC CMOS CIRCUIT

At every point in time (except during the switchingtransients) each gate output is connected to eitherV DD or V ss via a low-resistive path.

The outputs of the gates assume at all times the valueof the Boolean function, implemented by the circuit

This is in contrast to the dynamic circuit class, whichrelies on temporary storage of signal values on thecapacitance of high impedance circuit nodes.


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STATIC COMPLEMENTARY CMOS

F(In1,In2,InN)

In1In2

InN

In1In2InN

PUN

PDN

PMOS only

NMOS only

PUN and PDN are dual logic networks


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NMOS TRANSISTORS

IN SERIES/PARALLEL CONNECTIONTransistors can be thought as a switch controlled by its gate signal

NMOS switch closes when switch control input is high

X Y

A B

Y = X if A and B

XY

A

B Y = X if A OR B

NMOS Transistors pass a strong 0 but a weak 1


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PMOS TRANSISTORS

IN SERIES/PARALLEL CONNECTION

X Y

A B

Y = X if A AND B = A + B

X Y

A

B Y = X if A OR B = AB

PMOS Transistors pass a strong 1 but a weak 0

PMOS switch closes when switch control input is low


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THRESHOLD DROPS

VDD 0PDN

CL VDD CL

S

SD

D

VGS

0 VDD

PUN

0 VDD

- VTn

VDD |VTp |

VDD

0 VDD

CL

S

D

CL

VDD

VDD

S

D

VGS


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COMPLEMENTARY CMOS LOGIC STYLE


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COMPLEX CMOS GATE

D

A

B C

D

AB

C

OUT = D + A (B + C)


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CONSTRUCTING A COMPLEX GATE

C

(a) pull-down network

SN1 SN4

SN2

SN3 D

F F

A

D B

C

D

F

A

B

C

(b) Deriving the pull-up network hierarchically by identifyingsub-nets

D

A

A

B

C

V DD V DD

B

(c) complete gate


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C

A B

X = C (A + B)

B

AC

i

j

ABC

Logic Graph

j

VDDX

X

i

GND

AB

C

PUN

PDN


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C

A B

X = (A+B)(C+D)

B

A

D

VDDX

X

GND

AB

C

PUN

PDN

C

D

D

ABCD


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EXAMPLE: X = AB+CD

GND

x

a

b c

d

V DD x

GND

x

a

b c

d

V D D x

(a) Logic graphs for ( ab+cd ) (b) Euler Paths { a b c d }

a c d

x

V D D

GND

(c) stick diagram for ordering {a b c d }

b


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PROPERTIES OF COMPLEMENTARY CMOSGATES:

High noise margins :V OH and V OL are at V DD and GND , respectively.

No static power consumption : There never exists a direct path between V DD andV SS ( GND ) in steady-state mode .

Comparable rise and fall times: (under appropriate sizing conditions)


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SWITCH DELAY MODEL

AReq

A

Rp

A

Rp

A

Rn CL

A

CL

B

Rn

A

Rp

B

Rp

A

Rn C int

B

Rp

A

Rp

A

Rn

B

Rn CL

C int

INV


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INPUT PATTERN EFFECTS ON DELAY

Delay is dependent onthe pattern of inputs

Low to high transition both inputs go low

delay is 0.69 R p /2 CL one input goes low

delay is 0.69 R p CL

High to low transition both inputs go high

delay is 0.69 2Rn CL

CL B

Rn

A

Rp

B

Rp

A

Rn C int


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TRANSISTOR SIZING

CL

B

Rn

A

Rp

B

Rp

A

Rn Cint

B

Rp

A

Rp

A

Rn

B

Rn CL

C int 2

2

2 2

1 1

4

4


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FAN-IN CONSIDERATIONS

DCBA

D

C

B

A CL

C3

C2

C1

Distributed RC model(Elmore delay)

tpHL = 0.69 R eqn (C1+2C 2+3C 3+4C L)

Propagation delay deteriorates rapidly as afunction of fan-in quadratically in the worstcase.


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Fast Complex Gates:Design Technique 1

Transistor sizing as long as fan-out capacitance dominates

Progressive sizing

InN CL

C3

C2

C1 In1

In2

In3

M1

M2

M3

MN Distributed RC line

M1 > M2 > M3 > > MN (the fet closest to the

output is the smallest)


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FAST COMPLEX GATES:DESIGN TECHNIQUE 2Transistor ordering

C2

C1 In1

In2

In3

M1

M2

M3 CL

C2

C1 In3

In2

In1

M1

M2

M3 CL

critical path critical path

charged1

0 1 charged

charged1

delay determined by time todischarge C L, C 1 and C 2

delay determined by time todischarge C L

1

1

0 1


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FAST COMPLEX GATES:DESIGN TECHNIQUE 3

F = ABCDEFGH


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Delay in a Logic Gate

Gate delay:

d = h + p

effort delay intrinsic delay

Effort delay:

h = g f

logical effort effective fanout = C out /C in

Logical effort is a function of topology, independent of sizingEffective fanout (electrical effort) is a function of load/gate size


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LOGICAL EFFORT

f g pC C

C Rk Delayin

Lunit unit

1

g logical effort ,which is defined as how much moreinput capacitance a gate presents to deliver the sameoutput current as inverter.

P-intrincsic delay:ratio of intrinsic delays of gate andinverter

F-effective fanout


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EXAMPLES OF LOGICAL EFFORT

B

A

A B

F

V DDV DD

A B

A

B

F

V DD

A

F

1

2 2 2

2

2

1 1

4

4

Inverter 2-input NAND 2-input NOR

g = 1 g = 4/3 g = 5/3


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LOGICAL EFFORT OF GATES

IntrinsicDelay

EffortDelay

1 2 3 4 5

Fanout f

1

2

3

4

5

I n v e r t e

r : g =

1 ; p =

1

2 - i n p u t

N A N D

:g = 4 / 3

; p = 2

N o r m a l i z e d D e l a y


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LOGICAL EFFORT OF COMMON LOGIC GATES


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MULTISTAGE NETWORKS

N i

iii f g p Delay1

Stage effort: h i = g ifi

Path electrical effort: F = C out /C in

Path logical effort: G = g 1g2g N

Branching effort: B = b 1b2b N

Path effort: H = GFB

Path delay D = S d i = S p i + S h i


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BRANCHING EFFORT

Branching effort:

pathon

pathoff pathon

C

C C b


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OPTIMUM EFFORT PER STAGE

H h N When each stage bears the same effort:

N H h

P NH p f g D N iii / 1

Minimum path delay

Effective fanout of each stage: ii gh f

Stage efforts: g 1f1 = g 2f2 = = g NfN


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Example: Optimize Path

g = 1f = a g = 5/3

f = b/a

g = 5/3f = c/b

g = 1

f = 5/c

1a

b c

5


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EXAMPLE 8-INPUT AND


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RATIOED LOGIC


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IMPROVED LOADS

V DD

V SS

PDN1

Out

V DD

V SS

PDN2

Out

A A B B

M1 M2

Differential Cascode Voltage Switch Logic (DCVSL)


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DCVSL EXAMPLE

B

A A

B B B

Out

Out

XOR-NXOR gate


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PASS-TRANSISTOR LOGIC

I n p u t s

Switch

Network

Out Out

A

B

B

B

N transistors

No static consumption

Pass transistors require low switching energy to chargeup a node due to the reduced voltage swing


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EXAMPLE: AND GATE

B

B

F = AB

0


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DIFFERENTIAL PASS TRANSISTOR LOGIC

A

B

A

B

B B B B

A

B

A

B

F=AB

F=AB

F=A+B

F=A+B

B B

A

A

A

A

F=A

F=A

OR/NOR EXOR/NEXORAND/NAND

F

F

Pass-TransistorNetwork

Pass-TransistorNetwork

AABB

AABB

Inverse

(a)

(b)


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NMOS ONLY LOGIC:LEVEL RESTORING TRANSISTOR

M 2

M 1

M n

M r

Out A

B

V DD V DD Level Restorer

X

Advantage: Full Swing

Ratio problem


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TRANSMISSION GATE

A B

C

C

A B

C

C

B

C L

C = 0 V

A = 2.5 V C = 2.5 V


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TRANSMISSION GATE BASEDMULTIPLEXER

AM 2

M 1

B

S

S

S F

V DD


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TRANSMISSION GATE XOR

A

B

F

B

A

B

B M1

M2

M3/M4


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V out

0 V

2.5 V

2.5 VR n

R p

0.0 1.0 2.00

10

20

30

V out , V

essance,oms

R n

R p

R n || R p


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DELAY IN TRANSMISSION GATE NETWORKS

V 1 V i-1

C

2.5 2.5

0 0

V i V i+1

C C

2.5

0

V n-1 V n

C C

2.5

0

In

V 1 V i V i+1

C

V n-1 V n

C C

In R eq R eq R eq R eq

C C

(a)

(b)

C

R eq R eq

C C

R eq

C C

R eq R eq

C C

R eq

C In

m

(c)


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PROS AND CONS:

Pros:Robustnessgood performanceNo Static Power Dissipation

Cons:

Requires 2N transistors with a fan in ofN


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CONCLUSION:

Static CMOS circuits can be used for devicesthat have no extreme area,complexity or

speedconstraints


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REFERENCES:

1.DIGITAL INTEGRATED CIRCUTS BYJAN RABAEY,ANANTHA CHANDRAKASAN,BORIVOJE NIKOLIC

2.http://bwrc.eecs.berkeley.edu/ICbook


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THANK U

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Static Cmos