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CMPEN 411 L06 S.1
CMPEN 411VLSI Digital Circuits
Lecture 06: Static CMOS Logic
Kyusun Choi
[Adapted from Rabaey’s Digital Integrated Circuits, Second
Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]
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CMPEN 411 L06 S.2
Review: CMOS Process at a Glance
Define active areas
Etch and fill trenches
Implant well regions
Deposit and patternpolysilicon layer
Implant source and drainregions and substrate contacts
Create contact and via windowsDeposit and pattern metal
layers
One full photolithographysequence per layer (mask)
Built (roughly) from the bottom up
4 metal
2 polysilicon
3 source and drain diffusions
1 tubs (aka wells, active areas)
exception!
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CMPEN 411 L06 S.3
CMOS Circuit Styles
Static complementary CMOS - except during switching, output
connected to either VDD or GND via a low-resistance path
high noise margins
- full rail to rail swing
- VOH and VOL are at VDD and GND, respectively
low output impedance, high input impedance
no steady state path between VDD and GND (no static power
consumption)
delay a function of load capacitance and transistor
resistance
comparable rise and fall times (under the appropriate transistor
sizing conditions)
Dynamic CMOS - relies on temporary storage of signal values on
the capacitance of high-impedance circuit nodes
simpler, faster gates
increased sensitivity to noise
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CMPEN 411 L06 S.4
Static Complementary CMOS
VDD
F(In1,In2,…InN)
In1In2
InN
In1In2
InN
PUN
PDN
Pull-up network (PUN) and pull-down network (PDN)
PMOS transistors only
pull-up: make a connection from VDD to F
when F(In1,In2,…InN) = 1
NMOS transistors only
pull-down: make a connection from F to
GND when F(In1,In2,…InN) = 0
Question : How many transistors are used to implement
N-input function F(In1,In2,…InN) ?
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CMPEN 411 L06 S.5
Construction of PDN
NMOS devices in series implement a NAND function
NMOS devices in parallel implement a NOR function
A
B
A • B
A B
A + B
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CMPEN 411 L06 S.6
Dual PUN and PDN
PUN and PDN are dual networks
DeMorgan’s theorems
A + B = A • B [!(A + B) = !A • !B or !(A | B) = !A & !B]
A • B = A + B [!(A • B) = !A + !B or !(A & B) = !A | !B]
a parallel connection of transistors in the PUN corresponds to a
series connection of the PDN
Complementary gate is naturally inverting (NAND, NOR, AOI,
OAI)
Number of transistors for an N-input logic gate is 2N
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CMPEN 411 L06 S.7
CMOS NAND
A
B
A • B
A B
A B F
0 0 1
0 1 1
1 0 1
1 1 0
A
B
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CMPEN 411 L06 S.8
CMOS NOR
A + B
A
BA B F
0 0 1
0 1 0
1 0 0
1 1 0
A B
A
B
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CMPEN 411 L06 S.10
Complex CMOS Gate
OUT = !(D + A • (B + C))
D
A
B C
D
A
B
C
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CMPEN 411 L06 S.11
Static Complementary CMOS
VDD
F(In1,In2,…InN)
In1In2
InN
In1In2
InN
PUN
PDN
Question1: why PUN are PMOS only and PDN
are NMOS only?
Naturally inverting, implementing only functions such as NAND,
NOR, and XNOR in a single stage.
PMOS transistors only
pull-up: make a connection from VDD to F
when F(In1,In2,…InN) = 1
NMOS transistors only
pull-down: make a connection from F to
GND when F(In1,In2,…InN) = 0
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CMPEN 411 L06 S.13
Threshold Drops
VDD
VDD 0PDN
0 VDD
CL
CL
PUN
VDD
0 VDD - VTn
CL
VDD
VDD
VDD |VTp|
CL
S
D S
D
VGS
S
SD
D
VGS
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CMPEN 411 L06 S.14
Standard Cell Layout Methodology
signals
Routing
channel
VDD
GND
What logic function is this?
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CMPEN 411 L06 S.15
OAI21 Logic Graph
C
A B
X = !(C • (A + B))
B
A
C
i
j
j
VDDX
X
i
GND
AB
C
PUN
PDN
ABC
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CMPEN 411 L06 S.16
Two Stick Layouts of !(C • (A + B))
A B C
X
VDD
GND
X
CA B
VDD
GND
uninterrupted diffusion strip
crossover requiring vias
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CMPEN 411 L06 S.18
Consistent Euler Path
j
VDDX
X
i
GND
AB
C
A B C
An uninterrupted diffusion strip is possible only if there
exists a Euler path in the logic graph
Euler path: a path through all nodes in the graph such that each
edge is visited once and only once.
For a single poly strip for every input signal, the Euler paths
in the PUN and PDN must be consistent (the same)
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CMPEN 411 L06 S.19
OAI22 Logic Graph
C
A B
X = !((A+B)•(C+D))
B
A
D
VDDX
X
GND
AB
C
PUN
PDN
C
D
D
ABCD
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CMPEN 411 L06 S.20
OAI22 Layout
BA D
VDD
GND
C
X
Some functions have no consistent Euler path like x = !(a + bc +
de) (but x = !(bc + a + de) does!)
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CMPEN 411 L06 S.21
XNOR/XOR Implementation
A
B
A B
A B
A
B
XNOR XOR
A B
A
B
A
B
A B
Can you create the stick transistor layout for the lower left
circuit?
How many transistors in each?
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CMPEN 411 L06 S.24
Static CMOS Full Adder Circuit (page 565)
B
B B
B B
B
B
B
A
A
A
A
A
AA
A
Cin
Cin
Cin
Cin
Cin!Cout !Sum
Cout=AB+BCin+ACin
Cout = Cin & (A | B) | (A & B)
Sum = ABCin+!Cout(A+B+Cin)
Sum = !Cout & (A | B | Cin) | (A & B & Cin)
# transistors = 24+4
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CMPEN 411 L06 S.25
Two chips you are seeing today
Microprocessor ASIC (Application Specific IC)
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CMPEN 411 L06 S.26
Standard Cell Library
NAND INV
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CMPEN 411 L06 S.27
Standard Cell Library
NAND INV NAND
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CMPEN 411 L06 S.28
The design flow
VHDL
(decoder.vhd)
Simulation Synthesis
Verilog netlist
(decoder.v)
Place/Route
Physical layout
(decoder.cif)
Standard
Cell Lib
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CMPEN 411 L06 S.29
The IBM ASIC Design Flow
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CMPEN 411 L06 S.30
Next Lecture and Reminders
Next lecture
Pass transistor logic
- Reading assignment – Rabaey, et al, 6.2.3
