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ADVANCE DATA

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

September 2005 7801572A STMicroelectronics Confidential

®

C o n f i d e n t i a l

Features■ The STx7100 is a single-chip, high-

definition STB decoder including:● ST40 CPU core, 266 MHz● dual ST231 CPU cores for audio and video

decoding, both 400 MHz● transport filtering and descrambling● video decoder: H.264/AVC and MPEG-2● graphics engine and dual display:

high-definition (HD) andstandard definition (SD)

● audio decoder

■ The STx7100 also features the followingembedded interfaces:● USB 2.0● DVI/HDMI output● digital audio and video auxiliary input● modem● serial ATA

32

CP

ST40 core 266 MHz

UDI 16 K Icache

MMUInt. control

32 K Dcache

LMI

Digitalvideo input

LMU

S/PDIF

2-chPCM in

SDvideo in

TMDS main video

DENC

EMI

3xSSCs

4xUARTsILC

2x I/FSmCard

6x GPIO

PWMMAFE

interfaceIR

Tx/Rx

STBus

Main videodisplay

FDMA

AudioL

TSmerger/router

Displaycompositor

2D gammablitter

DACs

DVI-HDCPHDMI

Output stage

Main videooutput (HD)

YPbPr

Aux videooutput (SD)YC/CVBS

USB

AudioR

PDES

Clockgenerator

5 x 2-chPCM out

Peripheral I/Oand external interrupts

Flashperipherals

TSIN0NRSS-A

TSIN1 TS I/O

and systemservices

DACs

CUR GDP GDP

Aux videodisplay

Audio decoderand interfaces

AudioDACs

PTI

output (HD)

Video decoderH.264/AVC,

MPEG2

2.0

SerialATA

interface

LMI

32

SDRAMDDR

Video

System

ST231core

ST231core

DiSEqC

DAA

STx7100 (STb7100, STi7100, STm7100)

Low-cost HDTV set-top box decoder for H.264/AVC and MPEG-2

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Processor subsystem■ ST40 32-bit superscalar RISC CPU

● 266 MHz, 2-way set associative 16-Kbyte ICache, 32-Kbyte DCache, MMU

● 5-stage pipeline, delayed branch support● floating point unit, matrix operation support● debug port, interrupt controller

Transport subsystem■ TS merger/router

● 2 serial/parallel inputs● 1 bidirectional interface● merging of 3 transport streams● transport stream from memory support● NRSS-A module interface● TS routing for DVB-CI and CableCARD ™ modules

■ Programmable transport interface (PTI)● transport stream demux: DVB, DIRECTV®, ATSC, ARIB,

OpenCable, DCII● integrated DES, AES, DVB, ICAM and Multi2

descramblers● NDS random access scrambled stream protocol (RASP)

compliant● NDS ICAM CA● support for VGS, Passage and DVS042 residue handling

Video/graphics subsystem■ MPEG-4 AVC high profile level 4.1/ MPEG-2

MP@HL video decoder● hardware/firmware mixed architecture● advanced error concealment and trick mode support● dual MPEG-2 MP@HL decode

■ SD (ITU-R BT 601/656) D1 digital video input■ Displays

● HD display, multiformat capable(1080I, 720P, 480P/576P, 480I/576I)- Analog HD output RGB or YPbPr- HDMI encoded output

● SD display- Analog SD output: YPbPr or YC and CVBS

■ Gamma 2D/3D graphics processor● dual source blitter engine● alpha blending and logical operations● color space and format conversion● fast color fill● arbitrary resizing with high quality filters● acceleration of direct drawing by CPU

■ Gamma compositor and video processor● 5 channels mixer for HD output● independent 2-channel mixer for SD output● 2 graphic display planes● high-quality video scaler● picture up-conversion hardware● linear resizing and format conversions● horizontal and vertical filtering

■ Copy protection● HDMI 1.0/HDCP 1.1 copy protection hardware● Macrovision™ copy protection for 480I, 480P, 576I, 576P

outputs

Audio subsystem■ Digital audio decoder

● compatible with all popular audio standards● PCM mixing with internal or external source and sample

rate conversion● independent multichannel PCM output, S/PDIF output and

analog output● 6 to 2 channel downmixing● PCM audio input

■ Stereo 24-bit audio DAC for analog output■ IEC958/IEC1937 digital audio output

interface (S/PDIF)

Interfaces■ External memory interface (EMI)

● 16-bit interface supporting ROM, Flash, SFlash, SRAM,peripherals

● access in 5 banks● master/slave support for interconnecting two STx7100

devices

■ Dual local memory interface (LMI)● dual interface for 32-bit DDR1 200-MHz (DDR400)

memories, supports 64, 128, 256 and 512 Mbit devices

■ USB 2.0 host interface■ Serial ATA hard-disk drive support

● record and playback with trick modes● pause and time shifting● watch and record

■ On-chip peripherals● 4 ASCs (UARTs) with Tx and Rx FIFOS, two of which can

be used in smartcard interfaces● 2 smartcard interfaces and clock generators (improved to

reduce external circuitry)● 3 SSCs for I²C/SPI master slaves interfaces● 2 PWM outputs● teletext serializer and DMA module● 6 banks of general purpose I/O, 3.3 V tolerant● SiLabs line-side (DAA) interface● Modem analog front end (MAFE/DAA) interface● infrared transmitter/receiver supporting RC5, RC6 and

RECS80 codes● UHF remote receiver input interface● interrupt level controller and external interrupts,

3.3 V tolerant● low power/RTC/watchdog controller● integrated VCXO● DiSEqC TM 2.0 interface

■ Flexible multichannel DMA

Services and package■ JTAG/TAP interface■ ST40 and ST231 toolset support■ 35 x 35 PGBA package, 580+100 balls

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Contents

Part 1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Chapter 1 Applications overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Chapter 2 Device variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Chapter 3 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

3.2 Omega2 (STBus) interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

3.3 Processor cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253.4 Dual local memory interface (LMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

3.5 External memory interface (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

3.6 Transport subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

3.7 H.264/MPEG-2 video decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

3.8 Digital video input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

3.9 Video display processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

3.10 Graphics display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293.11 Display compositor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

3.12 Main display output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

3.13 Auxiliary display output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

3.14 Gamma 2D blitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

3.15 Audio subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

3.16 FDMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

3.17 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353.18 Clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

3.19 System services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Chapter 4 CPUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.1 ST40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

4.2 ST231 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Chapter 5 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

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5.2 Internal peripherals map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.3 Memory management and organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.4 Memory space access per initiator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Part 2 Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Chapter 6 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Chapter 7 Pin list and alternative functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7.1 Pin-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7.2 Alternative functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Chapter 8 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

8.1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

8.2 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

8.3 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

8.4 Transport, NRSS-A and D1 input interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

8.5 Display digital output interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

8.6 Display analog output interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

8.7 HDMI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

8.8 Audio digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

8.9 Audio analog interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

8.10 Programmable inputs/outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

8.11 External memory interface (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

8.12 System local memory interface (LMISYS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

8.13 Video local memory interface (LMIVID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

8.14 USB 2.0 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

8.15 SATA-I interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

8.16 Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Chapter 9 Reset configuration (mode pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Chapter 10 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

10.1 Video DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

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Chapter 11 Timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

11.1 Audio input AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

11.2 Audio output AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

11.3 Video output AC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

11.4 Transport stream input AC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9411.5 DVP inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

11.6 Transport stream output AC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

11.7 JTAG interfaces AC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

11.8 EMI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

11.9 LMI DDR-SDRAM timings (system and video) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

11.10 PIO output AC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

11.11 MAFE interface output AC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10211.12 MAFE interface input AC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

Chapter 12 HD and SD triple video DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

12.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

12.2 Output-stage adaptation and amplification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

Chapter 13 Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

13.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

13.2 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

13.3 Output stage filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

Chapter 14 PCB layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

14.1 SATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

14.2 DDR-SDRAM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

14.3 USB2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11314.4 Board design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

14.5 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

14.6 HDMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

Part 3 System infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Chapter 15 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

15.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

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15.2 Clock generator A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

15.3 Clock generator B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Chapter 16 Clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

16.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

16.2 Clock generator A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

16.3 Clock generator B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Chapter 17 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

17.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

17.2 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

17.3 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

17.4 Reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

17.5 CPUs reset and reset out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

17.6 ST40 watchdog timeout reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

17.7 NOTWDOGRSTOUT signal length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Chapter 18 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

18.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

18.2 ST40 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16518.3 Reducing or/and stopping the clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

18.4 ILC interrupt controller: wake-up interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

18.5 DDR self-refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

18.6 Low-power mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Chapter 19 Low power registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Chapter 20 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

20.1 Default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

20.2 Delta ST231 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

20.3 Audio ST231 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Chapter 21 System configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

21.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

21.2 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17221.3 Device identity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

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21.4 System status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174

21.5 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178

Chapter 22 Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

22.1 ST40 Interrupt network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196

22.2 Delta (H.264) ST231 interrupt network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198

22.3 STx7100 interrupt network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198

Chapter 23 Interrupt maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

23.1 ST40 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200

23.2 INTC2 secondary interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

23.3 Delta (H.264) ST231 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

23.4 STx7100 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206

Chapter 24 Interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

24.1 Interrupt level controler (ILC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

24.2 INTC2 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214

Chapter 25 Programmable I/O (PIO) ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Chapter 26 Programmable I/O ports registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Chapter 27 Mailboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

27.1 Mailbox register operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224

Chapter 28 Mailbox registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

Part 4 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Chapter 29 Local memory interface (LMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

29.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231

29.2 SDRAM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232

Chapter 30 LMI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Chapter 31 External memory interface (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

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31.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

31.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

31.3 EMI interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

31.4 EMI address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

31.5 EMI operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25231.6 Default/reset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

31.7 Peripheral interface (with synchronous Flash memory support) . . . . . . . . . . . . . . . . 254

31.8 Chip select allocation/bank configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

31.9 Address bus extension to low order bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

31.10 PC card interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

31.11 External bus mastering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

31.12 EMI buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

Chapter 32 EMI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

32.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

32.2 EMI register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

32.3 EMI buffer register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

Chapter 33 DMA network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

33.1 DMA requests and channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

Chapter 34 Flexible DMA (FDMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

34.1 Channel structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

34.2 FDMA timing model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

34.3 Operating the FDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

34.4 Setting up FDMA transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

Chapter 35 Flexible DMA (FDMA) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

35.1 FDMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

35.2 Channel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

35.3 Command mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

35.4 Interrupt mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

35.5 Memory-to-memory moves and paced transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

35.6 S/PDIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

35.7 SCD/PES parsing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

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Part 5 Transport interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

Chapter 36 Programmable transport interface (PTI) . . . . . . . . . . . . . . . . . . . . . . . . . . 315

36.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315

36.2 PTI functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31636.3 PTI architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317

36.4 PTI operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320

36.5 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322

36.6 DMA operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .324

36.7 Section filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326

Chapter 37 Programmable transport interface (PTI) registers . . . . . . . . . . . . . . . . . . 333

37.1 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334

37.2 Input interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340

37.3 PTI configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343

37.4 Transport controller mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346

Chapter 38 Transport stream merger and router . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

38.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347

38.2 DVB common interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349

38.3 NRSS-A interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349

38.4 Input examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350

38.5 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353

38.6 Transport stream formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354

38.7 Packet buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356

38.8 Transport stream inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356

38.9 Transport stream output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358

Chapter 39 Transport stream merger and router registers . . . . . . . . . . . . . . . . . . . . . 362

Part 6 Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372

Chapter 40 Digital video port (DVP) input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373

40.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373

40.2 Video decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374

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40.3 Ancillary data decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377

Chapter 41 Digital video port (DVP) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378

Chapter 42 MPEG2 video decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390

42.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390

42.2 Main functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390

42.3 Buffer organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392

42.4 Video decoding tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396

42.5 Video decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398

42.6 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407

Chapter 43 MPEG2 video decoder registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408

Chapter 44 H.264 video decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418

44.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418

44.2 Decoder main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418

44.3 H.264 decoder interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421

44.4 Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422

44.5 H.264 decoder reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422

Chapter 45 Teletext DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

45.1 Teletext DMA overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

45.2 Teletext packet format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

45.3 Data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

45.4 Interrupt control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

45.5 DENC teletext registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

45.6 Teletext external interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

Chapter 46 Teletext DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425

Chapter 47 2D graphics processor (blitter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428

47.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428

47.2 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429

47.3 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430

47.4 Endianness support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432

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47.5 Blitter functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .433

47.6 Using the 4:2:x macroblock-based plane as a source . . . . . . . . . . . . . . . . . . . . . . . . .452

47.7 Blitter XYL mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .453

47.8 Local memory storage of supported graphics formats . . . . . . . . . . . . . . . . . . . . . . . .458

Chapter 48 2D graphics processor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465

48.1 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .465

48.2 Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .467

48.3 Blitter 2D-filter coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .490

Chapter 49 Main and auxiliary displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493

49.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .493

49.2 Fully programmable horizontal sample rate converters . . . . . . . . . . . . . . . . . . . . . . .493

49.3 Fully programmable vertical sample rate converters . . . . . . . . . . . . . . . . . . . . . . . . . .493

49.4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .494

49.5 Linear motion upconverter (LMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .494

49.6 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .496

49.7 Soft reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .505

Chapter 50 Main and auxiliary display registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50650.1 Main and auxiliary display registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .508

50.2 LMU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .527

Chapter 51 Compositor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533

51.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .533

51.2 Compositor layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .534

51.3 Digital mixer 1 (MIX1) - main display output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .536

51.4 Digital mixer 2 (MIX2) - auxiliary display output . . . . . . . . . . . . . . . . . . . . . . . . . . . . .537

51.5 Generic display pipelines (GDP1 and GDP2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .538

51.6 Cursor plane (CUR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .546

51.7 Video plug (VID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .550

51.8 Alpha plane (ALP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .552

Chapter 52 Compositor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554

52.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .554

52.2 Register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .556

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52.3 Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559

Chapter 53 Video output stage (VOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588

53.1 Display and video output subsystem overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588

53.2 HD DACs clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590

53.3 Video timing generators (VTG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592

53.4 RGB to YCrCb color space conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597

53.5 Digital video output formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598

53.6 Analog video output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598

53.7 Upsampler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606

Chapter 54 Video output stage (VOS) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607

54.1 VTG 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610

54.2 VTG 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619

54.3 General VOS configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626

54.4 Main video output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628

54.5 Digital SD video out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634

54.6 HD DAC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636

54.7 Upsampler tap coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636

54.8 Waveform generator configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643

Chapter 55 Digital encoder (DENC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644

55.1 Digital encoder overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644

55.2 Data input format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644

55.3 Video timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645

55.4 Reset procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647

55.5 Digital encoder synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64855.6 Input demultiplexor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651

55.7 Subcarrier generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651

55.8 Burst insertion (PAL and NTSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652

55.9 Subcarrier insertion (SECAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653

55.10 Luminance encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653

55.11 Chrominance encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655

55.12 Composite video signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65755.13 RGB and UV encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658

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55.14 Closed captioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .659

55.15 CGMS encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .660

55.16 WSS encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .660

55.17 VPS encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .661

55.18 Teletext encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66155.19 CVBS, S-VHS, RGB and UV outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .664

Chapter 56 Digital encoder (DENC) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665

56.1 Configuration and status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .667

56.2 Digital frequency synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .679

56.3 WSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .682

56.4 DAC inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .683

56.5 Hardware ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .685

56.6 VPS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .686

56.7 CGMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .687

56.8 Teletext . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .687

56.9 Closed caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .691

56.10 Input demultiplexor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .694

56.11 Chroma coefficient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .695

56.12 Luma coefficient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .697

56.13 Hue control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .698

Chapter 57 High-definition multimedia interface (HDMI) . . . . . . . . . . . . . . . . . . . . . . . 699

57.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .699

57.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .699

57.3 Video processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .701

57.4 Data processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .702

57.5 Frame formatting and line coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .707

57.6 HDCP interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .710

57.7 Hot plug detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .711

57.8 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .711

57.9 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .711

57.10 Info frame programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .711

57.11 Data island definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .712

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Chapter 58 HDMI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717

Part 7 Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730

Chapter 59 Audio subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731

59.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731

59.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731

59.3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732

59.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733

59.5 Audio clocks generator (clock generator C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733

59.6 Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734

59.7 Audio output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734

59.8 Audio DAC and frequency synthesizer connections . . . . . . . . . . . . . . . . . . . . . . . . . . 735

59.9 PCM player 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735

59.10 S/PDIF player . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737

59.11 PCM reader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738

Chapter 60 Audio registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739

60.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73960.2 Audio configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742

60.3 PCM player 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748

60.4 PCM player 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753

60.5 S/PDIF player . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759

60.6 PCM reader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768

Part 8 Peripherals and interfaces . . . . . . . . . . . . . . . . . . . . . . 773

Chapter 61 Asynchronous serial controller (ASC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774

61.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774

61.2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774

61.3 Data frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775

61.4 Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777

61.5 Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778

61.6 Baudrate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780

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61.7 Interrupt control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .782

61.8 Smartcard operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .785

Chapter 62 Asynchronous serial controller (ASC) registers . . . . . . . . . . . . . . . . . . . . 787

Chapter 63 Synchronous serial controller (SSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796

63.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .796

63.2 Basic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .797

63.3 I 2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .806

Chapter 64 Synchronous serial controller (SSC) registers . . . . . . . . . . . . . . . . . . . . . 813

Chapter 65 CSS/CPxM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824

Chapter 66 Digital satellite equipment control (DiSEqC) 2.0 . . . . . . . . . . . . . . . . . . . . 825

66.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .825

66.2 DiSEqC transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .826

66.3 DiSEqC receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .827

66.4 Noise suppression filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .827

66.5 Programming the transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .828

66.6 Programming the receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .831

Chapter 67 DiSEqC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836

67.1 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .837

67.2 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .846

Chapter 68 High-bandwidth digital content protection (HDCP) . . . . . . . . . . . . . . . . . 856

68.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85668.2 Software usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .858

Chapter 69 HDCP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861

Chapter 70 Infrared transmitter/receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866

70.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .866

70.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .866

70.3 Start code detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .869

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Chapter 71 Infrared transmitter/receiver registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872

71.1 RC transmitter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874

71.2 RC receiver registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878

71.3 Noise suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881

71.4 I/O control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88271.5 Reverse polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882

71.6 Receive status and clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883

71.7 IrDA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885

71.8 SCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887

Chapter 72 Modem analog front-end (MAFE) interface . . . . . . . . . . . . . . . . . . . . . . . . 892

72.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892

72.2 Using the MAFE to connect to a modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892

72.3 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893

Chapter 73 Modem analog front-end (MAFE) interface registers . . . . . . . . . . . . . . . . 894

Chapter 74 Direct access arrangement modem (DAA) . . . . . . . . . . . . . . . . . . . . . . . . 898

Chapter 75 Programmable descrambler (PDES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 899

Chapter 76 PWM and counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900

76.1 Programmable PWM function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901

76.2 Periodic interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902

76.3 Capture and compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902

Chapter 77 PWM and counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903

Chapter 78 Serial ATA (SATA) subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 909

78.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 909

78.2 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 909

78.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910

78.4 Low power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912

78.5 Interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912

78.6 DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912

78.7 SATA host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912

http://-/?-http://-/?-http://-/?-http://-/?-

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STx7100


Chapter 79 Serial ATA (SATA) DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913

79.1 Configuration Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .913

79.2 Programming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .921

79.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .951

Chapter 80 Serial ATA (SATA) host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009

80.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1009

80.2 Configurable parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1015

Chapter 81 Serial ATA (SATA) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019

81.1 DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1022

81.2 SATA host controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1043

Chapter 82 Smartcard interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060

82.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1060

82.2 External interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1060

82.3 Smartcard clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1061

82.4 Smartcard removal and power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1062

Chapter 83 Smartcard interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063

Chapter 84 Test access port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064

Chapter 85 USB 2.0 host (USBH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065

85.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1065

85.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1066

85.3 Bus topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1067

85.4 Data transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1069

Chapter 86 USB 2.0 host (USBH) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070

Part 9 End notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072

Chapter 87 Register index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073

Chapter 88 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081

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STx7100



Chapter 89 Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082

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STx7100


Part 1

Overview

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1 Applications overview STx7100



1 Applications overview

The STx7100 is a new generation, high-definition set-top box decoder chip, and provides very highperformance for low-cost HD systems. With enhanced performances over the STi7710, it includesan H.264/AVC decoder for new low-bitrate applications, as well as dual-decode MPEG-2 capability.Based on the Omega2 (STBus) architecture, this system on chip is a full back-end processingsolution for digital terrestrial, satellite and cable high-definition set-top boxes compliant with ATSC,DVB, DIRECTV, DCII, OpenCable and ARIB BS4 specifications.

The STx7100 demultiplexes, decrypts and decodes a single HD or SD video stream with associatedmultichannel audio. Video is output to two independently formatted displays: a full resolution displayintended for a TV monitor, and a downsampled display intended for a VCR, or alternatively a secondSD TV. Connection to a TV or display panel can be via an analog component interface or a copyprotected DVI/HDMI interface. Composite outputs are provided for connection to the VCR withMacrovision protection. Audio is output with optional PCM mixing to an S/PDIF interface, PCMinterface or via integrated stereo audio DACs.

Digitized analog programs can also be input to the STx7100 for reformatting and display.The STx7100 includes a graphics rendering and display capability with a 2D graphics accelerator,two graphics planes and a cursor plane. A dual display compositor provides mixing of graphics andvideo with independent composition for each of the TV and VCR outputs.The STx7100 includes a stream merger to allow three different transport streams from differentsources to be merged and processed concurrently. Applications include DVR time shifted viewing ofa terrestrial program while acquiring an EPG/data stream from a satellite or cable front end.The flexible descrambling engine is compatible with required standards including DVB, DES, AESand Multi2.

The STx7100 embeds a 266 MHz ST40 CPU for applications and device control. A dual DDR1SDRAM memory interface is used for higher performance, to allow the video decoder the requiredmemory bandwidth for HD H.264 decoding and sufficient bandwidth for the CPU and the rest of thesystem. A second memory bus is also provided for flash memory storing resident software and forconnection of peripherals.

A hard-disk drive (HDD) can be connected either to the serial ATA interface or as an expansion drivevia the USB 2.0 port. The USB port can also be used to connect to a DOCSIS 2.0 CM gateway forinteractive cable applications.

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STx7100 1 Applications overview


The STx7100 is supported by STMicroelectronics’ STAPI software, and is compatible with severalother related devices such as the STi7109.

Figure 1: Low-cost satellite HD set-top box

Figure 2: Low-cost cable HD set-top box with return channel

STx7100

Transportstream in

VCRPTSN MAFE I/F Flash

IR Tx/Rx

RGB/YPbPr/

CVBS/YC

HDMI

Smartcards

2 x 128 Mbit

DDR1

2 x 128 Mbit

DDR1

QPSK Rx+STB6000STV0299

CableCARD ™interface

STx7100

STV0294B

Flash

VCRRS232CVBS/YC

IRTx/Rx

Cable

Smartcards

Tuner andSAW filter

Tuner andSAW filter

PGA

Diplexfilter

Upstream

Broadcast

IB data/ OOB

front endQAM/QPSKtransceiver

RGB/YPbPr/ HDMI

EMI

2 x 128 MbitDDR1

2 x 128 MbitDDR1

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1 Applications overview STx7100



Figure 3: Low-cost dual satellite and terrestrial HD set-top box with HDD

Figure 4: Low-cost HD IP-TV set-top box with HDD

STx7100

Flash2xDDR1

MAFE I/F

RS232

USB 2.0

PSTN

IRTx/Rx

Smartcards

DVB-CI

HDD

STV0299

RGB/YPbPr/

HDMISTV0370Tuner

QPSK Rx

8VSB Rx

HDD

SATA

(expansion)

EMI

+STB6000

STx7100

Flash2xDDR1

RS232

USB 2.0

IRTx/Rx

Smartcards

HDD

RGB/YPbPr/

HDMI

HDD

SATA

(expansion)

EMI

EthernetRJ45

Ethernetcontroller

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STx7100 2 Device variants


2 Device variants

The STx7100 is available in several variants. These are differentiated by between two and foursuffix letters in the product code, as summarised in Table 1 .

The first letter indicates market type , details of which are shown in Table 2 .

The second letter indicates chip revision .

The letterP

orL

indicates unleaded (Eco) packaging; see Chapter 6: Package on page 48 fordetails.Finally, for parts supplied “tape-and-reel”, the suffix T is added.

Examples

STi7100ZBP is a development version, cut 2, unleaded.STb7100OCT is a Nagra Premier version, cut 3, leaded, delivered in a tape-and-reel pack.

Table 1: Part code suffix summary

Market typeChiprevision

Leaded orunleadedpackage

Delivery type

Z Development version,security disabled

A Cut 1 P Unleaded(for STi andSTm 7100)

T Tape-and-reel

J Nagra C+ B Cut 2 L Unleaded(for STb 7100)

- Standard

O Nagra Premier ... and so on - Leaded

Q Nagra Dedicated

T Viaccess France Telecom

I TPS

Table 2: Market type

Markettype

Macro-vision

AC3/ Prologic SATA V22 DES ICAM USB2 Market

Z ✔ ✔ ✔ ✔ ✔ ✔ ✔ Development version,security disabled

J ✔ Nagra C+

O ✔ ✔ ✔ ✔ ✔ Nagra Premier

Q ✔ ✔ ✔ ✔ Nagra Dedicated

T ✔ ✔ ✔ ✔ Viaccess FranceTelecom

I ✔ ✔ ✔ ✔ ✔ ✔ TPS

http://-/?-http://-/?-http://-/?-http://-/?-

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3 Architecture STx7100



3 Architecture

3.1 Overview

The STx7100 is designed around the well-proven Omega2 (STBus) interconnect and presents a

new generation of video decoder for MPEG-4 AVC as well as MPEG-2 decoding.Transport streams are received and processed by the TS subsystem. The resulting PES streamsand section data are stored in memory buffers in DDR SDRAM attached to the local memoryinterfaces (system and video LMI).

A flexible DMA controller (FDMA) performs PES parsing and start code detection and routeselementary streams to audio and video bit buffers in DDR SDRAM. An MP@HL/H.264 videodecoder decodes HD or SD video streams. Audio decoding and PCM mixing is performed by theaudio decoder and output via S/PDIF and PCM interfaces. Audio can also be output via anintegrated 24-bit stereo DACs system.

After video decoding, two independently formatted video displays (main and auxiliary) can begenerated, and each mixed independently with graphics to create main and auxiliary displaycompositions. The main display composition (HD or SD) can be output as RGB or YPbPr analogcomponent video and digitally via a copy-protected DVI/HDMI interface. The auxiliary displaycomposition (SD only) can be output as Y/C analog component or composite video CVBS on aseparate interface for connection to a VCR or a second TV.

A digital video input interface allows the STx7100 to receive noncompressed SD digital video,and to output this via the main and auxiliary displays in place of decoded video. A separate PCMinput allows any associated audio to be received, mixed and output in place of decoded audio.The graphics subsystem comprises a separate 2D blitter, two graphics planes, a cursor planeand dual display compositor. Graphics buffers are created, stored in and displayed from buffersin DDR SDRAM.

The STx7100 embeds an ST40 CPU core for applications and data processing and devicecontrol. The CPU boots from flash/SFlash ™ on the external memory interface (EMI) and canexecute in place or transfer the main executable to the DDR SDRAM and execute from there.CPU data is held in DDR SDRAM where cacheable and noncacheable regions can beprogrammed. The 16-bit EMI is also used for connecting to external peripherals.System performance is enhanced with the multichannel FDMA which can be used for 2D blockand stream data transfers with minimal CPU intervention.

DVR applications are supported using a hard-disk drive (HDD) connected either to the serial ATAor USB 2.0 interface.The STx7100 also integrates a range of peripherals, system services and a clock generatormodule with embedded VCXO to significantly reduce external component cost.

3.2 Omega2 (STBus) interconnect

The Omega2 multipath unified interconnect provides high on-chip bandwidth and low latencyaccesses between modules. The interconnect operates hierarchically, with latency-criticalmodules placed at the top level. The multipath router allows simultaneous access paths betweenmodules, and simultaneous read and write phases from different transactions to and from themodules. Split transactions maximize the use of the available bandwidth.

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STx7100 3 Architecture


3.3 Processor cores

The STx7100 integrates one ST40 and two ST231 processor cores. The ST40 is used to controlmost chip functions; the ST231 processors control audio and video/H.264 decoding; seeSection 3.15 and Section 3.7 respectively.

The 266 MHz ST40 processor core features a 32-bit superscalar RISC CPU and IEEE-754

compliant floating point unit (FPU). It includes 2-way associative caches, 16 Kbyte instructioncache and 32 Kbyte data cache, as well as core support peripherals such as a real-time clockand interrupt controller.

3.4 Dual local memory interface (LMI)

System LMI and video LMI are 32-bit, high-bandwidth memory interfaces that enable a unifieddata memory architecture through the use of DDR SDRAM. Both can operate in a 32-bit or 16-bitconfiguration and have a maximum operating frequency of 200 MHz.Each LMI interface provides two chip-selects, to support up to two arrays of 1 x 32 devices or2 x 16 devices. DDR devices of capacity 64, 128, 256, or 512 Mbits can be used, providing amaximum capacity of 4 x 64 Mbytes. When the application includes an HD-MPEG4 decode or adual HD-MPEG2 decode that needs a high memory bandwidth, then two memory interfaces areused. With this memory configuration, most of the video decoding processes use the video LMIwhile the other processes of the application use the system LMI.

Accesses to DDR SDRAM go through a local look ahead buffer to enhance bandwidth utilizationand to take advantage of pages that are already open, and to open pages in advance.Optimizations also include opcode merging.Table 3 shows the memory requirements for each type of application.

3.5 External memory interface (EMI)

The EMI is a 16-bit general-purpose interface for attaching system flash or synchronous flashdevices and peripherals. Up to five separate banks are available, each capable of its own strobetiming configuration, and each with its own chip select signal. One bank provides PC-cardcompatible strobes for implementing a DVB-CI, ATAPI or CableCARD ™ module interface.

Table 3: DDR memory requirements for each type of application

Decode type Memory requirements (Mbytes)System LMI Video LMI

Single MPEG2 decode only 32 0

Dual MPEG2 decode only 32 32

H.264 decode only

H.264 and MP2 HD concurrent 64

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3.6 Transport subsystem

The transport stream subsystem comprises the TS merger/router and a programmable transportstream interface (PTI).

3.6.1 Transport stream input/output

Transport streams are input to the STx7100 via one of three interfaces. Two of these are parallelinputs which can also be configured for serial input if required. The third is a bidirectional parallelinterface that can be configured as an input or output.

A five-input, two-output transport stream merger/router allows any of the three external inputs to

be routed to the PTI. A fourth input is provided for routing internal transport streams stored inmemory to the PTI. A fifth input receives a full/partial transport stream created by the PTI andcan output it from the STx7100 via the bidirectional interface when configured as an output. Thisallows TS streams to be sent to a D-VCR via an IEEE1394 link layer controller. Routing to thetwo outputs can be concurrent.An NRSS-A interface is available for routing serial TS streams to and from an NRSS-Acompatible CA module.

The stream merger/router is also capable of merging any three of the input streams into one TSstream and forwarding this to the PTI allowing it to process three independently sourcedtransport streams at the same time.

3.6.2 Programmable transport interface (PTI)The PTI performs PID filtering, demultiplexing, descrambling, and data filtering on up to threetransport streams at the same time. The PTI extracts PCRs with time stamps and makes themavailable to the CPU for clock recovery and audio/video synchronization. The PTI can onlyextract one PCR at a time, and only one is available for clock recovery.PES data is transferred by DMA to memory buffers. Section data is transferred by DMA toseparate buffers for further processing by the CPU. The PTI can also extract indexing informationand then transfer packets, using DMA, to an intermediate buffer for writing to HDD.

Transport streams supported include DIRECTV®, DVB, ATSC, OpenCable, DCII, and ARIB BS4.The PTI performs PID filtering to select audio, video and data packets to be processed. Up to 96PID slots are supported.

Figure 5: Transport-stream subsystem

TS merger

TSIN1parallel or serial

TSIN2parallel or serial

TS I/Oserial/parallel in

NRSS-A interface (serial)

PTI

SWTS

Alt out

STBus

parallel out

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The PTI can descramble streams using the following ciphers:● DES-ECB including DVS-042 termination block handling,● DES-CBC including DVS-042 termination block handling,● DES-OFB,● Multi2-ECB including DVS-042 termination block handling,●

Multi2-CBC including DVS-042 termination block handling,● Multi2-OFB,● DVB-CSA,● AES decryption/encryption with cipher block chaining,● NDS specific streams can also be supported by the integration of ICAM functionality.

The PTI has a 48 x 16 byte section filter core.Three filtering modes are available:● wide match mode: 48 x 16-byte filters,● long match mode: 96 x 8-byte filters,● positive/negative mode: 48 x 8-byte filters with positive/negative filtering at the bit level.

Matching sections are transferred to memory buffers for processing by software.

When the PTI is required to output a transport stream, it can output the entire transport stream orselected packets filtered by PID. A latency counter is provided to ensure packet timing ispreserved. Packets can also be substituted.

3.7 H.264/MPEG-2 video decoder

The STx7100's video decoder is a new generation decoder for either SD or HD streams; it is fullycompliant with H.264/AVC MP@L4 and [email protected] (main and high profile) video streams as wellas ISO/IEC13818-2 MP@ML and MP@HL formats.The decoder uses a mixed hardware/firmware architecture with a hardwired datapath and a400 MHz ST231 CPU core engine. It provides flexibility for firmware upgrades, errorconcealment or trick modes. The core may be used for other coder/decoders at lower resolutionwhen the H.264 decoder is not running. The H.264/MPEG2 video decoder is capable of dualMP@HL decoding.A stream is decoded picture by picture from an elementary stream buffer. Decoding,reconstruction and prediction buffers are set up by the host CPU. CPU control of bit bufferpointers provides flexibility for trick modes and out of sequence decoding.

Semantic or syntax errors are detected by the decoder and failing macroblocks are replaced upto the next slice or picture.

3.8 Digital video inputDigital SD video data can be input to the STx7100 via an 8-bit digital video input port.

The 8-bit mode is intended for inputting SD video data conforming to ITU-R BT656 withembedded syncs or ITU-R BT601 with external syncs. In ITU-R BT656 mode, ancillary dataembedded in the stream can be extracted to a separate buffer.

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3.9 Video display processors

The STx7100 displays video using a main and auxiliary display processors ( Figure 6 ).

The video may have been decoded and reconstructed by the H.264/MPEG2 decoder or acquired

via the digital video interface.The same video or two different videos are displayed via the main and auxiliary displays, buteach may be set up to format the video differently, and display with different timing. Separatevideo timing generators (VTGs) are provided to support this.

The display processors are used to present the video from the display buffers and adapt thedecoded video format to a format suitable for display taking into account differences in scanningmethod, resolution, aspect ratio and scanning frequency.

The main-display processor receives decoded or acquired video from memory and performsblock-to-line conversion, pan and scan, and vertical and horizontal format conversion. There isalso a linear median upconverter (LMU) to perform interlace-to-progressive conversion onstandard definition (SD) pictures using motion estimation.The auxiliary-display processor receives decoded or acquired (and possibly decimated) videoand performs pan and scan, vertical format conversion, horizontal format conversion. The outputsize is limited to an SD format on the auxiliary-display processor, and is intended to output videofor VCR recording.

Figure 6: Display, composition and output

Mainvideo display

processor

Auxiliaryvideo display

processor

Cursor

GDP1

GDP2

VID1

GDP2

VID2

Mixer 1

Mixer 2Auxiliary

output stage

Mainoutput stage

Maindisplay

composition

Auxiliarydisplay

composition

Cursor

Graphics 1

Graphics 2

Graphics 2GDP2 can be assigned to Mixer 1 or Mixer 2

BCK

DVI-HDCPHDMI

Main analogoutputs

YPbPr or RGB

Auxiliary analogoutputs

YPbPr or YC,

STBus

AlphaAlpha planeplane

CVBS

http://-/?-http://-/?-

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3.10 Graphics display

3.10.1 Graphics layers

The STx7100 has two independent and identical graphics layers known as generic displaypipelines (GDPs) (see Figure 6 ). Each GDP receives pixel data from memory and features thefollowing:

● link-list-based display engine, for multiple viewport capabilities,● support for ARGBargb formats, including ARGB1555, ARGB4444, RGB565, RGB888,

ARGB8565, ARGB8888,● support for YCbCr4:2:2R, YCbCr888 formats,● support for premultiplied or non premultiplied RGB components,● color space conversion matrix, (YCbCr 601/709, chroma signed/unsigned to RGB),● gain and offset adjustment,● per-pixel alpha channel combined with per-viewport global alpha,● 5-tap horizontal sample rate converter, for horizontal upsampling. The resolution is 1/8th

pixel (polyphase filter with 8 subpositions),● color keying capability.

3.10.2 Cursor layer

The cursor is defined as a 128 x 128 pixel area held in local memory, in ACLUT8 format. Eachcursor entry is a 16-bit ARGB4444 color + alpha value. The alpha factor of 4 bits handles anantialiased cursor pattern on top of the composed output picture. The cursor-plane features areas follows:

● ACLUT8 format, with ARGB4444 CLUT entries. 256 colors can be simultaneously displayedfor the cursor pattern, among 4096 colors associated with a 16-level translucency channel.

● Size is programmable up to 128 x 128.● Hardware rectangular clipping window, out of which the cursor is never displayed (per-pixel

clipping, so only part of the cursor can be out of this window, and consequently transparent).● Current bitmap is specified using a pointer register to an external memory location, making

cursor animation very easy.● Programmable pitch, so that all cursor patterns can be stored in a single global bitmap.

3.11 Display compositor

The graphic compositor consists of a 5-layer digital mixer (Mix1) intended for the main TV display

(Figure 7 ) and a 2 layer digital mixer (Mix2) intended as an auxiliary display for applicationsincluding connection to a VCR ( Figure 8 ).Each mixer alpha blends graphics and video layers on a pixel by pixel basis based on alphacomponent values provided by each layer.

The Mix1 display planes are as follows:● a background color (RGB888 format, programmable through the registers),● the two graphics layers GDP1 and GDP2,● the main video display,● the cursor plane.

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The Mix2 display planes are as follows:● the auxiliary video display,● the graphics layer GDP2.

Figure 7: Gamma Mix1 planes

Figure 8: Gamma Mix2 planes

Background color

GDP1 graphics

Main v

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ST7100 DS 2005 September