SPU High Level Software

SPU High Level Software 1

PACS IBDR 27/28 Feb 2002

SPU High Level Software

H. Bischof, A.N. Belbachir (TUVIE)F. Kerschbaum, R. Ottensamer, P. Reegen, C. Reimers

(UVIE)



Data Compression/Reduction Scheme

Figure 1. Data Compression/Reduction Scheme

~120Kbits/s1800 Kbits/s

1800 Kbits/s



ASW Requirements - SPU HLSW Data Flow

• Spectroscopy (400 detectors, 50 test channels, 18 empty channels per SPU Module):

– 2000 kbits/s (4000 kbits/s for both SPUs)

• Photometry (512 detectors per sub-image): – 5 sub-images (1700 kbits/s for both SPUs)– 340 kbits for the LWL SPU– 1360 kbits/s for the SWL SPU

• Telemetry rate– ~120 kbits/s are available for science data– Transparent mode: max. of 28 selected detectors in

Spectroscopy or max. of 185 selected detectors in Photometry

– Default mode: Spectroscopy 97,14 kbits/s Photometry 105,3 kbits/s



ASW Requirements - Telemetry rates

Figure 2. Telemetry rates for the SWL and LWL SPU



ASW Requirements - Default Mode in Spectroscopy

Figure 3. Default Compression Mode in Spectroscopy

CRRF = 8

CRINT = 4

CRTSR = 1,6

CR = 51,2



Data Compression/Reduction - Spectroscopy

• Ramp Fitting Methods (1)

Least Squares

RANSACRANSAC+Least Squares

2-Samples Fit




• Ramp Fitting Methods (2)

SDE_ovl_app3SDE_reg_app3






• Evaluation of ramp fitting algorithms and test results Method

256-sample Ramp

Complexity (%)

Performance Evaluation Glitch

Detection Whole 31.0

4 S/Ramps 37.0 Least Squares 8 S/Ramps 39.2

Not recommended for cumulative process. Better precision with ramp

segmentation Not suited

Whole >100 4 S/Ramps >100 RANSAC 8 S/Ramps >100

Slow. Better suited for cumulative process

Whole >100 4 S/Ramps >100 RANSAC+Least Squares 8 S/Ramps >100

Very slow. Best suited for cumulative process

Whole 9.6 4 S/Ramps 13.3 2-Samples Fit 8 S/Ramps 15.6

Fast. Better precision with ramp segmentation

Good to detect

electrical outliers and

glitches

Whole 12.6 4 S/Ramps 17.7

Slope Difference Error (Regular) Approx. 1 8 S/Ramps 17.8

Fast.


Slope Difference Error (Overlap) Approx. 1 8 S/Ramps 9.7

Very fast.



Fast.



Very fast.

Robust to non-linearity and

saturation

Best suited for glitch detection




Ramp 1

Ramp 2

Ramp 3

Performance Method

256-sample Ramp

Ramp 1 Ramp2 Ramp3 Whole NOK NOK NOK

4 S/Ramps OK NOK NOK Least Squares 8 S/Ramps OK OK NOK

Whole NOK NOK NOK 4 S/Ramps OK OK NOK RANSAC 8 S/Ramps OK OK NOK

Whole NOK NOK NOK 4 S/Ramps OK NOK NOK

RANSAC+Least Squares

8 S/Ramps OK OK NOK Whole NOK NOK NOK

4 S/Ramps OK NOK NOK 2-Samples Fit 8 S/Ramps OK OK NOK

Whole OK OK OK 4 S/Ramps OK OK OK

Slope Difference Error (Regular) Approx. 1

8 S/Ramps OK OK OK Whole OK OK OK

4 S/Ramps OK OK OK Slope Difference Error (Overlap) Approx. 1


4 S/Ramps OK OK OK Slope Difference Error (Regular) Approx. 2


4 S/Ramps OK OK OK Slope Difference Error (Regular) Approx. 3

8 S/Ramps OK OK OK




• Analysis with simulated and real test data

• Status– Preprocessing, glitch detection – Ramp Fitting: cumulative errors difference scheme:

RANSAC (2 point with least square errors) implemented– Integration: mean algorithm implemented– TRR & SRR: Reference value & Difference values



ASW Requirements - Default Mode in Photometry

Figure 4. Default Compression Mode in Photometry

CRRF = 4

CRInt = 1

CRTSR = 3,9

CR = 15,6



Data Compression/Reduction - Photometry

• Evaluation of averaging algorithms and test results




Error [%] Plateau 1

Plateau 2

Plateau 3

Mean 0,2 2,5 16,7

Median 0,0 0,3 0,0

Sample Difference 0,1 0,1 0,1

Plateau 1

Plateau 2

Plateau 3

Time

Time

Time

MeanMedianSample DifferenceReal readout

Voltage

Voltage

Voltage




• Analysis with simulated data from our data generator

• Status– Preprocessing, glitch detection– Robust Averaging: mean algorithm implemented

(calibration on ground)– Integration: mean algorithm implemented– TRR & SRR: Reference value & Difference values



SPU HLSW Context Diagram

Figure 5. SPU HLSW Context Diagram



SPU HLSW Concept

Figure 6. SPU HLSW Concept

HLSW consists of three main parts:

• Communication Interfaces to DPU and to DEC/MEC

• Watch Process (Command Acknowledgement)

• Application Software (Reduction/Compression)



SPU SW Interfaces

• DPU TO SPU SW Interface– Communication is bi-directional (commands, response, HK and

compressed data) – All SPU SW activities are commanded by DPU

(e.g. start, stop, …)– SPU SW acknowledges the reception of all DPU commands

according to the communication protocol– SPU SW sends telemetry packets to DPU– DPU checks the “life” of the SPU SW via the HK

• DEC/MEC to SPU SW Interface– Communication is unidirectional (DEC/MEC to SPU) – Packet from DEC/MEC to SPU consists of science data and a

header– Science data are detector readouts and test channels– Header contains the instrument configuration and the

compression parameters



Memory Description

Figure 7. Memory Distribution for the SPU HLSW

• 1.5MB EEPROM• 32KB DPRAM• 7MB RAM

– 1 Mbytes for program storage

– 0.25 Mbytes for SW tables storage

– 1 Mbytes for input science data buffering

– 0.25 Mbytes for the DEC/MEC header buffering

– 0.5 Mbytes for output data buffering

– 4 Mbytes are for processing, etc.

EEPROM (1,5 MB)

DRAM (4 MB)

Processing Buffer(2.5 MB)

Input Buffers(1.25 MB)

Science Data Buffer

(1 MB)

Header

Buffer(256 kB)

Reserved(256 kB)

PRAM (3 MB)

Program Buffer(1MB)

Output Buffer(560 kB)

Table Buffers(256 kB)

DPRAM (32 kB)(SMCS)



SPU HLSW Status• SPU HLSW design frozen

• SPU HLSW Interfaces with DPU and DEC/MEC:

– Interface Control Document are under configuration control

– Software interfaces have been verified under test environment (PC+emulator)

– Detailed description of LLSW drivers are available since 2001, 13 Dec. for the integration on the real HW

• Application Software:

– Mechanism has been verified under test environment (PC+emulator)

– Performance not tested (individual compression modules tested ‘Prelimi.’)

• No real data

• No representative development HW



PA/QA Activities and Schedule• PACS PA Plan is adopted (from IFSI)

• SPU Test Plan is under configuration control

– SPU HLSW Interface tested under test environment (PC+ Emulator+ Spacewire Board)

– SPU HLSW individual module complexity tested in Sigma board

• Schedule

– SPU SW Interfaces and application SW mechanism have been tested

– SPU HLSW functionality will be tested at IAC (Spain)

– Test at IAC is planned in March/April 2002

– Delivery of SPU HLSW to project by begin May



Summary and Perspective

• SPU HLSW Interfaces tested with OBS Simulator

• Preliminary Application SW modules are ready for integration and performance tests in real HW

• Several ramp fitting and averaging algorithms are tested– It is still possible to add new algorithms to this library– New algorithms will be tested (functionality and

performance)

• Verification of SPU HLSW functionality will be done at IAC (Spain) in March/April 2002

Documents

SPU High Level Software