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© Freescale Semiconductor, Inc., 2007. All rights reserved.
Freescale SemiconductorUser’s Guide
The SPTWIMAXCC1E multi-standard baseband advanced mezzanine card (AMC) channel card is a system development platform for worldwide interoperability for microwave access (WiMAX) and wideband code division multiple access (WCDMA) markets. The channel card has a double AMC form factor for use as a standalone card or as part of an advanced TCA platform. It is designed for use as a channel card module for a base station system solution or as a standalone platform for Pico-base station implementation.
The platform is designed around the Freescale MPC8555E PowerQUICC™ III (PQIII) integrated communication processor and the StarCore MSC8126 multi-core DSP. The MPC8555E processor implements the MAC layer processing for WiMAX and WCDMA and the frame protocol processing for WCDMA. Two DSPs implement the upper PHY layer processing, including user domain processing and frequency domain signal processing for WiMAX applications and symbol rate processing for WCDMA applications.
The channel card uses a field-programmable gate array (FPGA) to provide interconnection solutions on the board and algorithmic integration for time domain processing or for chip rate processing. The interconnectivity delivered through the FPGA offers extension to an RF module. In addition, the FPGA has access to high bandwidth DDR2 for memory storage
Contents1 Channel Card Features . . . . . . . . . . . . . . . . . . . . . . . . .22 Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2.1 MPC8555E Subsystem . . . . . . . . . . . . . . . . . . . . . .62.1.1 MPC8555E DDR1 Interface. . . . . . . . . . . . . . . . 62.1.2 MPC8555E Flash Memory Interface . . . . . . . . . .72.1.3 MPC8555E Gigabyte Ethernet Interface . . . . . . .82.1.4 MPC8555E RS-232 Interface . . . . . . . . . . . . . .102.1.5 MPC8555E COP Interface . . . . . . . . . . . . . . . . .102.1.6 MPC8555E Local Bus-to-DSI Interface . . . . . .112.1.7 Asynchronous DSI Interface . . . . . . . . . . . . . . .112.2 MSC8126 DSP-FPGA Processing Block . . . . . . 132.2.1 MSC8126 DSP . . . . . . . . . . . . . . . . . . . . . . . . . .132.2.2 Algorithmic FPGA . . . . . . . . . . . . . . . . . . . . . . .162.3 SerDes FPGA Interface Block . . . . . . . . . . . . . . .202.3.1 Backplane Connector . . . . . . . . . . . . . . . . . . . . .212.3.2 SerDes FPGA Configuration . . . . . . . . . . . . . . 24
3 General Board Configuration . . . . . . . . . . . . . . . . . . .243.1 Reset and Control CPLD (Reset CPLD) . . . . . . . .253.2 Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . .303.3 IRQ Board Interrupt Connectivity . . . . . . . . . . . .313.4 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323.5 MPC8555 Boot Procedure and Configuration . . .333.6 MSC8126 Boot Procedure . . . . . . . . . . . . . . . . . .353.6.1 MSC8126 Standalone Operation . . . . . . . . . . . .353.6.2 Reset Configuration for System Operation. . . . 36
4 Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374.1 MPC8555 Memory Map . . . . . . . . . . . . . . . . . . . .374.1.1 MSC8126 Memory Map . . . . . . . . . . . . . . . . . .39
SPTWIMAXCC1EMulti-Standard Baseband AMC Channel Card
Document Number: SPTWIMAXCCUGAgile Number: UMS-21534
Rev. 0, 04/2007
Multi-Standard Baseband AMC Channel Card, Rev. 0
2 Freescale Semiconductor
Channel Card Features
A serializer/deserializer (SerDes) FPGA provides a serial RapidIO (sRIO) connection to the board AMC connector. Plugged into an ATCA platform or µTCA rack, the channel card interfaces with other AMC platforms, giving it scope for future expansion and development.
Data flow for downlink processing comes onto the board from the 1 Gbps Ethernet port of the MPC8555E processor, either through the RJ45 connector or the AMC connector. After PHY processing, the data can be transmitted through the RF module connected to the channel card. The data flow for uplink processing is the reverse path.
Figure 1. Freescale Multi-Standard AMC Channel Card
1 Channel Card FeaturesProduct features are as follows:
• Target use: benchmarking, proof of concept
• Form factor:
— Full-height, dual-width AMC size
— Layer count: 14 layers
— 1.6 mm thick
• MPC8555E running at 833 MHz to perform MAC layer processing, network interfacing, and overall channel card control functions:
— Communication processor module running (CPM) at 333 MHz
— 2 FCCs allow 100 Mbps Ethernet s ports to interconnect with the MSC8126 DSP
— GigE port connected to an RJ45 and a GigE port connected to the AMC connector
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Freescale Semiconductor 3
Channel Card Features
— Security processor
— Two RS-232 ports
— 16 Mbyte flash memory
— 256 Mbyte DDR1 module, upgradeable to 1 Gbyte
— Bootstrap from flash memory or TFTP from network
— Download of DSP images
• Two MSC8126 DSPs running at 500 MHz to perform the symbol rate portion of the PHY layer processing:
— The 64-bit system bus of each MSC8126 is connected to the algorithmic FPGA
— JTAG ports are chained
— RS-232 port for each DSP
— Each DSP has 100 BaseT port connected to RJ45 or to 100 BaseT port of the MPC8555E
— DSI bus accessible from MPC8555E local bus
— Bootstrapped through the DSI by the MPC8555E
• One EP2S180F1508C3N (Stratix II Altera FPGA) to perform the algorithmic and chip rate portion of the PHY layer processing:
— 1.2 V, CMOS90nm
— #180K equivalent logic elements
— Up to 9 Mbit on-chip memory and 450 MHz internal clock
— Two system bus interfaces with the MSC8126
— DSI bus interface for slave communication with the MPC8555E processor
— One high-speed data interface (HSDI) with FPGA SerDes double 32-bit data bus
— Connectivity to RF module through an ADC interface
— Double 7 segment display available
— 256 Mbyte DDR2 module, upgradeable to 1 Gbyte
— One UART port
• One EP1SGX40DF1020C5 Stratix GX Altera FPGA to perform SerDes interfaces:
— Up to 3.4 Mbit on-chip memory
— Two high speed transceiver channels, dedicated to SerDes capability at a data rate of up to 3.1875 Gbps full duplex
— HSDI (64-bit Tx/Rx) with FPGA algorithmic
— DSI bus interface for slave communication with the MPC8555E processor
— sRIO interface supporting 1X sRIO up to 3.125 Gbauds or 4X sRIO up to 2.5 Gbauds
— EPM240T100C5N (CPLD) to perform on-board power sequencing and reset sequencing
— EPM2210F324C3N (CPLD) to perform MPC8555E local bus interfacing with MSC8126 and FPGA DSI buses
• Power supplies:
— Card supply: 12 V and 3.3 V IPMCV provided by ATCA platform (ATCA mode)
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Hardware
— Card supply: 12 V and 3.3 V IPMCV provided by the power adaptor card (standalone mode)
— On-board supply through variable voltage regulators providing:
– Dedicated 3.3 V for IOs
– Separated 2.5 V for DDR1 and GigE PHY IO devices
– Dedicated 1.8 V for DDR2
– Single 1.5 V for Stratix GX core, SerDes transceiver, and single PHY GigE core
– Dedicated 1.5 V for Stratix GX PLLs
– Separated 1.2 V for MPC8555E, Stratix II, and MSC8126 cores
– Dedicated 1 V for Quad-PHY GigE core voltage
• JTAG:
— Single JTAG header for access to the MPC8555E
— Chained JTAG header for access to the MSC8126 DSPs
— Single JTAG header for Stratix II flash programming
— Chained JTAG header for FPGAs and LB/DSI CPLD
— Single JTAG header for reset CPLD
• Debug support:
— All devices have independent JTAG access
— Real-time debug is supported on the Stratix II FPGA algorithmic through the MICTOR connector
• Connectors:
— Connector for RF interface
— AMC interface
— Single universal asynchronous receiver/transmitter (UART) connector for multiple UARTS
2 HardwareThe channel card hardware consists of the following blocks:
• PowerQUICC III (MPC8555) subsystem
• DSP-FPGA processing block
• Backplane SerDes I/O block
• Board control, (reset, clock, JTAG, and so on)
Figure 2 shows the architecture of the channel card.
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Freescale Semiconductor 5
Hardware
Figure 2. Channel Card Architecture
The board architecture is further subdivided into three main blocks
• PQIII, which is the subsystem implementing the MAC processing through the MPC8555E processor
• DSP–FPGA block implementing the PHY processing through the MSC8126 DSPs
• SerDes FPGA, which gives the board ATCA interconnectivity.
Under typical operating conditions for a downlink chain, the MPC8555E terminates 1000BaseT Ethernet packet traffic from the host through its RJ45 connector or the AMC connector. The subsequent data is placed into MPC8555E external DDR memory. After MAC processing, the data is distributed to the MSC8126 DSPs for upper-layer PHY processing through the MSC8126 DSI port. A CPLD performs the local bus-to DSI-translation. After MSC8126 processing, the data is forwarded through the MSC8126 system bus to the FPGA for additional PHY processing, or it is forwarded to the RF interface through the ADC connector.
LocalUART
GigE
UARTMPC8555E
GigE
Bus
DDR1-SODIMM
SystemFEnt
UART
DSIMSC8126A
JTAG
Bus
SystemFEnt
UART
DSIMSC8126B
JTAG
Bus
PHY
AlgorithmicFPGA
HSDI
System
UARTADC
Clocks
Bus
SystemBus
DDR2-SODIMM
32-bit
sRIOHSDI
SERDES
sRIO
HSDI
HSDI
Flash
FPGA
Flash
64-bit
64-bit
µController
MMC
64-bit
64-bit
RS232RS232
RJ45RJ45RJ45
RS232JTAG
RS232 JTAG
RS232ADC
RESETCPLD
Port[8:11]
Port[4:7]
Port0
I2C
64-bit
64-bit
CPLD
DSI DSI
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Hardware
2.1 MPC8555E SubsystemThe MPC8555 subsystem runs the MAC layer for baseband processing and provides the following functionality on the board (see Figure 3):
• DDR1 memory controller
• Flash ROM memory controller
• Two RS-232 Interfaces
• Two Ethernet Interfaces, one to the front panel and one to the AMC connector
• DSI interface
The MPC8555E Gigabyte Ethernet interface gives access to an external host. Memory is provided by a DDR1 socket (typically 256 Mbytes) for ongoing operation and 16 Mbytes of flash memory for bootstrap. The MPC8555E local bus interfaces to the direct slave interface (DSI) through the LB-DSI CPLD, which demultiplexes the local bus. Two UART interfaces handle user I/O, and a Marvell 88E1145 Quad PHY handles Ethernet I/O.
Figure 3. MPC8555 Subsystem
Table 1 lists the memory controller resources on the MPC8555E processor. Note that CS3 is used to access all devices on the DSI interface. The individual devices are selected thorough address decoding.
2.1.1 MPC8555E DDR1 InterfaceThe MPC8555E system incorporates 256 Mbytes of DDR1 memory for high-bandwidth memory accesses (see Table 2). The memory is unbuffered and controlled by the onboard DDR controller. The 333 MHz rated DDR operates with a 64-bit interface and is physically implemented by a 200-pin SODIMM. The
Table 1. MPC8555 Local Bus Memory Controller Resources
Chip Select Peripheral
CS0 Flash memory (boot)
CS3 Direct slave interface (DSI)
CS4 DSI (broadcast mode)
LocalUART
GigE
UARTMPC8555E
GigE
Bus
PHY 32-bit
Flash
RS232RS232
RJ4564-bit
DDR1-SODIMM DSI
LocalBus
AMC Backplane
CPLDMemory
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DDR memory is directly controlled by the processor memory controller, which provides all the signals necessary for this control.
The DDR configuration is contained in a non-volatile ROM on the DDR DIMM. This ROM is accessed through the processor I2C interface. Using this interface, the processor interrogates the memory to check for its presence, size, speed, and so on. The values read are then used to configure the memory controller DDR configuration registers.
2.1.2 MPC8555E Flash Memory InterfaceThe MPC8555E has 16 Mbytes of flash memory for standalone reset configuration and boot (see Table 3). The flash memory is physically implemented as two AM29LV641D devices and is accessed through the local bus memory controller general-purpose chip-select machine (GPCM). The address and data on the local bus are multiplexed. An external demultiplexer in the LB-DSI CPLD and controlled by the local bus address latch enable (LALE) signal is used to separate the address and data bus.
Table 2. PowerQUICC III DDR1 Interface
Type Signal Description Processor IO
Address OMA[0:12]
OMBA[0:1]
Address signals
Bank address
Output
Data OMDQ[0:63]
OMDQS[0:7]
OMDM[0:7]
Data signals
Data strobe
Data mask
Input/Output
Error Check OMECC[0:7]
OMDQS8
OMDM8
Error check bit
Strobe for error check bits
Mask for error check bits
Output
Clock OMCK1
OMCK_N1
OCKE1
OMCK2
OMCK_N2
OMCKE2
Differential pair clocks and their enable Output
Control Signals OMWE
OMCE[0:1]
OMRAS
OMCAS
Write enable
Chip enable
Row address strobe
Column address strobe
Output
Table 3. Flash Interface Signals
MPC8555E Flash Signal Processor IO
LCS0 FCS Output
LGPL2 FOE Output
LBS[0:1] FWE[0:1] Output
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Hardware
2.1.3 MPC8555E Gigabyte Ethernet InterfaceThe processor implements two Gigabyte Ethernet ports that connect to the outside world through a port at the front of the card with an IEEE® 802.3™-compliant twisted pair port (10/100/1000-BaseT). The other port is routed to the fabric interface on the AMC connector. Each port is controlled by the MPC8555E triple-speed Ethernet controller (TSEC). The TSEC incorporates a MAC that supports 10, 100, and 1000Mbps/802.3 networks. The TSEC includes address, data filtering, data insertion and extraction, 2 Kbyte FIFOs, and DMA functions.
For Gigabyte operation the clocks operate at 125 MHz. To reduce the signal count and make routing easier, the PHYs are connected to the TSEC block through the RGMII interface. The TSECs interface to a Marvell 88E1145 Quad PHY device connecting to two of the four ports, with the other two ports used by the DSPs (see Figure 4). Table 4 lists the signals used.
The PHY is reset from the Reset CPLD during power up via the CPLD signal QPHY_RESET_N. Both ports have a common interrupt which feeds back to the MPC8555 IRQ0 signal. The polarity of this interrupt is programmable (default is low).
Figure 4. Gigabyte Ethernet Interfaces
LAD[0:31] LA[0:31] Output
LAD[0:31] LD[0:15] Input/Output
Table 4. Gigabyte Ethernet Signals
Signal Description Processor IO
GTX_CLK125 Gbit Transmit 125 MHz source Input
GTX_CLK Gbit transmit clock Output
TX_CTL Transmit Control Output
TXD[3:0] Transmit data Output
RX_CLK Receive clock Input
RX_CTL Receive Control Input
Table 3. Flash Interface Signals (continued)
MPC8555E Flash Signal Processor IO
PQIII
RGMII toCopperMDC
MDIOINT
RGMIITSEC1
TSEC2RGMII
PHY88E1145
Port 0
PHY88E1145
Port 1
RGMII toFiber
RJ45(IntegratedMagnetics)
P1AMC
Connector
QPHY_RESET_N
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Hardware
Table 5 details the configuration of ports 0 and 1 of the 88E145 PHY.
RXD[7:0] Receive data Input
MDC Management data clock Output
MDIO Management data Input/Output
Table 5. Ethernet Port Configuration
Pin Bit Description
Port 0 Config [TSEC1]
CONFIG 0 P0_Duplex 0000 Phy address =0000 [Full address = 0x10000]
CONFIG 1 P2_Link10 1011 HWCFG Mode = RGMII to Copper
CONFIG 2 P3_Duplex 1100 Auto negotiation, advertise all capabilities, forced master
CONFIG 3 P3_Link10 1111 ENAXC = Enable auto crossover, DIS_FC = Disable automatic selection of fiber/Copper, DIS_SLEEP = Disable energy detect
CONFIG 4 P0_Duplex 0000 Interface Select = MDC/MDIO, ENA_PAUSE = 00,
Port 1 Config [TSEC2]
CONFIG 0 P0_Link1000 0001 PHY address = 00001 [Full address = 0x10001]
CONFIG 1 P0_Link10 0011 HWCFG mode = RGMII to fiber
CONFIG 2 P3_Duplex 1100 Auto negotiation, advertise all capabilities, forced master
CONFIG 3 P3_Linkl0 1111 ENAXC = Enable auto crossover, DIS_FC= Disable automatic selection of fiber/copper, DIS_SLEEP = Disable energy detect
CONFIG4 P0_Duplex 0000 Interface select = MDC/MDIO, ENA_PAUSE = 00
Port 2 Config [DSP A]
CONFIG 0 P0_Link100 0010 Phy address =000 [Full address = 10010]
CONFIG 1 P3_Link10 1111 HWCFG Mode = GMII to copper
CONFIG 2 P0_Link10 0011 Forced 100BASE-TX, full duplex
CONFIG 3 P3_Link10 1111 ENAXC = Enable auto crossover, DIS_FC = Disable automatic selection of fiber/copper, DIS_SLEEP = Disable energy detect
CONFIG 4 P0_Duplex 0000 Interface select = MDC/MDIO, ENA_PAUSE = 00
Port 3 Config DSP[B]
CONFIG0 P0_Link10 0011 Phy address = 0011 [Full address = 10011]
CONFIG 1 P3_link10 1111 HWCFG Mode = GMII to copper
CONFIG 2 P0_Link10 0011 Forced 100BASE-TX, full duplex
CONFIG 3 P3_Link10 1111 ENAXC = Enable auto crossover, DIS_FC = Disable automatic selection of fiber/copper, DIS_SLEEP = Disable energy detect
Table 4. Gigabyte Ethernet Signals (continued)
Signal Description Processor IO
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Hardware
2.1.4 MPC8555E RS-232 InterfaceAn RS-232 UART through the MPC8555 gives programmable debug or communications capability. A Maxim MAX3387 supplies the level conversion for the interface.
Figure 5. RS-232 Interface
The RS-232 HD3 connector also provides the connections for the other RS-232 devices on the board. Table 6 lists the pinout.
2.1.5 MPC8555E COP InterfaceThe common on port (COP) is part of the MPC8555E JTAG module and is implemented as a set of additional instructions and logic within the JTAG. The COP can connect to a dedicated debug station for extensive system debug. A standard on-board 16-pin header gives access to the COP.
CONFIG 4 P0_Duplex 0000 Interface Select = MDC/MDIO, ENA_PAUSE = 00
Global Signals
GCONFIG0 P0_Duplex 0000 DIS_DTE = Enable DTE detect, Termination = 50 Ω. 1/4MDIO = 4 separate MDIO interfaces; DIS125CLK = Enable125CLK
GCONFIG1 P3_Duplex 1100 LED_TXBLINK = LED is solid on for transmit activity
SIG_DET = use external SD+/- input pins for signal detect status
Interrupt Polarity = Active high
Table 6. RS-232 HD3 Pinout
Device TXD/RXD Pins
PQIII UART0 2/3
PQIII UART1 1/4
DSP A 9/10
DSP B 11/12
FPGA ALGO 7/8
Table 5. Ethernet Port Configuration (continued)
Pin Bit Description
PQIII
UART_SIN0
UART_SOUT0
UART_SIN1
UART_SOUT1
PHYMAX3387
RXD
TXD
RXD
TXD
RS-232Connector
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Freescale Semiconductor 11
Hardware
2.1.6 MPC8555E Local Bus-to-DSI InterfaceThe local bus-to-DSI interface is the main communications path between the MPC8555E processor and the DSP farm. It can also be used as a low-bandwidth control path between the MPC8555E and the two FPGAs. The DSI modes are configurable, as follows:
• Asynchronous mode (default). SRAM-like interface enabling the host for single accesses (with no external clock). Data is transferred using the MPC8555E memory controller UPM.
• Synchronous mode. SSRAM-like interface enabling the host for single or burst accesses of 256 bits (8 accesses of 32 bits) with its external clock decoupled from the MSC8126 internal bus clock.
The DSI gives external hosts direct access to the MSC8126 internal (and external) memory space, including internal memories and the registers of the internal modules. The DSI write buffer stores the address and the data of the accesses. The external host can perform multiple writes without waiting for those accesses to complete. Latencies that are typical during accesses to internal memories are greatly reduced by the DSI read prefetch mechanism. The host addresses each MSC8126 device using a single chip-select; the most significant bits on the address bus identify the addressed MSC8126 device. The 4-bit MSC8126 DSI address is hardwired through CHIP_ID [0:3] (see Table 7). The FPGA chip IDs are programmable and encoded in the FPGA.
Several DSI address lines are multiplexed on the DSI as shown in Table 8. The host can also write the same data to multiple MSC8126 devices simultaneously by asserting a dedicated broadcast chip select.
2.1.7 Asynchronous DSI InterfaceThe DSI is asynchronously controlled through the UPM-controlled signals listed in Table 9. These signals are routed through the CPLD, which operates in a transparent mode. The DSI operates in Dual Strobe mode. Note that in the default asynchronous mode signals, the synchronous signals, HCLKIN and HBST, are not used.
Table 7. MSC8126 DSI Chip ID
Device CHIP_ID[0:3]
DSPA 4b0000
DSP B 4b0010
FPGA ALGO 4b0110
FPGA SERDES 4b0111
Table 8. MSC8126 DSI Addresses
DSI Address Multiplexes With Comment
A7 TT0 Set SIMUCR[TTPC] to 1
A8 HCID3 Tied low
A9 HDST0 n/a
A10 HDST1 n/a
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Hardware
Figure 6 details the local bus-to-DSI implementation.
Figure 6. Local Bus-to-DSI Interface
Table 9. DSI Asynchronous Connection
PQIII UPM Signal MSC8126 Description
LCS3 HBCS Broadcast chip select
LCS4 HCS Chip select
LBS[0:3] HWBS[0:3] Byte strobe
LGPL2 HRDS General purpose (read/write)
LGPL4/UPMWAIT HTA UPMWAIT
HCSHBCSHRW
HCID[0:3]
HWS[0:3]HBSTHTAHCLKIN
HD[0:31]
DSI_A[7:29]
DSP A
ILA8BLA[27:31]FCSFWE[0:1]FOED[0:31]
FLASH
RSTCONF
LB-DSICPLD
A[9:29]
HCSHBCSHRW
HCID[0:3]
HWS[0:3]HBSTHTAHCLKIN
HD[0:31]
DSI_A[7:29]
DSP B
HCSHBCSHRW
HCID[0:3]
HWS[0:3]HBSTHTAHCLKIN
HD[0:31]
A[7:29]
ALGO
HCSHBCSHRW
HCID[0:3]
HWS[0:3]HBSTHTAHCLKIN
HD[0:31]
A[7:29]
FPGA
SERDESFPGA
D[0:5]
LCS[0,3:4]
LGPL[0:4]
PQIII
LAD[0:31]
BLA[28:31]
LWE[0:3]
LBCTL
LALE
LCK0
LGPL4 = UPMWAIT
LB-DSICPLD
100 MHzClock
LGPL[0,3,5]
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Hardware
2.2 MSC8126 DSP-FPGA Processing BlockThe main components of the MSC8126–FPGA block are the two MSC8126 DSPs and the algorithmic FPGA. All three devices are slaves, and the DSPs receive bootstrap, control, and data from the MPC8555. The FPGA receives only control information from the MPC8555; it receives PHY processing information from the RF front-end and DSPs. Bulk storage is available through its DDR2 memory. The main components in the DSP-FPGA processing block are as follows:
• MSC8126 DSI
• MSC8126-to-FPGA system bus interface
• Memory storage through DDR2 memory
• Analog-to-digital controller (ADC) interface
• MSC8126 Ethernet
• RS-232 I/O
Figure 7. DSP-FPGA Processing Block
2.2.1 MSC8126 DSPThis section describes the various interfaces of the MSC8126 DSP.
2.2.1.1 MSC8126 DSI Interface
During powerup, the DSI defaults to 32-bit asynchronous mode with accesses in dual strobe mode. In addition, the DSI configuration registers are programmed to allow the DSI to operate in full address bus mode in which DCR [SLDWA] = 0 and DCR [ADREN] = 0100. Therefore, an external controller (MPC8555) can access MSC8126 internal and external memory using the DSI HA[7:31] address bits. Address bit HA7 is used to differentiate between internal accesses (HA7 = 0) and external accesses (HA7
System
FEnt
UART
DSIMSC8126 A
JTAGBus
System
FEnt
UART
DSIMSC8126 B
JTAGBus
PHY
AlgorithmicFPGA
HSDI
System
UARTADC
Clocks
Bus
SystemBus
DDR2-SODIMM
HSDI
Flash
64-bit
64-bit
64-bit
64-bit
RJ45RJ45
RS-232JTAG
RS-232JTAG
RS-232ADC
64-bit
DSI
HSDIInterface
DSI
32-bit
Memory
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Hardware
= 1). For an external access with HA7 = 1, the HA [8:31] bits are decoded onto the A[8:31] system bus, giving the host a 16 Mbyte address range.
2.2.1.2 MSC8126-to-Algorithmic FPGA Interface
The main communication path between the MSC8126 and FPGA is the high-bandwidth 64-bit 166 MHz system bus. Each MSC8126 DSP has an independent system bus connection to the FPGA for uplink and downlink conversions. A copy of the MSC8126 166 MHz clock is routed to the FPGA for synchronization. Table 10 lists the signals of the FPGA interface.
For simpler applications, a GPCM controller with the signals listed in Table 11 can be used. Each MSC8126 DSP can access a memory region using either CS1 or CS3.
Table 10. MSC8126 FPGA Interface
Memory Controller Signal Description MSC8126 IO
CS1 Chip select 1 Output
CS3 Chip select 3 Output
PGPL[0:3,5] UPM general-purpose line Output
PGPL4/UPMWAIT UPM general-purpose line (or GPCM WE) Output
A[0:31] Address Output
D [0:63] Data Input/Output
PBS[0:7] Bye strobes (PBS0 = POE for GPCM) Output
FA_DSP_60xCLK Clock Input to FPGA
Table 11. GPCM Control of the FPGA Interface
DSP Memory Controller Signal
Connects to FPGA Pin Net Name
DSP A accesses to Memory Region 1
Chip select (CS) H38 DSPA_CS1_FPGA_ALGO
Write enable (WE) E37 DSPA_DQM0
Output enable (POE) F37 DSPA_GPL2
DSP A accesses to Memory Region 2
CS J39 DSPA_CS3_FPGA_ALGO
WE E37 DSPA_DQM0
POE F37 DSPA_GPL2
DSP B accesses to Memory Region 1
CS E26 DSPB_CS1_FPGA_ALGO
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Hardware
2.2.1.3 MSC8126 Ethernet Interface
Each MSC8126 DSP has a fast Ethernet port that is routed to an RJ45 interface. Data is transferred through the MII fast Ethernet port to a Marvel 88E1145 integrated 10/100/1000 quad Gbyte transceiver. DSP A is routed to port 2, and DSP B is routed to port 3. The MII management ports (MDIO and MDC) are implemented using two general-purpose input/output (GPIO) lines (GPIO13 and GPIO19, respectively). This port can be used to write to the internal registers of the PHY. Each port can generate an IRQ to the MSC8126 DSPs.
• Port 2 → DSPA_IRQ1
• Port 3 → DSPB_IRQ1
The Marvel 88E1145 part is configured with the parameters detailed in Table 5.
Figure 8. MSC8126 Ethernet Interfaces
The wiring for the DSP FCC port-to-PHY interface is detailed in Figure 9.
Figure 9. MSC8126 FCC Port
WE B25 DSPB_DQM0
POE C25 DSPB_GPL2
DSP B accesses to Memory Region 2
CS3 F27 DSPB_CS3_FPGA_ALGO
WE B25 DSPB_DQM0
POE C25 DSPB_GPL2
Table 11. GPCM Control of the FPGA Interface (continued)
DSP A
DSP B
Magnetic
Magnetic
RJ45
RJ45
PHY88E1145
Port 2MII
PHY88E1145
Port 3MII
Each DSP controls the PHY throughMDIO/MDC (GPIO13/GPIO9)
IRQ1
TX_ERTX_CLKTXD[0:3]
RX_CLKRX_DVRX_ER
TX_EN
88E1145
CRSCOLRXD[0:3]
MDCMDIO
PHY
MII_TX_ERMII_TX_CLKMII_TXD[0:3]
MII_RX_CLKMII_RX_DVMII_RX_ER
MII_TX_EN
MII_CRSMII_COL
MII_RXD[0:3]
GPIO13GPIO9
MSC8126
Multi-Standard Baseband AMC Channel Card, Rev. 0
16 Freescale Semiconductor
Hardware
2.2.1.4 MSC8126 RS-232 Interface
An RS-232 UART is provided through each of the MSC8126 serial communications interfaces (SCIs) to provide programmable debug or communications capability. A Maxim MAX3387 handles the level conversion for the interface. Note that the receiver inputs are pulled low internally and the transmitter inputs have external pull-ups.
2.2.1.5 MSC8126 JTAG Interface
The MSC8126 EOnCE module allows non-intrusive interaction with the SC140 core in order to examine and analyze registers, memory, and on-chip peripherals. The EOnCE module interfaces with the debugging system through the on-chip JTAG TAP controller pins. The MSC8126 EOnCE JTAG debug ports are connected in a chain to allow simultaneous debug of the complete DSP array. An EOnCE connector on P7 has the following signals:
• TMS. Pulled up so that five TCK clocks put the TAP into the test logic reset state after reset.
• TSRT. This reset signal is pulled low to force the JTAG into reset by default.
• TCK. This clock signal is pulled low to save power in low-power stop mode. TCK can also be pulled high.
• TDI. This input signal is pulled high to save power in low-power stop mode. All JTAG ports have a weak internal TDI pullup.
• TDO. This output signal is pulled high.
• HRESET. This signal is pulled high and also connects to the reset CPLD.
To aid in debugging, several 0 Ω resistors in the JTAG chain allow isolation of either of the MSC8126 DSPs (not shown in Figure 10 )
Figure 10. MSC8126 JTAG
2.2.2 Algorithmic FPGAThe Altera EP2S180F150C3 FPGA provides PHY layer processing in addition to tasks performed by the MSC8126 DSPs. The FPGA interfaces to the MSC8126 DSPs through the system bus and has direct access to 512 Mbytes of DDR2 memory for data storage. MPC8555-generated control information can be
TMSTCKTRST
3
P7 DSPJTAG
Header
1
TMS TCK TRST
DSP A
TDI TDO
HRESET
TMS TCK TRST
DSP B
TDI TDO
HRESET
HRESET9
105
14
CPLD
TDITDO
Multi-Standard Baseband AMC Channel Card, Rev. 0
Freescale Semiconductor 17
Hardware
passed to the FPGA through its DSI port. In addition, it can access the SerDes FPGA through a 64-bit read/64-write high-speed data interface (HSDI). A high-density ADC connector gives external access to the FPGA and is typically used for interfacing to RF modules. A UART is also available for general usage.
2.2.2.1 Algorithmic FPGA DDR2 Memory
The ALGO FPGA has access to 512 Mbytes of DDR2 memory for high-bandwidth memory accesses. The memory is unbuffered and controlled by the FPGA DDR2 controller. The DDR operates with a 64-bit interface and is physically implemented as a 200-pin SODIMM. The address, clock, and control signals are parallel terminated, while the data is on-chip terminated and controlled through the DDR2_ODT[1:0] signals. Table 12 lists the connections. The DDR configuration is contained in a non-volatile ROM on the DDR DIMM that is accessible to the processor I2C interface. Using this interface, the FPGA interrogates the memory to check for its presence, size, speed, and so on. These read values are then used to configure the memory controller DDR configuration registers.
2.2.2.2 Analog-to-Digital Controller (ADC) Interface
The ADC interface gives external access to the FPGA, with a differentially routed point-to- point interface with a control bus and general-purpose I/O as shown in Table 13.
Table 12. FPGA DDR2 Interface
Type Signal Description Processor IO
Address DDR2_A[12:0] Address signals
Bank Address
Output
Data DDR2_DQ[63:0]
DDR2_DQS[7:0]
DDR2_DM[7:0]
Data Signals
Data Strobe
Data Mask
Input/Output
Clock DDR2_CK[1:0] Differential pair clocks and their enable Output
Control Signals DDR2_ODT[1:0]
DDR2_WEn
DDR2_CEn
DDR2_RASn
DDR2_CASn
On chip termination
Write Enable
Chip Enable
Row Address Strobe
Column Address Strobe
Output
Table 13. ADC Interface
Signal Width I/O Standard FPGA Direction Pin Count
DAC_DATA[0:15] 16 LVDS Output 32
DAC_DCLK [ 1 LVDS Output 2
DAC_SDO 1 LVTTL Output 1
DAC_SDIO 1 LVTTL Input 1
DAC_SCLK 1 LVTTL Output 1
DAC_CSB 1 LVTTL Output 1
Multi-Standard Baseband AMC Channel Card, Rev. 0
18 Freescale Semiconductor
Hardware
2.2.2.3 High-Speed Data Interface
The HSDI provides high bandwidth access to the SerDes FPGA and ultimately to the SERDES backplane. The bus is point-to-point, and its signals are described in Table 14.
2.2.2.4 Algorithmic FPGA RS232 Interface
An RS-232 UART is available through the HD3 connector. A Maxim MAX3387 provides the level conversion for the interface. The receiver inputs are pulled low internally, and the transmitter inputs have external pullups.
2.2.2.5 Algorithmic FPGA Configuration
The options for programming the FPGA are as follows:
• Use the EPCS64 configuration chip to program FPGA external flash memory. This is the active serial (AS) configuration scheme and is the default mode on the card.
• Program directly from the CPLD/FPGA JTAG header (HD5) into the FPGA internal RAM.
• Use the MPC8555 device to program the FPGA.
ADC_DATA[0:15] 16 LVDS Input 32
ADC_DCLK 1 LVDS Input 2
ADC_OVR 1 LVDS Input 2
PLL_CLKOUT_spare 1 LVDS Output 2
PLL_CLKIN_spare 1 LVDS Input 2
PLL_CLKIN_FB_spare 1 LVDS Input 2
DAC_SSCLK 1 LVDS Input 2
RF_BRD_CTRL[0:31] 32 LVTTL Input/Output 32
Table 14. HSDI Interface
Signal Description ALGO FPGA I/O
HSDI_RXCLK Receive clock Input
HSDI_RXD[0:63] Receive data Input
HSDI_RX_CTL[1:2]
HSDI_RX_VALID
Receive Control Input
HSDI_TXCLK Transmit Clock Output
HSDI_TXD[0:63] Transmit Data Output
HSDI_TX_CTL[1:2]
HSDI_TX_VALID
Transmit Control Output
Table 13. ADC Interface (continued)
Signal Width I/O Standard FPGA Direction Pin Count
Multi-Standard Baseband AMC Channel Card, Rev. 0
Freescale Semiconductor 19
Hardware
The HD4 header can be used to program the external Flash memory. The configuration settings are controlled through the signals MSEL[3:0] on the SW4 switch. HD5 can be used to program the FPGA internal memory. Table 15 shows the JTAG connection for this mode.
Figure 11 details the FPGA-to-flash memory connections. For future use, the FPGA can also be programmed from the MPC8555 using GPIO lines.
Figure 11. FPGA/CPLD JTAG Scheme
Table 15. FPGA Algorithmic Configuration
Configuration Scheme MSEL[3:0] = SW4[1:4] Comment
Fast AS (40 MHz) 1000 1=ON
0=OFFRemote system upgrade fast AS (40 MHz) 1001
AS (20 MHz) (default) 1101
Remote System upgrade fast AS (20 MHz) 1110
CPLD_LB_TDISERDES_TDOSERDES_TDI
RESETCPLD
TMS TCK
ALGO
TDI TDO
CPLD_LB_TDO
FALGO_TDOFALGO_TDITDI_JTAG_FPGA
TDO_JTAG_FPGA
HD5
3
TMS TCK
SERDESTDI TDO
µController
TMS TCK
SERDES
TDI TDO
TMS TCK
LB/DSI
TDI TDO
TMS_JTAG_FPGATCK_JTAG_FPGA
9
51
Multi-Standard Baseband AMC Channel Card, Rev. 0
20 Freescale Semiconductor
Hardware
Figure 12. FPGA Configuration Scheme
2.3 SerDes FPGA Interface BlockThe Altera EP1SGX40DF1020C5 FPGA (SerDes FPGA) provides system access to the Fabric interface through AMC backplane edge connector P1. The SerDes FPGA interfaces to the edge connector through two x4 SRIO interfaces that are each programmable from 1.25 Gbps, 2.5 Gbps, and 3.125 Gbps. Data can then be transferred to the algorithmic FPGA for processing through the high-bandwidth HSDI. A DSI port on the SerDes FPGA is for control applications.
MSEL1MSEL2MSEL3
Data0DCLK
(F22)nCS0
MSEL0
ASDI0
CONF_DONE(F33)nCONFIG(AM30)NCE(B36)
nSTATUS(A37)
ALGO FPGAStratix-II
FALGO_CONF_DONEFALGO_nSTATUS
FALGO_nCONFIGnCE
FPGA_DATA0
DCLKnCSASDI
Data
EPCS64
FALGO_ASDIFALGO_NCS0FALGO_DCLK
Switch(1 or 0)
PC17PC21PC18
PD14PC16PC14PC22
PC15
MPC8555
189
7
Header
56
3
CONFIG_DATA[0:7]
PQIII_CONFIG_DATA0
PQIII_CONFIG_DATA[1:7]
10k
10k10k
10k
CONFIG_DATA[0:7]
SERDES FPGA
EPC16UC88U15
Microcontroller
MultiplexerIDTQS3VH16233
12B1
EPC_CONFIG_DATA[0:7]
Multi-Standard Baseband AMC Channel Card, Rev. 0
Freescale Semiconductor 21
Hardware
Figure 13. SERDES Interface Block
2.3.1 Backplane Connector
The backplane connector provides connectivity to a total of 170 conductive traces on both sides of the module design. The connector interfaces to the following:
• Two 4x SRIO (16 wire) for the SerDes FPGA
• Gigabyte fibre interface for MPC8555 TSEC2
• AMC clocks
The channel card is mechanically designed to fit into an AMC slot through its P1 connector. The connector is hard gold-plated for insertion durability. The pinout of this connector is listed in Table 16.
Table 16. AMC Connector Site Pin Definitions
Pin No.AMC
DefinitionSignal
DescriptionPin # AMC Definition Signal Description
01 GND 170 GND
02 +12V 169 TDI n/c
03 PS1# 168 TDO n/c
04 MP IPMCV 167 TRST n/c
05 GA0 GA0 166 TMS n/c
06 RSRVD n/c 165 TCLK n/c
07 GND 164 GND
08 RSRVD n/c 163 TX20+ n/c
09 +12V 162 TX20- n/c
10 GND 161 GND
11 TX0+ P1_SOUT_P 160 RX20+ n/c
12 TX0- P1_SOUT_N 159 RX20- n/c
SRIO
SERDES
DSI
HSDI SIRO
FPGA
DSI
32-bit
64-bit
64-bit
HSDIHSDI
µController
Port[4:7]
Port[8:11]
Multi-Standard Baseband AMC Channel Card, Rev. 0
22 Freescale Semiconductor
Hardware
13 GND 158 GND
14 RX0+ P1_SIN_P 157 TX19+ n/c
15 RX0- P1_SIN_N 156 TX19- n/c
16 GND 155 GND
17 GA1 GA1 154 RX19+ n/c
18 +12V 155 RX19- n/c
19 GND 152 GND
20 TX1+ n/c 151 TX18+ n/c
21 TX1- n/c 150 TX18- n/c
22 GND 149 GND
23 RX1+ n/c 151 RX18+ n/c
24 RX1- n/c 150 RX18- n/c
25 GND 146 GND
26 GA2 GA2 145 TX17+ n/c
27 +12V 144 TX17- n/c
28 GND 143 GND
29 TX2+ n/c 142 RX17+ n/c
30 TX2- n/c 141 RX17- n/c
31 GND 140 GND
32 RX2+ n/c 139 TX16+ n/c
33 RX2- n/c 138 TX16- n/c
34 GND 137 GND
35 TX3+ n/c 136 RX16+ n/c
36 TX3- n/c 135 RX16- n/c
37 GND 134 GND
38 RX3+ n/c 133 TX15+ n/c
39 RX3- n/c 132 TX15- n/c
40 GND 131 GND
41 ENABLE # ENABLE_N 130 RX15+ n/c
42 +12V 129 RX15- n/c
43 GND 128 GND
44 TX4+ SRIO_TD0 127 TX14+ n/c
Table 16. AMC Connector Site Pin Definitions (continued)
Pin No.AMC
DefinitionSignal
DescriptionPin # AMC Definition Signal Description
Multi-Standard Baseband AMC Channel Card, Rev. 0
Freescale Semiconductor 23
Hardware
45 TX4- SRIO_TD_N0 126 TX14- n/c
46 GND 125 GND
47 RX4+ SRIO_RD0 124 RX14+ n/c
48 RX4- SRIO_RD_N0 123 RX14- n/c
49 GND 122 GND
50 TX5+ SRIO_TD1 121 TX13+ n/c
51 TX5- SRIO_TD_N1 120 TX13- n/c
52 GND 119 GND
53 RX5+ SRIO_RD1 118 RX13+ n/c
54 RX5- SRIO_RD_N1 119 RX13- n/c
55 GND 116 GND
56 SCL_L AMC_SCL 115 TX12+ n/c
57 +12V 114 TX12- n/c
58 GND 113 GND
59 TX6+ SRIO_TD2 112 RX12+ n/c
60 TX6- SRIO_TD_N2 111 RX12- n/c
61 GND 110 GND
62 RX6+ SRIO_RD2 109 TX11+ SRIO2_TD3
63 RX6- SRIO_RD_N2 108 TX11- SRIO2_TD_N3
64 GND 107 GND
65 TX7+ SRIO_TD3 106 RX11+ SRIO2_RD3
66 TX7- SRIO_TD_N 105 RX11- SRIO2_RD_N3
67 GND 104 GND
68 RX7+ SRIO_RD3 103 TX10+ SRIO2_TD2
69 RX7- SRIO_RD_N3 102 TX10- SRIO2_TD_N2
70 GND 101 GND
71 SDA_L AMC_SDA 100 RX10+ SRIO2_RD2
72 +12V 99 RX10- SRIO2_RD_N2
73 GND 98 GND
74 CLK1+ AMC_CLK1_p 97 TX9+ SRIO2_TD1
75 CLK1- AMC_CLK1_n 96 TX9- SRIO2_TD_N1
76 GND 95 GND
Table 16. AMC Connector Site Pin Definitions (continued)
Pin No.AMC
DefinitionSignal
DescriptionPin # AMC Definition Signal Description
Multi-Standard Baseband AMC Channel Card, Rev. 0
24 Freescale Semiconductor
General Board Configuration
2.3.2 SerDes FPGA ConfigurationThe options for programming the FPGA SerDes are as follows:
• Use the configuration device EPC16UC88 to program the FPGA external flash memory through the HD5 header.
• Program directly from the CPLD/FPGA JTAG header (HD5) into the FPGA internal RAM.
• Use the MPC8555 to program the FPGA.
The configuration schemes in which the FPGA operates are listed in Table 17. The default method is to program the FPGA in passive serial (PS) configuration mode using the HD5 header. The Serdes FPGA can also be programmed from the MPC8555 through its GPIO pins. Switch SW2.4 selects this function. Note that this function is not currently implemented and SW2.4 should be switched to OFF.
3 General Board ConfigurationGeneral board configuration pertains to reset CPLD, clock distribution, board interrupt connectivity, LEDs, MPC8555 boot procedure and configuration, and the MSC8126 boot procedure.
77 CLK2+ AMC_CLK2_p 94 RX9+ SRIO2_RD1
78 CLK2- AMC_CLK2_n 93 RX9- SRIO2_RD_N1
79 GND 92 GND
80 CLK3+ AMC_CLK3_p 91 TX8+ SRIO2_TD0
81 CLK3- AMC_CLK3_n 92 TX8- SRIO2_TD_N0
82 GND 89 GND
83 PS0# PS0_N 88 RX8+ SRIO2_RD0
84 +12V 87 RX8- SRIO2_RD_N0
85 GND 86 GND
Table 17. FPGA SerDes Configuration
Configuration Scheme MSEL[2:0] = SW2[3:1] Comment
FPP Configuration 000 1=ON
0=OFFPPA Configuration 001
PS Configuration [Default] 010
Remote/local Update FPP 100
Remote/local Update PPA 101
Remote/local Update PS 110
Table 16. AMC Connector Site Pin Definitions (continued)
Pin No.AMC
DefinitionSignal
DescriptionPin # AMC Definition Signal Description
Multi-Standard Baseband AMC Channel Card, Rev. 0
Freescale Semiconductor 25
General Board Configuration
3.1 Reset and Control CPLD (Reset CPLD)The Multi-Standard AMC Channel Card can operate in standalone mode, or it can be plugged into an ATCA carrier card. In each mode, the CPLD operates differently in terms of how power is enabled on the card. In standalone mode, push button switch SW7 acts as the power switch to enable power on the card. When the channel card is plugged into an ATCA carrier card, a value of zero on the edge connector ENABLE signal is used as the power enable. Table 18 lists the switch settings for the two powerup modes.
At powerup in either mode, the external supply first switches on the reset CPLD IPMCV voltage (3V3). After the CPLD is on, it asserts the ATX_PS_ON control signal to the PSU to switch on the 12 V to the card. The CPLD then waits until the PSU asserts the power OK signal (ATX_PS_OK). Then the CPLD sequentially switches on the individual voltages to ensure a stable supply. Figure 14 details the power circuitry.
The 12v Synquor power modules provide the DC-DC conversion for the 1.2 V MSC8126, algorithmic FPGA and MPC8555 core voltages, the 1.5 V Serdes FPGA core voltage, and the 3.3 V general I/O. Smaller DC-DC voltage regulators provide the Ethernet PHY voltages. The DDR1 and DDR2 voltages are generated using a TPS51116 synchronous buck controller. The power to the board can be recycled through the SW7 push button switch.
Table 18. Powerup Modes
Switch Setting Description [Standalone Mode]
SW5.2 ON Switch on external PSU
SW5.3 ON Stand Alone Operation
Switch Setting Description [ATCA Chassis]
SW5.2 OFF Switch off external PSU
SW5.3 OFF Select ATCA rack
Multi-Standard Baseband AMC Channel Card, Rev. 0
26 Freescale Semiconductor
General Board Configuration
Figure 14. Power Circuitry
The CPLD and its associated clock source and reset source are continuously powered from the IPMC voltage supply to the AMC. The internal reset generator provides a retimed internal reset signal based on the input from the external reset source. Because the CPLD is continuously powered, the external reset generator has a push-button switch to allow a reset to be generated to the CPLD without disconnecting the external supply. This switch is for use during debugging.
The strobe generator provides a timing pulse with a repetition period of 30 msec, assuming a clock frequency of 66 MHz. The timing pulse is the fundamental timing signal within the CPLD and is used for the switch debouncing logic, the timing of reset periods, and other internal functions.
The input handler provides debouncing of the power switch and reset push button switch, based on the timing strobe interval of 30 msec. It also monitors reset requests from the CPU for activity. It provides enable signals to the power sequencer and reset sequencer modules to start power and reset generation sequences.
RESETCPLD
1V2_PQIII_Power_On
ATX_PS_OK
ATX_PS_ON
IPMCV(3.3 V)
12 VPowerModule
PowerModule
PowerModule
PowerModule
3V3_Power_OnPowerModule
MAX8556
I/O
1V2_PQIII
2.5 V2V5_Power_On
1V2_FPGA
1V2_DSP
1.5 V
1 V
DDR2_Power_GoodTPS51116
LT1529GVDDVTT(0.9 V)MVREF0
DDR2_LT1529_PowerOn
DDR2_S3_PowerOnDDR2_S5_PowerOn VCCIO_1V8
DDR2 FPGAALGO
L
DDR1_Power_GoodTPS51116
LT15295V-R12.5V_DDR1VTT0(1.25 V)VREF0
DDR1_LT1529_PowerOn
DDR1_S3_PowerOnDDR1_S5_PowerOn
DDR1
1V2_FPGA_Power_On
1V2_VAR_Power_On
1V5_Power_On1V_Power_On1V_Power_OK
5V-R2
PQIII
EthernetPHY
88E1145and RJ45
LT1764
ALGOFPGA
SerDesFPGA
SerDesFPGA
ALGOFPGA
PQIII
DSP A DSP B
3.3 V
Multi-Standard Baseband AMC Channel Card, Rev. 0
Freescale Semiconductor 27
General Board Configuration
The power sequencer provides on/off control and monitoring for the 12 V hot swap controller and the on-board voltage regulators. The reset sequencer in Figure 15 sends the reset signals for the MPC8555, MSC8126 DSPs, algorithmic FPGA, SerDes FPGA, and other peripheral devices on the card. It also sends the enable signal to the configuration data buffer for the MPC8555 and MSC8126. The reset sequence is designed to bring up the MPC8555, MSC8126 DSPs, and FPGAs in a controlled sequence.
Figure 15. CPLD Block Diagram
Table 19 lists interface signals for the CPLD and their functionality. Some CPLD functions are not used on the current AMC card, but the necessary pins are identified here for future use. This section is subject to change as additional features/functionality are added.
Table 19. Reset CPLD Control Signals
Pin SignalPin No.
DIR Description
Clocks, Reset
PLD_CLK 12 In 66 MHz clock In
8126_PORESET 84 Out Active low DSP configuration pin buffer control
DSPA_PORESET 48 Out Active low power-on reset for DSP A
DSPB_PORESET 50 Out Active low power-on reset for DSP B
RESET_FPGA_SERDES 36 Out Active low power-on reset for SerDes FPGA
RESET_FPGA_ALGO 39 Out Active low power-on reset for ALGO FPGA
DSPA_HRESET 49 Out Active low HRESET input to DSP A
DSPB_HRESET 51 Out Active low HRESET input to DSP A
RESET_N 85 Out Active low flash memory reset
InternalReset
Generator
On-BoardRegulators
12 VSwitch
PowerSequencer
LEDHandler
InputHandler
ResetSequencer
StrobeGeneratorReset/Control
CPLD
PLD_CLKBoot ProcessorReset Interface
RESETOn-Board
LEDsReset Request Sources
and DIP Switches
Multi-Standard Baseband AMC Channel Card, Rev. 0
28 Freescale Semiconductor
General Board Configuration
QPHY_RESET_N 86 Out Active low quad PHY reset
SEL_ETH_DSPA 77 0ut DSP A Ethernet multiplexer
SEL_ETH_DSPB 76 0ut DSP B Ethernet multiplexer
RESET_DSPA 27 In MPC8555 port line PC8 controls DSP A HRESET
RESET_DSPB 28 In MPC8555 port line PC9 controls DSP B HRESET
CPU Interfaces
8555_RSTCONF_N 83 Out Active low enable for configuration data buffer
8555_HRESET_N 82 Out Active low HRESET signal to MPC8555
8555_SRESET_N 81 Out Active low JTAG SRESET to MPC8555
8555_TRST_N 78 Out Active low JTAG reset to MPC8555
8555_COP_HRESET_N 29 Out
O.D.
Active low HRESET from the COP Interface (pin 13)
8555_COP_SRESET_N 30 In Active low SRESET to/from the COP Interface (pin 11)
8555_COP_TRST_N 34 In Active low JTAG reset from JTAG header (pin4)
8555E_HRESET_REQ_N 33 In Active low request o/p from MPC8555
Switch Interfaces
PORST 3 In Active low debounced push button reset switch
PB_RESET_N 2 In Active low debounced push button reset switch
USR0 4 In DIP switch SW5.1 input
USR1 5 In DIP switch SW5.2 input
USR2 6 In DIP switch SW5.3 input
USR3 7 In DIP switch SW5.4 input
Power Supply Interfaces
3V3_Power_On 100 Out Active high output to enable on-board 3.3 V regulation
1V2_PQIII_Power_On 95 Out Active high output to enable MPC8555 1.2 V core voltage
1V2_VAR_Power_On 97 Out Active high output to enable DSP 1.2 V core voltage
1V2_FPGA_Power_On 96 Out Active high output to enable FPGA 1.2 V core voltage
1V5_Power_On 99 Out Active high output to enable FPGA 1.5 V voltage
2V5_Power_On 18 Out Active high output to enable 2.5 V core voltage of the PHYs
1V_PowerON 17 Out Active high output to enable Quad PHY 1 V magnetic
DDR1_LT1529_PowerOn 89 Out Active high output to enable 2.5 V/1.25 V DDR1 voltage
DDR1_S5_PowerOn 88 Out Active high output to enable on-board DDR1 voltage regulation
Table 19. Reset CPLD Control Signals (continued)
Pin SignalPin No.
DIR Description
Multi-Standard Baseband AMC Channel Card, Rev. 0
Freescale Semiconductor 29
General Board Configuration
DDR1_S3_PowerOn 87 Out Active high output to enable on-board DDR1 voltage regulation
DDR1_Power_Good 20 In Active low DDR1 power good indicator
DDR2_LT1529_PowerOn 92 Out Controls the 1.8 V/0.9 V DDR2 voltage
DDR2_S5_PowerOn 91 Out Active high output to enable on-board DDR2 voltage regulation
DDR2_S3_PowerOn 90 Out Active high output to enable on-board DDR2 voltage regulation
DDR2_Power_Good 20 In Active low DDR1 power good indicator
PS_ON_ATX 1 in Active high power enable from carrier
ATX_POWER_PLUGGED 8 In Active low operation signal from IPMC
SYSTEM_SHUTDOWN 15 In Active low operation signal from IPMC
PWR_ENABLE 16 In Active low operation signal from IPMC
Power_not_OK 19 In Active low operation signal from IPMC
ENABLE_N 26 In Active low operation signal from carrier card
SYSTEM_RESET_N 35 In Active low operation signal from carrier card
Miscellaneous Interfaces
DSPA_EE0 75 out Active high force DSP A into debug signal
DSPB_EE0 74 out Active high force DSP B into debug signal
LED_N0 44 out LED(LD5) Control (0/1 = on/off)
LED_N1 43 out LED(LD6) Control (0/1 = on/off)
LED_N2 64 out LED(LD7) Control (0/1 = on/off)
LED_N3 62 out LED(LD8) Control (0/1 = on/off)
CPLD_GPIO1 71 in Connects to DSP A GPIO25
CPLD_GPIO2 70 In Connects to DSP B GPIO25
CPLD_GPIO3 69 In Connects MPC8555 port line PA22
CPLD_GPIO4 68 In Connects MPC8555 port line PA23
CPLD_GPIO5 67 In Connects MPC8555 port line PA24
CPLD_GPIO6 66 In Connects MPC8555 port line PA25
CPLD_GPIO7 61 In Connects to ALGO FPGA [pin:N24]
CPLD_GPIO8 58 In Optional logic 1/0 strap
CPLD_GPIO9 57 In Optional logic 1/0 strap
CPLD_GPIO10 56 In Connects to SerDes FPGA
Table 19. Reset CPLD Control Signals (continued)
Pin SignalPin No.
DIR Description
Multi-Standard Baseband AMC Channel Card, Rev. 0
30 Freescale Semiconductor
General Board Configuration
3.2 Clock DistributionThe channel card has three clock regions
• MPC8555 (see Table 20)
• MSC8126/FPGA clocking (see Table 21)
• Ethernet
The MPC8555 system clock is generated from a single 33 MHz clock. The local bus clock is then fed out to LB-DSI CPLD.
The MSC8126 CLKIN signals are generated from a single 166 MHz oscillator, which is distributed through the IDT23S09 low skew output buffer to the MSC8126 farm and FPGAs. Clock mode 0 is used on the MSC8126 to give a core frequency of 500 MHz and a system bus of 166 MHz
CPLD_GPIO11 55 In Connects MPC8555 port line PC6
CPLD_GPIO12 54 In Connects MPC8555 port line PC7
CPLD_GPIO18 53 In Connects LB-DSI CPLD [K17] and ALGO FPGA [N14]
CPLD_GPIO19 54 In Connects LB-DSI CPLD [K16] and ALGO FPGA [N13]
JTAG
SERDES_TDI 37 out JTAG chain output to SerDes
SERDES_TDO 38 in JTAG chain output from SerDes
FALGO_TDI 40 out JTAG chain output to FALGO
FALGO_TDO 41 in JTAG chain output from FALGO
TDI_JTAG_FPGA 42 in JTAG input from header
TDO_JTAG_FPGA 47 out JTAG output to header
Table 20. MPC8555 Clock Frequencies
CLKIN CCB DDR Interface Core
33 MHz 333 MHz 166 MHz 833 MHz
Table 21. MSC8126 Clock Frequencies
Clock Mode CLKIN Core Bus
0 166 MHz 500 MHz 166 MHz
Table 19. Reset CPLD Control Signals (continued)
Pin SignalPin No.
DIR Description
Multi-Standard Baseband AMC Channel Card, Rev. 0
Freescale Semiconductor 31
General Board Configuration
In Ethernet PHY to DSP operation, the 25 MHz Ethernet receive and transmit clocks are generated by the PHY and fed back to the MSC8126s. In PQIII MAC to DSP MAC mode, receive and transmit clocks are generated by a 25 MHz oscillator and fed back to both PQIII and the DSP.
Figure 16. MSC8126 and FPGA Clocking
3.3 IRQ Board Interrupt ConnectivityThe channel card has an extensive interrupt scheme to facilitate communications between all devices. The interrupt scheme consists of the following interrupt types:
• Direct hardwired interrupts between devices
• Software wired interrupts through the LB-DSI CPLD. The CPLD can be pre-programmed as the user requires.
Figure 17 details the layout. Note that the CPLD is preprogrammed with the default interrupts shown as the dotted line in the figure.
MSC8126 A(DSP A)
MSC8126 B(DSP B)
ALGOFPGA
SerDesFPGA
166 MHzOscillator
IDT23S09
Multi-Standard Baseband AMC Channel Card, Rev. 0
32 Freescale Semiconductor
General Board Configuration
Figure 17. Interrupt Connectivity
3.4 LEDsSurface mount 0603 footprint LEDs throughout the platform enable debugging and facilitate interfacing. Their positions and associated device are shown in Figure 18.
IRQ2IRQ3
GPIO15GPIO16
IRQ5IRQ6
GPIO19
IRQ1MSC8126 A
GPIO20GPIO21
IRQ4IRQ7
GPIO17GPIO18INT_OUT
IRQ2IRQ3
GPIO15GPIO16
IRQ5IRQ6
GPIO19
IRQ1MSC8126 B
GPIO20GPIO21
IRQ4IRQ7
INT_OUT
Ethernet PHY(Port C)
GPIO17GPIO18
RESETCPLD
GPIO18_DSPAINT_OUT_DSPA
GPIO17_DSPB
Ethernet PHY(Port D)PA8
PD29PD3PA9
IRQ2IRQ3IRQ4IRQ5
MPC8555
IRQ2_PQIII
IRQ5_PQIII
IRQ3_PQIIIIRQ4_PQIII
GPIO17_DSPA
GPIO18_DSPBINT_OUT_DSPB
GPIO2GPIO3GPIO4
IRQ1IRQ2IRQ3IRQ4
GPIO1
ALGO
IRQ7IRQ8
GPIO10GPIO11
IRQ5
GPIO12
IRQ6GPIO5
DSPA_INT_OUTDSPB_INT_OUT
FPGA
GPIO17GPIO18GPIO19GPIO20GPIO21
GPIO6GPIO7
GPIO13
GPIO16
GPIO14GPIO15
PC24PC25PC26PC28
PA10PA11IRQ6
LB/DSICPLD
GPIO5IRQ1IRQ2IRQ5IRQ6
GPIO4
SerDesIRQ3IRQ4GPIO3
GPIO2GPIO1
FPGAPA12PA13IRQ7
IRQ0Ethernet PHY
(Port A/B)NOTES:
1. Not shown in diagram.DSPA_DREQ1 → FPGA ALGO (K14)DSPB_DREQ1→ FPGA ALGO (K13)
2. Default CPLD connections shown.
Multi-Standard Baseband AMC Channel Card, Rev. 0
Freescale Semiconductor 33
General Board Configuration
Figure 18. LED Locations
3.5 MPC8555 Boot Procedure and ConfigurationA switch is used to select the MPC8555 mode of operation. The MPC8555 processor can operate with uBoot mode enabled or disabled. The effect of this switch is to toggle the MSB address line to the flash memory so the MPC8555 either jumps into empty flash (SW3.1= OFF) at 0xFF7FFFFC or jumps into uBoot mode and executes the boot sequence (SW3.1 = ON) at 0xFFFFFFFC.
Table 22. MPC8555 Boot Modes
Switch Position Description
SW3.1 ON uboot/Linux boot
SW3.1 OFF Disable uboot/Linux
RESET CPLDSwitch
SERDES FPGASwitch
RESETCPLD JTAG
AMC Connector(P1)
ALGO
Power Reset
Board Reset
SERDES
PQIII JTAG(HD2)
(HD1)
ADC Interface(P8)
ALGO FPGAFlash JTAG
(HD4)
ALGO FPGADisplay
Multi-RS232 Interface(HD3)
CPLD/FPGA JTAG(HD5)
DDR2 Socket(P9)
Power Socket(J5)
(SW9)
(SW10)
(SW7)
DSP JTAG(P7)
(SW6)
SeeSerDes FPGA
See LEDs
LD12LD13LD14LD16 ALGO FPGA (LD11)
ALGO FPGA (LD15)ALGO FPGA (LD17)ALGO FPGA (LD18)
DSPA (LD9)DSPB (LD10
RESET CPLD (LD5)RESET CPLD (LD6)RESET CPLD (LD7)RESET CPLD (LD8)
RX ETH Port4 (LD2)TX ETH Port4 (LD4)
SerDes FPGA LEDs
LB/DSI CPLD (LD1)LB/DSI CPLD (LD3)
(LD19)
DDR1 Socket(P4)
(SW5)
(SW8)
Multi-Standard Baseband AMC Channel Card, Rev. 0
34 Freescale Semiconductor
General Board Configuration
At power-up, the MPC8555 samples several signals as part of its configuration process. Eight of these signals are configurable through DIP switches, and the rest are hardwired, as described in Table 23.
Table 23. MPC8555 Configuration Settings
Switch Setting Description Comment Signal
SW1.1
SW1.2
SW1.3
SW1.4
OFF
ON
OFF
ON
b1010 => 10:1
33.3 MHz × 10 = 333 MHz
CCB clock: SYSCLK ration LA28
LA29
LA30
LA31
SW1.5
SW1.6
ON
OFF
b10 → 3:1
333 MHz × 2.5 = 833 MHz
e500 Core: CCB clock ratio LALE
LGPL1
SW1.7
SW1.8
OFF
OFF
b11 → One added buffer delay
(0 added delay for LALE)
Local bus output hold configuration
LWE0
LWE1
Pull up 1 The e500 core is allowed to boot without waiting for configuration by an external master (default)
CPU boot configuration LA27
Pull up 1
1
1
Local bus GPCM = 32-bit ROM (default)
Boot ROM location LGPL0
LGPL1
LWE3
Pull up 1 MPC8555 acts as a host on PCI (default)
Host/Agent configuration LWE2
Pull up 1
1
Boot sequence is disabled. No I2C ROM is accessed (default)
Boot sequencer configuration LGPL3
LGPL5
Pull low 0 Ethernet interfaces operate in reduced mode, either RTBI or RGMII using only 4 Tx and Rx signals
TSEC width configuration MDC
Pull low 0 The TSEC1 controller operates using the GMII/RGMII protocol
TSEC1 protocol configuration TSEC2_TXD3
Pull low 0 The TSEC1 controller operates using the GMII/RGMII protocol
TSEC2 protocol configuration TSEC2_TXD2
Connected to ETH PHY
Z PCI1 clock selection Not used TSEC2_TXD1
Connected to ETH PHY
Z PCI2 clock selection Not used TSEC2_TXD0
Pulled High 1 PCI32 configuration Not used PCI2_Frame
Pulled High 1 PCI1 I/O impedance Not used PCI1_GNT1
Pulled High 1 PCI2 I/O impedance Not used PCI2_GNT1
Pulled High 1 PCI1 arbiter configuration Not used PCI1_GNT2
Pulled High 1 PCI2 arbiter configuration Not used. PCI2_GNT2
Pulled High 1 PCI debug configuration Not used PCI2_GNT3
Multi-Standard Baseband AMC Channel Card, Rev. 0
Freescale Semiconductor 35
General Board Configuration
3.6 MSC8126 Boot ProcedureThe MSC8126 DSPs can be configured to boot with the default reset configuration word (RCW) or to boot over DSI, as shown in Table 24.
3.6.1 MSC8126 Standalone OperationTo power up the MSC8126 in its default configuration mode, the clock frequency, boot mode, and DSI mode should be configured as shown in Table 25. This mode is typically used during debug and brings up phases.
On test point 0 0 = LBC debug info driven on MSRCID signals
1 = DDR SDRAM controller debug info driven on MSRCID signals
Not used MSRCID0
On test point default to 1 0 = DDR Debug info is driven on ECC pins
1 = EEC pins function in their normal (default) mode
DDR Debug Configuration MSRCID0
Pulled high 1 PCI output hold configuration Not used PCI_GNT4
Table 24. Boot Options
Boot Mode CNFGS [S1.3] RSTCONF [S1.4] Comment
Default Boot
(Standalone operation)
0 [ON] 1 [OFF] Default RCW of 0x0 is written after 1024 cycles.
DSI Boot 1[OFF] 0 [ON] Reset configuration write through DSI
Table 25. DSP Standalone Mode
FeatureSettings
[OFF=1 ON=0]Comments
S1.1 ON MODCK1=0 Set for Clock Mode 0
MODCK2=0S1.2 ON
S1.3 ON CNFGS=0
RSTCONF = 1 [Default reset configuration word 0x0 written after 1024 cycles if HRCW from external host not received]
S1.4 OFF
S1.5 ON BM0
BM1
BM2 [BM[0:2]=001 Boot from External HostS1.6 ON
S1.7 OFF
S1.8 ON Set to Asynchronous DSI
Table 23. MPC8555 Configuration Settings (continued)
Switch Setting Description Comment Signal
Multi-Standard Baseband AMC Channel Card, Rev. 0
36 Freescale Semiconductor
General Board Configuration
The DSPs can be forced into debug mode through the SW5.1 switch, as shown in
3.6.2 Reset Configuration for System OperationIn system operation, the MSC8126 receives its reset configuration word and code from the MPC8555 through its DSI interface. The switch settings for this mode are described in Table 27.
The reset configuration word is described in Table 28.
Table 26. DSP in Debu Mode
FeatureSettings
[OFF=1 ON=0]Comments
SW5.1 ON EE0 = 1, DSPs enter debug mode
SW5.1 OFF EE0 = 0, standard operation
Table 27. DSI Configures
FeatureSettings
[OFF=1 ON=0]Comments
SW1.1 ON MODCK1=0 Set for Clock Mode 0
MODCK2=0SW1.2 ON
SW1.3 OFF CNFGS=1
RSTCONF=0 RCW write through DSISW1.4 ON
SW1.5 ON BM0
BM1
BM2 [BM[0:2]=001 Boot from External Host]SW1.6 ON
SW1.7 OFF
SW1.8 ON Set to Asynchronous DSI
Table 28. MSC8126 Hard Reset Configuration Word
Bit Name Value Description
0 EARB 0 Internal arbitration
1 EXMC 0 Internal memory controller
2 INT OUT 1 INT_OUT is selected
3 EBM 0 Single MSC8126 bus mode
4–5 BPS 00 Boot port size is 64 bits (not used)
6 SCDIS 0 SC140 core enabled
7 ISPS 0 Internal space is 64 bits
8 IRPC 1 Burst address line used
9 Reserved 0 0
Multi-Standard Baseband AMC Channel Card, Rev. 0
Freescale Semiconductor 37
Memory Maps
4 Memory MapsThis section details the memory map for the various devices. Note that because the memory maps are configurable through firmware they are subject to change. The listings in this section are the default options on the card.
4.1 MPC8555 Memory MapThe MPC8555 accesses DDR through its dedicated DDR controller. On the local bus, CS0 is used for flash memory access, and CS4 is used to access all devices on the DSI bus through the local bus controller. The MSB address bits are decoded to select the appropriate devices. The memory map, shown in Figure 19, details the flash memory locations of uboot, Linux, and the root file system. The root file system can be expected to grow as functionality is added to the board. The MPC8555 can view the full internal memory map of the MSC8126 through the DSI interface, as shown in Figure 22.
10–11 DPPC 00 Data parity pins act as IRQ lines
12 NMI OUT 1 NMI is serviced by SC140 core
13–15 ISB 000 Internal space base is 0xF0000000
16 Reserved 0 Reserved
17 BBD 0 Arbitration pins enabled (not used)
18 MMR 0 No masking on bus request lines
19 ETH. 0 GPIO Ethernet interface selected
20 TTPC. 1 Transfer type pin selection (HA7 selected)
21 CS5PC 1 BCTL1 selected
22-23 TCPC 00 TC function selected
24 LTLEND 0 Big endian
25 PPCLE 0 (not applicable)
26 Reserved 0
27 DLLDIS 1 No DLL bypass
100 MHz bus clock, 150 MHz CPM Clock, 300 MHz core clock
28-30 MODCK[3-5] 000 Clock configuration (default is Mode 0)
31 Reserved 0
Configuration Word = 0x20800C10
Table 28. MSC8126 Hard Reset Configuration Word (continued)
Bit Name Value Description
Multi-Standard Baseband AMC Channel Card, Rev. 0
38 Freescale Semiconductor
Memory Maps
Figure 19. MPC8555 Memory Map
Table 29. MPC8555 Local Bus Resources
Chip Select Device BR OR
CS0 Flash 0xFF001801 0xFF006FF7
CS4 DSI 0xC0001881 0xF0000106
0xFFFFFFFF
0xFF000000
0xC20000000xC1FFFFFF
0xC0000000
0x00000000
CS0
CS4
0xC0FFFFFF
SERDES FPGA
DDR(256MB)
ALGO FPGA
Flash
DSI (B)
DSI (A)
DDR Controller
Local Bus
0xFFFFFFFF
0xFFF80000
0xFF000000
0xFFF7FFFF
0xFFE000000xC7FFFFFF
0xFF800000
0xFF3F0000
Linux
µBoot
Rootfs
MPC8555
0xC9FFFFFF
0xC8000000
0xC7FFFFFF
0xC6000000
0xC3FFFFFF
Size canGrow
External System Bus(16MB)
System Registers
Core 3 – M1(224K)
Core 2 – M1(224K)
Core 1 – M1(224K)
Core 0 – M1(224K)
M2(476K)
IP Bus
0xC3FFFFFF
0xC3000000
0xC21BFFFF
0xC2180000
0xC21BFFFF
0xC2180000
0xC2177FFF
0xC2140000
0xC2137FFF
0xC2100000
0xC20F7FFF
0xC20C0000
0xC20B7FFF
0xC2080000
0xC2077000
0xC2000000
External System Bus(16MB)
System Registers
Core 3 – M1(224K)
Core 2 – M1(224K)
Core 1 – M1(224K)
Core 0 – M1(224K)
M2(476K)
IP Bus
0xC1FFFFFF
0xC1000000
0xC01BFFFF
0xC0180000
0xC01BFFFF
0xC0180000
0xC0177FFF
0xC0140000
0xC0137FFF
0xC0100000
0xC00F7FFF
0xC00C0000
0xC00B7FFF
0xC0080000
0xC0077000
0xC0000000
0xFFFFFFFF
0xFF000000
0xC20000000xC1FFFFFF
0xC0000000
0x00000000
CS0
CS4
0xC9FFFFFF
0xC8000000
0xC7FFFFFF
0xC6000000
0xC3FFFFFF
0xC0FFFFFF
SERDES FPGA
DDR
ALGO FPGA
Flash
DSI (B)
DSI (A)
MSC8126B MPC8555 MSC8126A
(256MB)
Multi-Standard Baseband AMC Channel Card, Rev. 0
Freescale Semiconductor 39
Mechanical Considerations
Figure 20. MSC8126 Memory Map from the MPC8555
4.1.1 MSC8126 Memory MapEach MSC8126 DSP uses five of the available chip selects as memory resources. Two are used for FPGA accesses and three for internal resources (L1 and L2 SRAM, IP bus peripherals, and DSP peripherals). The base and option register settings, which define this memory map, are detailed in Table 30 with chip selects 9–11 automatically set up as part of the ROM boot sequence.
Appendix AMechanical ConsiderationsThe AMC channel card is compliant with the AMC.0 (rev 1.0, Jan 05) specifications in terms of height and width for a full-height dual-width module. The only exception is the optional population of the Mictor connector on side 2, which violates height restrictions. Note that this connector is not needed for normal operation of the AMC. Furthermore, the board complies with the following standard dimensions (see Figure 21):
• PCB thickness:1.6 mm
• Component Side 2: 2.6 mm
• Component Side 1:Zone 1: 13.21 mm
• Zone 2: 10.85 mm
Figure 21. Component Height Areas
A.1 ComplianceThe channel card currently is compliant with the form factor and power considerations of the AMC.0 specification. Note the following restrictions:
Table 30. MpC8126 Memory Controller Resources
Chip Select Device BR OR
CS1 ALGO FPGA (Future Use) Application Specific
CS3 ALGO FPGA (Future Use) Application Specific
CS9 IP Peripherals 0x02181821 0xFFFC0008
CS10 DSP Peripherals 0x021E0021 0xFFFF0000
CS11 Internal SRAM 0x020000C1 0xFFE00000
10.85
1.602.60
13.21 Component Side 2
Component Side 1
All Dimensions in Millimeters
Zone 1Zone 2
Multi-Standard Baseband AMC Channel Card, Rev. 0
40 Freescale Semiconductor
Mechanical Considerations
• The module management controller (MMC) is not populated. Select the MMC bypass option on the carrier.
• The channel card cannot be hot swapped.
A.2 Certification• The SPTWIMAXCC1E AMC Channel Card is CE/UL certified.
Multi-Standard Baseband AMC Channel Card, Rev. 0
Freescale Semiconductor 41
Mechanical Considerations
Figure 22. Channel Card Assembly
REV
S/N
FREESCALE©2006
180.60
148.50
All Dimensions in Millimeters
Multi-Standard Baseband AMC Channel Card, Rev. 0
42 Freescale Semiconductor
Mechanical Considerations
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Multi-Standard Baseband AMC Channel Card, Rev. 0
Freescale Semiconductor 43
Mechanical Considerations
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Document Number: SPTWIMAXCCUGRev. 004/2007
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