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SoC/ASIC/SoC-FPGA/S-ASIC Design and Verification
Methodology
intelop
Intelop Corporation4800 Great America Pkwy.
Ste-201Santa Clara, CA. 95054
Ph: 408-496-0333, Fax: 408-496-0444www.intelop.com
Courtesy of Cadence design
intelopChallenges in Embedded Systems Design
intelopCritical Issues
intelopVerification Effort size
intelopOverview of Verification Methodologies
intelopSoftware Simulation
intelopSoftware Simulation
intelopHardware Acceleration
intelopEmulation
intelopOverview of Verification Methodologies
Formal Verification
intelopFormal Verification : equivalence Check
intelopFormal Verification : equivalence Check
intelopTheorem Proving
intelopFormal Verification : Model Check
intelopFormal Verification : Model Checking
intelopFormal Verification : Challenges
intelopSemi-Formal Verification : Assertion
intelopSemi-Formal Verification : Coverage
intelopSemi-Formal Verification : Coverage
intelopSemi-Formal Verification : Coverage
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Semi-Formal Verification
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Design Complexity
intelopLanguage Heritage for SoC Design
intelopSystemC in SoC Design
intelopSystemC in SoC Design
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Abstraction Levels of SystemC
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Vera (Synopsys)
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Vera (Synopsys)
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System Verilog
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System Verilog
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Key Components of System Verilog
intelopSystem Design Language Summary
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SoC Verification
intelopEmbedded Processor Cores in SoC
intelopModels of Embedded Processor
intelopModels of Embedded Processor
intelopModels of Embedded Processor
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Verification with Embedded Processor
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Verification with Embedded Processor
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Simultaneous SoC design Flow
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Tool utilized in HW-SW Co-Verification
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Tool utilized in Co-Simulation
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Conclusion
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Conclusion