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SoC FPGA TECHNOLOGY
HISTORY
• Digital Logic: (1950s-1960s)
3-input Function
ABC
A B C Y0 0 1 10 1 0 11 1 0 00 0 0 11 1 1 0
Black Box
Truth Table Digital Circuit
CMOS NAND Gate
Sum of ProductsProduct of Sums
HISTORY
• Regular structures for two-level logic: (1960s-70s)
• Consist of MUXs, De-MUXs, Decoders, FFs.
• Yield spaghetti-like maze!
• Each modification means a new PCB.
• Engineers got fed up!
HISTORY
• Programmable Logic Devices (PLDs): (1970s-80s)
• Chip makers addressed this problem by unconnected arrays of AND-OR gates.
• Fuses used to connect gates.
• Each fuse could be blown open or left close.
• Programming took place at manufacturers plants.
• Simple PLDs (SPLD) could only handle up to 10–20 logic equations.
• You had to break the design apart.
• Wiring was also required and it was a big no-no!
• Again engineers got fed up!
HISTORY
• Programmable Logic Devices (PLDs): (1970s-80s)
Programmed State
HISTORY
• Complex PLD (CPLD): (1980s)
• Contains a bunch of PLD blocks connected togetherby a global interconnect matrix.
• Each component is programmed individually.
HISTORY
• Application Specific Integrated Circuits (ASICs):
• Not available circa 1980s!
• Custom fabricated design from scratch.
• Large complex functions, millionsof gates customised for extremespeed and low power.
• Very expensive in smallquantities > $1 Million
• Very hard to design.
• NOT reprogrammable which meanshigh risks!
HISTORY
• Application Specific Integrated Circuits (ASICs):
• Any mistake means millions of dollars!
• June 1994, a flaw in Intel Pentium chipcauses a division error, discovered bysomeone called Dr Nicely.
• December 20th 1994, Intel apologizedand replaced all flawed Pentiums upon request.
• Intel reserved $420 million to cover costs!
• Full story:http://www.emery.com/1e/pentium.htm
PROBLEM
PLDs• Limited
Complexity• Thousands of
gates• Easy to design• Programmable
ASICs• Large Complex
Functions• Millions of gates• Hard to design• Not
reprogrammable
FPGA
FPGA DEFINITIONS
• Field Programmable Gate Arrays (FPGAs) are digital integrated circuits (ICs) that contain configurable (programmable) blocks of logic along with configurable interconnects between these blocks.
• The “field programmable” portion of the FPGA’s name refers to the fact that its programming takes place “in the field”.
WHY USE FPGA?
• The cost of an FPGA design is much lower than that of an ASIC.
• Implementing design changes is much easier in FPGA.
• Time to market for FPGAs is much faster.
• FPGAs make many small, innovative design companies viable.
• In 2003: 1500 to 4000 ASIC design starts and 5000 ASSP design starts, while around 450,000 FPGA design starts in the same year.
WHY USE FPGA?
• What distinguishes an FPGA from an ASIC is embodied in the name:
Field Gate ArrayProgrammable
FPGA ARCHITECTURE
• Programmable logic blocks calledLogic Elements (LEs).1000+ → 100,000+
• Massive fabric of programmableinterconnects.
• LEs described as islands in a “sea”of interconnects.
• Manufacturers refer to LE in different ways.Altera refers to it as Adaptive Logic Module (ALM).Xilinx refers to it as Configurable Logic Block (CLB).
ARCHITECTURE: LOGIC ELEMENTS
• 8-input divisible look-up table(LUT).
• Four dedicated registers to improvetiming closure.
• Full Adders and MUXs.
• 25% of ALMs can be used asdistributed memory using MLABs.
ALM for Altera Cyclone V
ARCHITECTURE: LUT
• LUT contains memory cellsto implement smalllogic functions.
• Each cell holds ‘0’ or ‘1’.
• Programmed with outputsof truth tables.
• Inputs select content of oneof the cells as output.
ARCHITECTURE: LAB AND ALM
• LABs are Logic Array Blocks
• Some FPGAs have two ALMs in eachLAB, while others have four.
• Fast programmable interconnectwithin the LAB.
• This is complemented by anequivalent hierarchy in theinterconnect.
LAB
ALM ALM
ALM ALM
Logic Cell
Logic Cell
Logic Cell
Logic Cell
Logic Cell
Logic Cell
Logic Cell
Logic Cell
Interconnect Speed
LABs
ALMs
Logic Cells
ALM connection details for Cyclone V
ARCHITECTURE: EMBEDDED MULTIPLIERS, ADDERS, ETC.
• Some functions may be slow inprogrammable logic.
• One common operation in DSPapplications,Multiply-and-Accumulate (MAC).
• Some FPGAs provide entire MACsas embedded functions.
ARCHITECTURE: MORE FEATURES
• Memory
• DSP Blocks
• PLLs
• Transceivers
• GPIO
• Hard IP
• That’s whatdifferentiates FPGAfrom CPLD.
DESIGNING WITH FPGA: HDL
• Can’t design FPGA by hand; way too much logic to manage and hard to make changes.
• Hardware Descriptions Languages (HDL) are used to specify functionality of logic at a high level.
• Most two popular languages are Verilog and VHDL (VHSIC Hardware Description Language).
D Q
Q
Verilog VHDL DFF
DESIGNING WITH FPGA: FLOW
• Validation:
• High level simulation to catch specification errors.
• Verify pin-outs and connections to other systemcomponents.
• RTL Synthesis:
• Process of compiling HDL code into logic gatesand flip-flops.
• Technology Mapping:
• Map the logic onto elements available in the implementationstechnology (LUTs).
• Placement and Routing:
• Assign logic blocks to functions.
• Make wiring connections.
Design System
Validation
RTL Synthesis
Place and Rout
Verification
DESIGNING WITH FPGA: FLOW
• Timing Analysis:
• Verify paths and determine delays.
• Check critical paths and improve their timing.
• Adjust placement of cells to improve timing closure.
• If the design does not fit it can be divided into multiple chips.
• Generate programming files which contain bits to be loaded in the device.
DESIGNING WITH FPGA: OPENCL
• What is OpenCL (Open Computing Language)?
• Open standard framework that enables developers to write programs that execute across heterogeneous systems including CPUs, GPUs, DSPs, and FPGAs.
• Benefits of OpenCL for FPGAs:
• Faster time-to-market: using the OpenCL C-based parallelprogramming language as opposed to low-level HDL.
• Quick design exploration: by working at higherlevel of abstraction.
• Easy design re-use: by retargeting existing OpenCLcode to current and future FPGAs.
• Faster design completion: by generating an FPGAimplementation in single step.
CONFIGURING FPGA
• Millions of SRAM cells hold LUTs and interconnect values.
• Volatile memory, loses configuration when power is turned off.
• Non-volatile memories are used to power up FPGAs with specific bit file.
SoC FPGA
• Formerly, designers used to implement what so called soft processors, which are microprocessors implemented in HDL.
• Popular IPs: NIOS II from Altera and MicroBlaze from Xilinx.
• Such architectures did not realize high performances, in addition to resources consumption and power consumption.
• They were also vendor-specific.
SoC FPGA
• Chip makers again for the rescue!
• SoC FPGAs integrate an ARM-based hardprocessor system (HPS) consisting ofprocessor, peripherals, and memoryinterfaces with the FPGA fabric usinga high bandwidth interconnect backbone.
• It combines the performance and powersavings of hard intellectual property (IP)with the flexibility of programmable logic.
SoC FPGA: ADVANTAGES
• Improved system performance: through a higher HPS to FPGA bandwidth interconnect, hardware acceleration, and increased memory performance.
• Increased reliability: through error correction code (ECC) and memory protection. Warm/Cold CPU reset that initiates without affecting or reprogramming FPGA.
• More flexibility: through hardware differentiation, system boot and configurations options, and multiple hardened memory controllers.
• Lower system cost: through single-chip integration, integrated PCIe controller and no power off sequencing.
SoC FPGA
• FPGA Vendors and Processors:
FPGA Vendor Hard Processor Soft Processor
Actel None Third-Party only
Altera ARM NIOS, NIOS II
Lattice None Third-Party only
Xilinx IBM PowerPC MicroBlaze, PicoBlaze
QuickLogic MIPS Third-Party only
SoC FPGA: HPS
Cyclone V SoC HPS Architecture
SoC FPGA: HPS FEATURES
• 925 MHz, dual-core ARM® Cortex™-A9 MPCore™ processor.
• Each processor core includes:
• 32 KB of L1 instruction cache, 32 KB of L1 data cache.
• Single- and double-precision floating-point unit and NEONTM media engine.
• CoreSightTM debug and trace technology.
• 512 KB of shared L2 cache.
• 64 KB of scratch RAM.
• Multiport SDRAM controller with support for DDR2, DDR3, and LPDDR2 and optional error correction code (ECC) support.
SoC FPGA: APPLICATIONS
• Just to name a few:
• Automotive Advanced Driver Assistance Systems (ADAS)
• Wireless Communications
• Military Radar
• Military Secure Communications
• The top four manufacturers of electronic imaging systems all use FPGAs
• This include CT, MRI, and Ultrasonic equipment
DEMONSTRATIONS
• Morse Transmitter
• 9-bit Microprocessor (Hello World)
• SoC HPS Apps (G-Sensor)
• DE1-SoC Ubuntu Desktop
REFERENCES
• www.altera.com
• www.Xilinx.com
• www.fpga4fun.com
• FPGAs Instant Access by Clive “Max” Maxfield
• Rapid Prototyping of Digital Systems, SOPC Edition by James O. Hamblen
