Asic and Fpga Design

8/12/2019 Asic and Fpga Design

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ASIC and FPGA Design Flow


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What is an ASIC?

What is an Integrated Circuit (IC)?ICs are basically chips

Silicon Wafers

Transistors, resistors, capacitors fabricated.

Can be either Digital or Analog.Microprocessors, Amplifier, Memory.

ASICs are Application Specific ICs

Designed for a special application

ASICs may be customized or mass produced

Digital to Audio Converter

Mpeg2 Decoder


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Hierarchy of IC Design


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ASIC Design Methodologies

Gate Level Design .Implement Logic at Gate Level

Schematic Editor (Mentor Graphics)

Hardware Description Language (Gates)

Logic Synthesis to Netlist

Implement in SiliconFull Custom Layout .

Design Logic at the Transistor Level

Hierarchical Design

Build Design from Bottom UpConnect Components Manually


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ASIC Design Methodologies

Behavioral DesignDescribe Algorithm Behavior (C like code)

Use Behavioral Synthesis tools

Result is RTL-HDL or Gate-level Netlist

Implement in Silicon

RTL Design

Describe Behavior

Synthesizable Subset of Hardware Description Language

Use RTL Synthesis tools for Gate-level Netlist

Implement in Silicon


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Hierarchy of ASIC Design


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ASIC Design Flow1. Design entry- Using a hardware description language ( HDL ) or schematic

entry.

2. Logic synthesis- Produces a netlist - logic cells and their connections.(Tools-Design Compiler/Design analyzer/Leonardo spectrum).

3. System partitioning- Divide a large system into ASIC-sized pieces.

4. Prelayout simulation- Check to see if the design functions correctly.

5. Floorplanning- Arrange the blocks of the netlist on the chip.

6. Placement- Decide the locations of cells in a block.

7.Routing- Make the connections between cells and blocks.


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8.Extraction- Determine the resistance and capacitance of the

interconnect.

9. Postlayout simulation- Check to see the design still workswith the added loads of the interconnect.

SoC Encounter tool for physical design.


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ASIC Design Flow


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Design Compiler

Takes an RTL hardware description and a

standard cell library as input.Produces optimized netlist as output.

Synthesis involves many steps:High-level RTL optimizations

Technology independent optimizations

Technology mapping to the standard cells


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Script files (.tcl)

Use Synopsys

commands to execute

synthesis

RTL Verilog (.v)

Synthesized Verilog

(.sv)

RTL VHDL (.vhd)Synthesized VHDL

(.svhd)

Design Compiler

Synopsys Database

(.db)

Binary format that

represents RTL, gates,

or internal libraries.

Reports (.rpt)

Logs (.log)

File types


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SoC Encounter (ASIC)

SoC Encounter provides an integrated solution

for an RTL-to-GDSII design flow.

Advanced RTL synthesisSilicon virtual prototyping

Mixed-signal support

Nanometer routing


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Large Part of ASIC Design is Verification and Testing

forCorrectness

Area

Timing

Power


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Verification

Originally HDLs designed for verification

Designs written in HDL and translated manually toschematics

Mentor Design Architect, Altera Quartus II

RTL Synthesis Tool replaces this step

Test Benches still used for verificationTest bench written in behavioral HDL

RTL Design Simulated with test bench

Determines correctness of design intent

Several other factors not consideredTiming, manufacturing process, power


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Formal Verification

Verification through simulation is problematic

Long simulation timesLikely does not test all possible permutations

Formal VerificationReduces time to do verification

Proves the structure of the two designs are logicallyequivalent

Can test original RTL against successive iterations of

RTL

Test RTL against synthesized netlist

Test pre vs. post layout netlist


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Timing Verification

One of the most important aspects of ASIC design

Analyze critical paths to verify that they meet timing

constraintsCan be done pre or post layout

Pre-layout uses wire load models to estimate delays

Post-layout back annotates actual wire delays

extracted from layout tools.


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Design for Test

Design for test (DFT) adds logic to the design to verify

the function of the chip.Built in self test (BIST) is synthesizable logic added to

the chip

Some EDA tools generate this logic automatically

Generates logic vectors to test the memory or logic of

the hardware

Boundary Scan (JTAG)

For testing board connections

Scan Insertion

Multiplexed FFs, turns into shift style register, applying

logic vectors.


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Alternate Hardware Implementation

Field Programmable Gate Arrays (FPGA)Hardware-like Speeds (10-100x slower)

Software-like Programmability (10-100x harder)

Design Flow similar, but easier than ASIC flows

Design logic at the Gate-Level or higherASIC can go down to polysilicon level

Logic is traditionally mapped to LUTs

Routing is mapped to pre-existing lines and switches


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Field Programmable Gate Arrays

Originally Designed as Reprogrammable Hardware

solution

Can be retargeted in the field

Early devices, extremely small and slow

1000 gates? < 20 MHz

Now billed as ASIC replacement

>> 1 Million Gates, > 500 MHz

Pay a fixed price per part

ASIC Fabrication Start-up cost becoming prohibitive

FPGAs also used for testing ASICs before fabrication


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FPGA Design Flow


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Design Flow

Design EntryVHDL/Verilog

Schematic

Synthesis

FPGA- Synplify ProASIC- Design Compiler/Design Analyzer

Place & Route

FPGA- Xilinix ISEASIC- SoC Encounter

SimulateModelSim


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Synplify Pro (FPGA)

Synthesizes the HDL code

Provides optimized netlist for the target FPGA

technology

Does synthesis in two steps:Compile-

syntax check

creates technology independent optimized netlist

Technology Map-based on the timing constraints specified by the

user, optimizes the netlist generated by the compiler

to the technology


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Xilinx ISE (FPGA)

Design Implementation:

Translate- merges the incoming netlists and constraints

into a Xilinx design file (.ngd file)

Map- maps the design into the available resources(CLBs and IOBs) on the target device (.ncd file).

Place and Route- places and routes the

design to the timing constraints.


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ModelSim

Provides a comprehensive simulation anddebug environment for ASIC and FPGA designs.

Can be used for functional and timing

simulation of the designs

Documents

Asic and Fpga Design