Slides Parte2 Rev2010

8/9/2019 Slides Parte2 Rev2010

1/71

Joo Goes (DEE) - 2010

Design of CMOS Amplifiers

December, 2008 (revised, Jan. 2010)


2/71


Contents:

Basic amplifier topologies

Current-mirrors

Basic cascode topologies and differential-pair

Single-stage transconductance amplifiers

Two-stage Miller-compensated amplifiers

Advanced two-stage amplifier topologies


3/71


Basic Amplifier Topologies


4/71


Basic Amplifier Topologies(common-source amplifier)

Vdd

vin

vout

M1

M2MB

I

Gain stage with high input impedance

( )

21

1

211

gdsgds

gm

rdsrdsgmAv

+

=

=

For low frequencies:


5/71


Vdd

vin

vout

M1

M2MB

I

( )( )

2121'

210

'10

1010

1

gdgddbdbLL

Lgd

gd

CCCCCC

rdsrdsR

sCCR

sCRgmRsAv

++++=

=

++

+=

For high-frequencies we have:

The output impedance is given by:210 rdsrdsR

Basic Amplifier Topologies(common-source amplifier)


6/71


Voltage buffer; DC level shifter;

11121

1 +++

=gmgmbgdsgds

gmAv

In low-frequencies and consideringbody effect:

Vdd

MB

M1

M2

vin

vout

I

Basic Amplifier Topologies(common-drain amplifier or source-follower)


7/71


For high-frequencies:

11121

0

11

gmgmgmbgdsgdsR

+++=

The zero has negative real part!!Stability problems may arise.

The output impedance is given by:

Vdd

MB

M1

M2

vin

vout

I

( )( ) ( )

1221'

'11211

11

gsgddbsbLL

Lgs

gs

CCCCCC

sCCgmbgdsgdsgm

sCgmsAv

++++=

+++++

+=



8/71


Since we have

For the emitter-follower:

For the source-follower:

This means that, for the same current, the emitter-followerhas a 4 times lower impedance than the source-follower!(Assuming VDSsat= VGS -VTn= 200 mV).

TV

Icgm=:TJBs

10

1

gmR

( )ovd

D

V

Igm

=

2:MOSs



9/71


Low input-impedance Current-gain stage

+

+

1

2

1

21

1

11rdsrds

gmrin

gdsgds

gmAv

In low-frequencies:

Vdd

vbias

vout

M1

M2MB

I

vin

rin

Basic Amplifier Topologies(common-gate amplifier)


10/71


Basic Amplifier Topologies(Summary of single-transistor amplifier topologies)

Amplifier

configuration

Voltage gain,

AV

Input

impedance, Rin

Output

impedance, Rout

Common-source ( )outdsm rrg || High High

Common-gate ( )outdsm rrg || Low High

Common-drain

(source-follower)

1 High Low


11/71


Basic Amplifier Topologies(Enhanced Voltage Followers)

(a) (b) (c)

Enhanced Voltage Followers: (a) NMOS-type supper-source follower (SSF); (b)

NMOS-Flipped-voltage follower (FVF); (c) NMOS enhanced voltage follower with

current feedback.

Basically it employs, in a fully differential implementation, two NMOS ordinary source

followers (SFs) and negative feedback is applied from the drain of the NMOS devices

to the low-impedance nodes of the amplifier (sources of the NMOS). The current

sources force the input transistors (NMOS) to conduct a fixed bias current. Thus these

NMOS device operate as simple SFs and copy the input signal at their gates to the

output. The second devices (PMOS) act as a class-A amplifier in a closed-loop

configuration. Due to the feedback, the output impedance can be made very small.


12/71


Current-Mirrors


13/71


Improved current-mirrors(Basic current-mirror with degenerated-source)

Main goal: increase rout!

( )RSgmrdsrds

RSRSgmrdsrout

+

++=

22

2

22

1

1

At low-frequencies:

Vdd

M1 M2

Iout

rout

I

RS RS


14/71



Disadvantage: Output dynamic-range decreases!

(Vout> 2*Vdsat+VTn)

2

441 rdsgmrdsrout

For low-frequencies:

Vdd

M1 M2

I

M3 M4

Iout

rout

Improved current-mirrors(Wilson Current-mirror)


15/71


( )442

4424

1

1

gmrdsrds

rdsgmrdsrdsrout

++=

In low-frequencies:

Vdd

M1 M2

I

M3 M4

Iout

rout

Improved current-mirrors(Cascode Current-mirror)


Disadvantage: Output dynamic-range decreases!

(Vout> 2*Vdsat+VTn)


16/71


Improved Cascode-current-mirrors(Wide larger output dynamic-range)

M6

M7 M8

Vdd

MB

Vdd

Ibias= Iin/ k

IinIout

W / L

(n+1)2

*k

W / L

(n)2

W/LW/L

Improved dynamic-range

Vout > 2*Vdsat if n=1!

Systematic offset problemdue to an asymmetry in the mirror!

(VDS7 > VDS8, since the drain

impedances are different)!


17/71


Much better solution! Improved output dynamic-range

Vout > (n+1)*Vdsat!

M7 e M8 biased in the limit oftriode/saturation region and M7

and M5 act like a single diode.

M5 M6

M7 M8

Vdd

MB

Vdd

Ibias= Iin/ k

IinIout

W / L

(n+1) 2*k

W / L

(n)2

W / L

(n)2

W/LW/L

Improved Cascode-current-mirrors(Wide larger output dynamic-range)


18/71


[Hosticka, 1979, Bult, 1990,Sackinger, 1990].

Use an extra amplifier in afeedback loop to keep VDS8constant.

Vdd

M7 M8

I

M6

Iout

rout

-

+Vbias

( ) ( )Ardsrdsgmrout + 1866

Improved Cascode-current-mirrors(Gain-boosting techniques)


19/71


2nd. option:

Use regulated-cascode employing asingle transistor amplifier.

Vdd

M7 M8

I

M5 M6

Iout

rout

Vdd Vdd

Mx2 Mx1

Ibias Ibias

Improved Cascode-current-mirrors(Gain-boosting techniques)


20/71


Basic cascode Topologies

and differential-pair


21/71


Advanced amplifier topologies(telescopic-cascode amplifier)

Vbiasvoltage should obey to:

Vbias> Vdsat-M1 +VGS-M2= Vdsat-M1 ++ VTn+ Vdsat-M2

For maximum output dynamic-range:

Vbias= Vdsat-M1 + VTn+ Vdsat-M2

M2

M1vin

vout

CLVbias

Vdd

Ibias


22/71


It is basically a common-gate amplifier cascoded

with a common-source amplifier:

Rule: Output impedance, rout, for 2 devices, M1 andM2 in cascode configuration is given by: rds1multiplied by the gain of M2 (gm2.rds2)!

M2

M1vin

vout

CLVbias

Vdd

Ibias

( )( )

( )( ) ( )( )

( )Rougly!

2

22211

source-currentcascodeauseweifonly,2

22

212

2

2

2

2

=

rdsgm

routrdsgmrdsrdsgm

vsvout

vinvsAv

rdsgm

routrdsrdsgmrout

fonte

M

M

fonte

Advanced amplifier topologies(telescopic-cascode amplifier)


23/71


Similar circuit but with a PMOS cascodetransistor

(++) input and output common-mode levelscan be equal;

(--) Slower, because the is a PMOS devicein the signal path;

(--) Worse power dissipation since thereare 2 current branches;

M2M1

vin

vout

CL

Vbias

Vdd

Ibias1

Ibias2

Advanced amplifier topologies(folded-cascode amplifier)


24/71


The differential-pair

For low frequencies we have:

M1 M2V+ V-

ID1 ID2

Ibiasroutgm

vin

routvingmAv

vingmiiiout

gmgmgmvingm

gmgm

vini

DDd

dd

D

=

=

==

===

+

=

21

2112

2

1

1

1since,


25/71


Basic differential amplifier(with active loads)

At low-frequencies:

( )

42

1

421

gdsgds

gm

rdsrdsgmAv

+=

=

M1 M2

vin

Ibias

Vdd

M3 M4

vout

rout


26/71


Single-stage operational transconductanceamplifiers (OTAs)


27/71


Operational Amplifiers

V+

V-

+-

VoV+-V-

A(V+-V-)

I=0

I=0

ri

ro

-

+

v1

vo

v2

Z1

Z2

Z3

Z41

1

22

1

21

43

4:generalIn

vZ

Zv

Z

ZZ

ZZ

Zvo

+

+=

Ideally:

Open-Loop gain,A, infinite;

Input Impedance, ri,infinite and outputimpedance, ro, zero.


28/71


Operational Amplifiers

( Op-Amps )

For low finites open-loop gains, A, one must take into account the error

added by this parameter in order to define its specification.

In switched-capacitor (SC) circuits, since no resistors are used, the outputimpedance is purely capacitive. Therefore, a single-stage

transconductance operational amplifier (OTA) might be used.

OTAs such as the folded-cascode, telescopic-cascode or mirror-cascodecan be considered amplifiers with a dominant pole and, hence, thedynamic analysis is simple as well as its stability.


29/71


Operational Amplifiers(definitions)

DC Differential gain, Ad: Open-loop low-frequency gain measured when a

differential input signal is applied; Typically: Ad= 40 to 120 dB;

Common-mode gain, Ac: Open-loop low-frequency gain measured when acommon-mode input signal is applied; Typically: Ac= 20 to 40 dB;

Common-mode rejection ratio, CMRR: CMRR = Ad/Ac.Typically: CMRR= 40 to 80 dB;

Power-supply rejection ratio, PSRR: PSRR = Ad/Aps.

Typically: PSRR= 90 dB at DC and decreases when frequency increases;


30/71



Input offset voltage, Vos: Amount of voltage one has to apply at the inputsin order to reach zero voltage at the output;Typically Vos= 1 to 10 mV;

Output swing, OS: Maximum amplitude allowed at the outputs to get lowharmonic distortion;

Slew-rate, SR: (dvo/dt) max; Depends on the biasing currents and loads;Measured by appying an input step with reasonable amplitude;

Typically: SR= 10 to 1000 V/us;


31/71



Gain-Bandwidth Product, GBW: frequency at which the open-loop gain is0 dB;

Phase Margin, PM: Margin to 180 between the input and the output atthe unity-gain frequency. Usually it is desired PM > 60 to guaranteemonotonic response in unity-gain configuration;

Settling-time, ST: defined to 0.1% accuracy at unity-gain configuration;(related to the GBW).


32/71


33/71


Single-stage transconductance amplifier (OTAs)(Telescopic-cascode)

(++) High DC gain,

(++) Low current consumption(only a single current branch);

(--) small output swing(5 transistors in stack);

(--) Normally different input and output

DC common-mode levels

M1 M2v+ v-

M3 M4

M5 M6

M7 M8

M9VB1

VB2

VDD

vout

( )

2

2

11 rdsgm

A


34/71


Single-stage transconductance amplifier (OTAs)(Mirror-cascode)

(++) High DC gain,

(++) equal input and output common-modevoltages;

(++) Better output swing;

(--) Higher current consumption(2 current branches);

(--) Dynamic performance (speed) verydependent on the dynamic current mirror

M1 M2v+ v-

M9VB1

VDD

VB2

vout

M3 M4

M5 M6

M7 M8

M10 M11M12 M13

( )

2

2

11 rdsgmA


35/71


Single-stage transconductance amplifier (OTAs)(Folded-Cascode)

(++) High DC gain,

(++) equal input and output common-modevoltages

(++) Better output swing;

(--) Higher current consumption(2 current branches);

M1 M2

M9VB1

VDD

M10 M11VB2

vout

VB3M3 M4

M5 M6

M7 M8

I

I/2

I

I/2I/2

I

I/2

( )

2

2

11 rdsgm

A


36/71


37/71


Single-Stage OTAs(folded-cascode)

( )

( ) [ ][ ]

( )( )

( )

( )( )

( )sVFC

AISR

HzFC

SgmGBW

Cs

gmAv

rdsgmrdsrdsrdsgmrdsgmAv

Crdsgmrdsrdsrdsgmrdss

rdsgmrdsrdsrdsgmrdsgm

Crouts

routgm

sV

sV

Av

L

D

L

L

LLin

out

/10

2

)]()[())((

)]()[())((1

)]()[())((

1

64

1

1

441016681

44101668

4410166811

=

=

+

=+

==

:bygivenisSRThe

:bygivenisGBW

:sfrequenciehmedium/higAt

:frequencylowAt


38/71


Single-Stage OTAs(Mirror-Cascode with biasing circuitry)

M1 M2

M9VB1

VDD

M10 M11

vout

VB3M3M4

M5 M6

M7 M8

I/2

I

k*I/2 k*I/2

I/2VB3I/10

I/10 I/10I/10

MB1 MB3

MB5

MB4

MB7

AMPOP CASCODE ESPELHADO

I/10

MB6VB2

VB2

CIRCUITO DE POLARIZAO

M10a M11a

M3a M4a

MB2


39/71


( )

( ) { }

( )( )

( )

( )

( ) ( )sV

FC

AIK

SR

HzFC

SgmKGBW

GBW

Cs

gmKAv

KCrouts

routgmK

sV

sVAv

L

L

L

Lin

out

/102

:bydefinedisrate-Slew

2

:bygivenisgainunityin)(productbandwidth-Gain

:sfrequenciehighAt

4,3,2normally,1

6

1

1

1

=

=

+

==

Single-Stage OTAs(Mirror-Cascode)


40/71


Frequency response of single-stage OTAs(telescopic-cascode versus folded/cascode)

( )

( )

( )

!60havetoorderin,

:yielding,

:thateddemonstratbecanItpoles.dominant-nonthebydefinedalwaysis

ionconfiguratcascodeaintechnologygivenaformaximumThe

~2

.max

.max

4

3.max

2

22

,2

PMGBW

L

V

GBW

p

M

dsatpnp

=

=

Example: Vdsat= 0.25V; Lmin= 0.6 m; n = 0.06 m2/V.s; p = 0.02 m2/V.s; LM2= 1.2 m (to avoid short-channel effects).

GBWmx. = ?

(Answer. 620 MHz, telescopic-cascode and 206 MHz folded-cascode)


41/71


Single-stage OTAs(folded-cascode amplifier with gain-boosting)

Main OTA

SATn SATp

Biasingcircuitry


42/71


Single-Stage OTAs(Using MATCAD to design Single-Stage OTAs: #1)

Units

uA 10 3

mA:= um 10 6

m:= fF 10 15

farad:= q 1.6 10 19

coul:= pF 10 12

farad:=

Initial DataIB 1000 uA:= CL 24 pF:= VDD 1.2V:=

VDsat1 100 mV:= VDsat6 100 mV:= VDsat8 100 mV:= VDsat4 100 mV:= VDsat11 100mV:=

L1 0.5 um:= L4 0.5 um:= L6 0.5 um:= L8 0.5 um:= L11 0.5 um:=

Vbs1 100 mV:= Vbs11 100 mV:= Vbs4 100 mV:= Vbs6 100 mV:=

Technology Definitions

VTN

0.38 volt:= KN

500 uA volt 2

:=

KB 1.38 10 23

joule

K:=

VTP 0.33 volt:= KP 100 uA volt 2

:=

KB300 K

q 0.026 V=

CGSD0 0.30 fF

um:= overlap capacitance

CGOX 12.3fF

um2

:= gate capacitance per unity area

Sd_s 0.4 um:= drain/source minimumdrawing area

CJN 0.722 fF

um2

:= CJP 0.953 fF

um2

:= diode capacitance per unity area

PBN 0.62 volt:= PBP 0.684 volt:= Junction potential

MJN 0.264:= MJP 0.295:= Adjust coeficient

CJSWN 0.0993fF

um:= CJSWP 0.105

fF

um:= Lateral capacitance per perimeter unit

MJSWN 0.105:= MJSWP 0.135:= Ajusting coeficient


43/71


Single-Stage OTAs(Using MATCAD to design Single-Stage OTAs: #2)

Transistor's Equations

gm IDVDsat,( ) if VDsat KB300 K

q 2

=

=

0dt

d:aslongasslimitation,,Rate"-Slew"nobewillThere

.7001.0ln

:needwe0.1%,ansmaller therrorsettlingaFor

.1

:bygiventhenis,response,-stepthe

OTAFor thecircuit.theofconstant-timetherepresentswhere

:likeresponse-stepahaveion weapproximatpole-singleaIn


48/71


-

++-

Cf

Ci

CpCload

VoutVin

Any SC circuit in a given phase can always be representedin the form:

Single-Stage OTAs(Exponential Linear Settling)


49/71


( )

( ) ( )

( )

( ) ( )( ) ( )

uc

uu

udBc

p

f

A

wsAsA

sAsAsA

CpCiCloadCL

CfCpCi

Cf

CfsCpCis

CpCis

==

===

+

=+

=

++=

++

=

++

+=

11

pole.loop-closedtheoffrequency

frequency,gain-unitytheiswhere

1

where,1

feedbackparallel-(series

11

1

:asfactorfeedbackthedefinecanweoperationSCtheofphaseeachIn

c

0

3

1

0

Single-Stage OTAs

(Exponential Linear Settling)


50/71


Advantages: better substrate-noise rejection; better PSRR;

better output swing (dynamic range is improved by 2) better robustness to charge-injection.

Drawbacks: Passives are duplicated and there is a need o a CMFB circuit

-

+

v1vo

Z1

Z2

-

+

v1+ vo+Z1

Z2

v1- vo-Z1

Z2

+-

single-ended fully-differential

Single-Stage OTAs(Fully-differential Realizations)


51/71


52/71


Common-Mode feedback circuits (CMFB)

1 Continuous-time version:

VddVdd Vdd

Ibias

Vref = Vdd/2

Vcontrol

20 k 20 k

1.5 pF 1.5 pF

Vout+ Vout-



53/71


1

1

1 2

2

2

Cs Cc

Cs Cc

Vcontrol

Vref = Vdd/2

Vref = Vdd/2

Vout+

Vout-

Vdd

Vbias

Common-Mode feedback circuits (CMFB)

2 SC version:



54/71


Two-stage Miller-Compensated Amplifiers


55/71


Two-Stage Amplifiers(Basic Topology)

-

+Vin A1 -A2 1 Vout

Cc

Andar diferencial

de entrada

2 andar de ganho

(fonte-comum)

buffer de sada

(Classe A, B ou AB)

T St A lifi


56/71


( )( )76

42

1

72

2,12,11

21

rdsrdsgmA

rdsrdsgmroutgmA

AAA

V

V

VVV

=

==

=

M5

M1 M2

M3 M4

Cc

M7

M6

Vin-Vin+

Vout

Vbias

1Rc

v1

Two-Stage Amplifiers

(DC gain)

Two Stage Amplifiers


57/71


( )

( )

( ) ( )

( )

Cc

I

Cc

I

Cc

I

dt

voutdSR

CcgmwwjAwGBW

Ccs

gm

ACcs

gmA

vin

voutsA

ACcsCeqsZout

CeqsrdsrdsZout

Zoutgmvin

vA

ACcCeq

DDCc

uuVu

V

VV

V

V

V

2,15.max

.max

2,1

2,1

2

2,1

2

2

2,11

2

2

10dBa

.11

:freqs.hmedium/higfor,1

42

1

1991]SedraTheorem,[Miller1

:isecapacitancequivalentresultingthev1,nodeIn

====

===

=

=

=

==

+=


(Medium/High frequencies)



58/71


M5

M1 M2

M3 M4

Cc

M7

M6

Vin-Vin+

Vout

Vbias

Rc

v1

1 Polo

2 Polo

If the 2 poles are close to each othera compensation capacitor is required

(Cc);

The Miller compensation techniqueconsists in adding Cc(assuming Rc= 0)in order to make Pole-splitting;

The Miller capacitance, Cc, moves thefirst pole to lower frequencies;

The series-shunt feedback moves the

second pole to higher frequencies.


(Frequency response and Compensation)



59/71


gm1*vinR1 C1

Rc Cc

gm7*v1R2 C2

v1Vout

( )

( )

CLCgdCdbCdbC

CgsCdbCdbC

rdsrdsR

rdsrdsR

+++=

++=

=

=

6672

7421

762

241





60/71


( )

( )

( ) ( )( ) ( )[ ]( )2121211122211

1

21

01122

1

0111

11

:and1nodestoKVLappyingand0Assuming

2

7

7

71

7

1

CCCcCCRRsCcCRCcCRCcgmRRs

gmCcs

RgmRgmvin

voutA

vgmCcsvvoutCsRvout

vingmCcsvoutvCsR

v

voutvRc

V

++++++++

==

=++

+

=++

+

=





61/71


Cc

gmw

CCCcCC

gm

CcCCcCCC

Ccgm

CcRRgm

z

p

p

7

77

2

7

1

12211221

21

1

:partrealpositivewithzeroaandpoles2fact,inhas,circuitThe

=

++=

++





62/71


( ) ( )

Cc

gmRRgmgm

CcRRgm

fAGBW

CRC

gm

CR

Rgm

RgmCCcCCc

Vu

11

7

p1

7p2

p1

71

21221

1

dB0a

:thatmakesP1,pole,dominantThe

22

1

2

11

1

:inresulting,2

1e

1

1,2,1

:havewedesignsprcaticalIn

=

=

=

>>>>>





63/71


CcRcgm

Rc

CcRc

gmgmCCc

gmgm

Ccgm

Cgm

CcgmGBW

z

zp

=

>

>>

==


64/71


Better output swing

Always stable after proper compensation for CL< CLmx;

Very simple biasing circuit;

Lower power dissipation when feedback factors, ,,,,Are small;

Slower (50% of the speed is lost due to the compensation);

Requires Ccand Rcfor compensation. Rc can be madeusing a transistor;




65/71


Advanced Two-Stage Topologies

Two-stage cascode-compensated OTA (1)


66/71


Two stage cascode compensated OTA (1) VDD

M1

M2

M7

M6

VDDVDD

VSS

M5

M4

M8

VDD

VSS

Ccomp

VSS

VDD

VSS

VBp1 VBp1 VBp2

VBn

VBnc

vinpvinnvoutn voutp

na

nb

IcasIout

nc

M3

vcm

Icmfb

Mcp

VSS

VDD

VBpc

VBn

VREFPMc

+

2

cmfb

bias

II

f

Cas

m

I

f

Out

m

I

PBI PBI

f

Cas

m

I

f

CasBias

m

II

+

2

f

CasBias

m

II

+

2

1 2

1

2

12

12

Bias

Main OTA

SC CMFB

Folded-cascode first-stagefollowed by two common-source

second-stages;Cascoded-Miller compensation.

Two-stage hybrid-compensated OTA (2)


67/71


Two stage hybrid compensated OTA (2)

Bias

Main OTA

SC CMFBs

f

Cas

m

I

f

Out

m

I2

f

Bias

m

I

f

Out

m

I

PBI PBI

f

Cas

m

I

f

Cas

m

I

f

CasBias

m

II

+

2

1 2

1

2

1

2

1

2

1

2

1

2

Folded-cascode first-stagefollowed by fully-differentialcommon-source second-stage;Hybrid cascoded-Miller compensation.

Two-stage OTA with positive feedback (3)


68/71


Two stage OTA with positive feedback (3)

Main OTA

SC CMFBs

1

2

1

2

1

2

1

2

1

2

1

2

M7

M8

VDDVDD

VSS

M5

M4

M6

VDD

VSS

VDD

VB5

VB4vinpvinnvoutn voutp

nb

IBias

nc

M1VB5

M2

2IOut

M9

VSS

VB9

n1

n2

ICas

Ccomp/2

Ccomp/2

VCM2

VCM1

VDD

na M3

Folded-cascode first-stagefollowed by fully-differentialcommon-source second-stage;Hybrid cascoded-Millercompensation. Local positive-feedback applied to the NMOScascode devices of the firststage.

[Randall Geiger and others,ISCAS03, CICC03]

Design of multi-stage OTAs


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Design of multi stage OTAs(How to extract the equations for the Optimizer? Step #1)

Step #1: Derive the small-signal model of half-circuit making a minimumof simplifications;

Basic 3rd. Orderexample



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Design of multi stage OTAs(How to extract the equations for the Optimizer? Step #2)

Step #2: Separate all nodesusing the Y-parameterstechnique



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es g o u t stage O s(How to extract the equations for the Optimizer? Steps #3 to #5)

Step #3: Find node equations (voltages, va, vb, vc=vo, etc and current);

Step #4: Solve, collect, simplify with using a symbolic solver and

get the open-loop transfer function (vo/vin);

Step #5: Port the open-loop transfer function into the Optimizer

Documents

Slides Parte2 Rev2010