Silicon Strip R&D Activity in Korea

Introduction Sensor design and simulation Pre-results of 1st mask performance Status of 2nd mask design Summary

B.G. Cheon (Chonnam Nat’l Univ.)On behalf of Korean Silicon Working Group

Generic silicon sensor R&D since 2001 Silicon charge detector for CREAM balloon experiment Started working on silicon sensor R&D for Belle upgrade Looking for any application to other fields 7 institutions so far …

Korean silicon working group

Kyungpook National UniversityEwha Women’s UniversitySeoul National University

Korea UniversityYonsei University

Sungkyunkwan UniversityChonnam National University

Global design layout/parameter concepts can be referred to other presentations in this workshop.

Silicon tracker R&D for ILC

• Intermediate tracker - tracking efficiency - linking efficiency - matching efficiency - standalone tracker

• main tracker - momentum resolution - tracking efficiency

Double-sided silicon strip sensor type Three metal process Implanted strips in ohmic side are orthogonal t

o the strips in juction side Readout strips in junction side are parallel to th

e strips of ohmic side

DSSD sensor design

Metal 1 and metal 2 contact (VIA)Metal 1 and metal 2 contact (VIA)

n+ ohmic n+ ohmic sideside

p+ junction p+ junction sideside

11stst metal metal

22ndnd metal readout line metal readout line

n+ ohmic components: # : implanted n+ # : p-stop # : SiO2

# : Al for readout

p+ junction components: # : implanted p+ # : 1st metal # : SiO2

# : VIA # : 2nd metal

Simulation package : Silvaco TCAD ATHENA – process simulation ATLAS – device simulation

PIN diode simulation calibrates DSSD simulation Structure & mesh Implantation (Boron, Phosphorus) Electric potential & field IV & CV characteristics Response of injected photon into the DSSD

DSSD sensor simulation

Structure

N-type Si(100), 8.5k, 380m

Implantation

Annealing 900oC, N2, 90min at P+Annealing 900oC, N2, 140min at N+

N strip = Phosphorus P strip = BoronP stop = Boron

IV & CV

Leakage current (I-V) C-V 1/C2 -V

Photon injection into DSSDphoton : wavelength = 0.6m, intensity=100W/cm2

0V

Total current density e current density h+ current density

150V

Wafer layout (1st mask)Mask design package : Cadence (Solaris)

DSSD sensor parameters

ListDC – Type 

unitp+ side n+ side

Sensor size 55610 x 29460 (sawing line included) μm2

Wafer thickness 380 μm

Strip pitch interval 100 50 μm

Readout pitch interval 50 50 μm

# of implanted strips 512 512

# of readout strips 512 512

Strip pitch length 25600 51072 μm

Strip pitch width 9 9 μm

Readout pitch width 9 9 μm 

Test bench @ clean room

Sensor profiles

n+ implanted

n+ side

p-stop in atoll VIA in hourglassreadout pad in staggering

guard ring

p+ implanted readout strip

p+ side

P-side measurementProbe n bulk pad(ground) on n-side & p-guard ring () on p-side

Total leakage current/sensor

0 20 40 60 80 100 120

1E-8

1E-7

1E-6

Le

aka

ge

cu

rre

nt (

A)

Reverse bias voltage(V)

LOT4_1_T1 LOT4_4_T1 LOT4_4_T3

0 20 40 60 80 100 120 140 160

1.0x10-7

2.0x10-7

3.0x10-7

4.0x10-7

5.0x10-7

6.0x10-7

7.0x10-7

8.0x10-7

Leak

age

curr

ent(

A)

Reverse bias voltage(V)

Pside IV ( LOT4_1_T1_shield)

These aredisappearedafter insulatingwafer edges

Total capacitance/sensor

0 20 40 60 80 100 120 140 160 1802.00E-011

4.00E-011

6.00E-011

8.00E-011

1.00E-010

1.20E-010

Cap

acita

nce(

F)

Reverse bias voltage(V)

LOT4_1_TI_CV

0 20 40 60 80 100

0.00E+000

2.00E+020

4.00E+020

6.00E+020

Y A

xis

Titl

e

X Axis Title

A

Specification of 2nd mask design

N-side P-side

Sensors 512ch 50m pitch 512ch 100m pitch

2types

Test Patterns Miniature 16ch 50m pitch

32ch 50m pitch

64ch 50m pitch

16ch 100m pitch

32ch 100m pitch

64ch 100m pitch

Pixel Array n+ implantation 25m 5 5 array ☓50m 5 5 array ☓

100m 5 5 array ☓

PIN Diode n+ implantation 1cm 1cm diode ☓

SSD R&D

(Single Strip Detector)

n+ implantation 100m pitch

2 types

SDD R&D

(Silicon Drift Detector)

25m sensor

25m sensor surrounded by p+ imp.

p+ implantation

Multi-purpose mask: sensors + various test patterns

N-side

512ch 50m pitch

1x1cm2 PIN diode

64ch 50m pitch

16ch 50m pitch

Rear-side of SSD Pixel Array

For SDD R&D

32ch 50m pitch

P-side512ch 100m pitch

w/o hourglass (sensor-1)

512ch 100m pitchw/ hourglass (sensor-2)

1cm PIN diode

For SDD R&D

Pixel array

16ch 100m pitch

16ch 100m pitch SSD

32ch 100m pitch

64ch 100m pitch

P-side (sensor-1)

Implant w/ hourglass

perpendicular to metal designed to reduce capacitance not applied to VIA region

512ch 100m pitch sensor

Test pattern: Miniature

S/N measurement of each pitch strip sensor after making wire bonding complete. Three types of sensors have been prepared.

16/32/64 channels

P-side :16ch 100m pitch Sensor

N-side :16ch 50m pitch sensor

Case of wire bonding

Test pattern: P-side SSD

Metal size is larger than p+ implantby reducing contact size.

Metal size is smaller than p+ implant by keeping contact size.

SiO2

p+

contact 1st Metal

SiO2VIA2nd Metal

P-side: two metal processes It is needed to make it compatible with other p+ implantation.

16ch 100m pitch sensor(55610 x 5560)

p+ implantation

Metal

Metal

p+ implantation

Test pattern: pixel array

Case of wire bonding in each diode

Case of readout pad in each diode

Pixel size : 25☓25, 50☓50, 100☓100 (m2) Each sensor array : 5☓5 matrix Readout pad option was added to make wire bonding easy during the measurement of S/N

Test pattern: SDD

50m☓50mn+ implant

100m☓100m metal

R&D pattern for Silicon Drift Detector Sensor size : 1cm ☓ 1cm (guard ring included) N-side : n+(sensor) & p+ implant except the sensor P-side : p+ implant in total

Summary

DSSD sensors fab-out (~20 wafers, 3 sensors/wafer) and IV & CV have been measured.

automatic probe station & wirebonder purchased and installed faster and more reliable measurement

2nd mask design including various test patterns is almost ready. Fabrication and measurement will be done within two months.

Silicon Drift Detector R&D has just been started.

Irradiation test for checking sensor rad-hardness is being planned.

Readout & DAQ design and production are in progress.

Backup sildes

CREAM(Cosmic Ray Energetics And Mass) balloon exp. To measure energy spectrum of each elements in 1012 ~1015 eVFirst mission of design, fab. and integration performed in Korea Sensor size=1.1cm2 ; S/N>4 ; Total 1000 channels

CREAM Silicon Charge Detector

Electric potential

Reverse bias ( 0V ~ -90V )

Electric field

P_strip region(P+)

N wafer region

P_strip’s doping concentration is higher than N wafer’s. So N_bulk region’s electric field is spread out widely, but the slope of P_strip region’s field is very steep. In depletion region, electric field is not zero.

Electron concentration

The higher reverse bias is, the larger depletion region is

Recombination rate

The higher reverse bias is, the larger depletion region is

N-side sensor

512ch 50m pitch sensor

p-stop

guard ring

pad

P-side (sensor-2)

Implant w/o hourglass

hard to implement hourglass in the mask process compare btw w/ and w/o hourglass

512ch 100m pitch sensor

SENS technology

Test pattern: SDD type-1

Silicon Drift Detector R&D 를 위한 pattern

guard ring 을 포함한 크기 : 1cm ☓ 1cm

N-side 에 센서를 두고 뒷면은 무공정

센서의 배열에 따라 세 종류가 있다 .

50m☓50mn+ implant

100m☓100m metal

Implantation

Annealing 900oC, N2, 90min at P+Annealing 900oC, N2, 140min at N+

N strip = Phosphorus

P stop = Boron

P strip = Boron