IC Mask Design Nmi Presentation 2009

© IC Mask Design 2009

“Yield and DFM in Layout at Nanometer Technologies”

NMI Conference, April 2nd 2009


Yield: Introduction

• Yield is a measure of how many functional devices are produced during the manufacturing process

• Traditionally foundries have managed yield

• On DSM/nanometer processes, yield needs to be considered during the design process

• DFM (Design For Manufacture)

• Quality of layout & design has direct impact on device yield


Yield: Introduction

• Traditional approach of addressing yield issues post layout becomes ineffective

Designs requiring full mask spins

Designs operating as expected


Design For Manufacture

• Recommended Design Rules

• For high yield, layout needs to be completed to obey recommended design rules

• New EDA DFM tools addressing yield

• New tools check the layout for DFM

• No longer a Pass/Fail

• Reports on potential yield with statistical reporting of errors

Design For Manufacture: Recommended Design Rules


• Aggressive layout = low yield = high performance• Relaxed layout = high yield = low performance


Aggressivelayout rules

Relaxedlayout rules

Source/Drain short

Source/Channel short

Sticky Contact


Extended Poly Endcap

• Requirement to increase standard poly endcap dimension

• On small gates, rounding can reduce channel width & cause device threshold variation

Increase poly endcap dimension

Roundingerror



Metal/Poly Overlap of Contact

• Minimum metal/poly overlap of contact can easily cause a “sticky” contact

• Contact is an open rather than short between two layers

• Increase conductor overlap of contact

• Never use single contacts/vias

Increased metal/polyoverlap of contact



Metal Overlap of VIA – End Of Line

• Minimum metal/metal overlap of contact can easily cause a “sticky” via

• via is an open rather than short between two layers

• Increase conductor overlap of contact

• Ensures low ohmic connection

• Never use single contacts/vias



Implement Wire Spreading

• Reduces critical area

• Reduces lateral capacitance

• Improves CMP yield

• Reduces potential of pattern short

Design For Manufacture: Layout For High Yield



Insert Dummies

• Insert dummy patterns in sparse areas of die

• Consider manual placement around matched structures

• Improves CMP

• Improves CD variation



Insert Dummy Structures

• For a high degree of matching and reduced CD variation, insert dummy structures around matched structures

• Improves CMP

• Improves CD variation

• Improves yield

MatchedDevicesDummy

Structures


Orient polysilicon uniformly

• Improves printability

• OPC and PSM

• Guarantees minimum CD variance

• Improves CMP yield

• Guideline at 130nm• Recommended at 90nm• Necessity at 65m


Non-uniformpolysilicon direction

Uniformpolysilicon direction


Lithography Friendly Layout

• Conforming to recommended design rules ensures a higher yield, but does not guarantee failure free silicon

• On smaller geometries, it is possible to use DFM and RET tools, prior to tapeout

• Examine the layout for possible lithography and yield defects

• Optimise prior to tapeout

Design For Manufacture: Lithography Aware/Friendly Layout


Lithography Friendly Layout



DFM Analysis


Original Layout Data DFM Analysis Result

Short

Short

Open


Design For Manufacture: VDSM Design Flow


Yield and DFM at Nanometer Technologies:

Summary

• Addressing yield in layout is an essential task on VDSM technologies

• Consistent strategy needed on what matters to address and how to address them

• It is less expensive and costs less time to address yield in abstract data rather than physical silicon

• Physical designers responsibility is to reduce risk in silicon at all times

• Ignore yield at your peril !!

Technology

IC Mask Design Nmi Presentation 2009