Project 1A: 4-to-1 Multiplexer using 8-bit Buses on inputsi266/spr12_hw10/5381.pdfAlternatively, we can create this circuit using eight 1-bit 4-to-1 line multiplexers. The resulting

Project 1A: 4-to-1 Multiplexer using 8-bit Buses on inputs

A 4-to-1 multiplexer (4-1 MUX) takes 4 inputs and 2 selectors (since 2^2=4). This 4-1 MUX will

use 8-bit buses for the 4 input lines, giving a total of 34 (= 4 x 8 + 2) input values, including the

selectors. The output will be an 8-bit bus that matches one of the four input buses. The purpose of

the 4-1 MUX is to select one of the four 8-bit inputs, making use of the 4 (=2^2) permutations of

the selectors to choose the appropriate output from the four inputs.

The 4-to-1 MUX with 8-bit buses is implemented similarly to the 1-bit 4-to-1 line MUX, except

that each of the four selector outputs is linked to 8 different outputs. For example, if the selectors

are set to (S1,S0)=(0,0), then the output will be an 8-bit bus equal to the input I0.

A snapshot of the circuit is included below (see Exhibit 1). Waveforms for the following tests

follow the circuit (see Exhibit 2).

Exhibit 1:

Testing:

1

I first check the selectors by altering the values for each of the four inputs to check that each is

selected properly.

S0 | S1 | I0 | I1 | I2 | I3

0 | 0 | 11111111 | 11110000 | 00001111 | 11001100

0 | 1 | 11111111 | 11110000 | 00001111 | 11001100

1 | 0 | 11111111 | 11110000 | 00001111 | 11001100

1 | 1 | 11111111 | 11110000 | 00001111 | 11001100

Or in decimal form:

S0 | S1 | I0 | I1 | I2 | I3

0 | 0 | 255 | 240 | 15 | 204

0 | 1 | 255 | 240 | 15 | 204

1 | 0 | 255 | 240 | 15 | 204

1 | 1 | 255 | 240 | 15 | 204

The expected and actual output for these scenarios is:

S0 | S1 | Expected | Actual

0 | 0 | 11111111 | 11111111

0 | 1 | 11110000 | 11110000

1 | 0 | 00001111 | 00001111

1 | 1 | 11001100 | 11001100

Or in decimal form:

S0 | S1 | Expected | Actual

0 | 0 | 255 | 255

0 | 1 | 240 | 240

1 | 0 | 15 | 15

1 | 1 | 204 | 204

I next check that all circuits are working by testing the following scenarios. The output in each case

should be 11111111. Since I know the selectors are working, this confirms that all individual input

wires are properly connected from the bus down to the output.

S0 | S1 | I0 | I1 | I2 | I3

0 | 0 | 11111111 | 11111111 | 11111111 | 11111111

0 | 1 | 11111111 | 11111111 | 11111111 | 11111111

1 | 0 | 11111111 | 11111111 | 11111111 | 11111111

1 | 1 | 11111111 | 11111111 | 11111111 | 11111111

2

Or in decimal form:

S0 | S1 | I0 | I1 | I2 | I3

0 | 0 | 255 | 255 | 255 | 255

0 | 1 | 255 | 255 | 255 | 255

1 | 0 | 255 | 255 | 255 | 255

1 | 1 | 255 | 255 | 255 | 255

Alternatively, we can create this circuit using eight 1-bit 4-to-1 line multiplexers. The resulting

circuit would be a somewhat simplified version of the circuit shown in Exhibit 1.

Exhibit 2

3

Project 1B: 8-bit Adder

An 8-bit adder adds two 8-bit inputs to produce the 8-bit sum of these two numbers. Note that the

maximal value for the sum of two unsigned 8-bit integers is 111111110 (= 11111111+11111111),

which is a 9-bit adder. Hence, when mapping the sum to an 8-bit output, it makes sense to output

the final carry term. If this term is not used then it can be ignored later on. Furthermore, when

adding 2s complement numbers, it is useful to know whether or not there is overflow. We can

determine this by comparing the final two carry terms. If these are equal, there is no overflow. If

they are unequal, there is.

The 8-bit adder can be constructed by first creating a 2-bit full adder and then stringing eight of

these full adders together. Each pair of bits can be added pairwise to the carry term from the

previous (previous=less significant) pair's carry term. For example, if we were adding the 2-bit

number 11 to the 2-bit number 10, we would first add the least significant bits to get the sum=1

(=1+0) and the carry term=0. Then we add the 2nd least significant bits to the previous carry term to

get a 1-bit sum of 0 (=1+1+0) and a carry of 1. We see again that limiting to 2-bits can cause us to

drop the final carry term. Addition of two 8-bit numbers is just a continuation of the process

outlined for two bits.

In each step (i.e., each pairwise addition of bits), we have 3 inputs and two outputs (the input carry

term for the least significant bits is 0). The 3 inputs include the nth bit from each 8-bit input and the

carry term from the sum of the (n-1)th bits. The outputs are the 1-bit sum of the three input bits and

the carry term. The possible combinations are described in the following truth table.

X | Y | Cn-1 | S | Cn |

0 | 0 | 0 | 0 | 0 |

0 | 0 | 1 | 1 | 0 |

0 | 1 | 0 | 1 | 0 |

0 | 1 | 1 | 0 | 1 |

1 | 0 | 0 | 1 | 0 |

1 | 0 | 1 | 0 | 1 |

1 | 1 | 0 | 0 | 1 |

1 | 1 | 1 | 1 | 1 |

From this, we can see that S is an odd function, which can be written as S=XOR[XOR(X, Y), Cn-1].

Cn = m3 + m5 + m6 + m7 = X'YCn-1 + XY'Cn-1 + XYCn-1' + XYCn-1= XY + (X+Y)Cn-1. This

computation is simplified using a K-map, which I do not show. However, the equation is easily

checked by substituting values from the complete truth table above (e.g., in the last 2 rows, X=Y=1,

which implies XY=1, which satisfies the above equation and matches the desired results).

Using these equations for S and C, I create and test a component that sums two input bits and an

input carry bit to produce a 1-bit sum and an output carry bit. See Exhibit 3 for the circuit and

Exhibit 4 for the waveform. Since the truth table is short, I compute the waveform for all 8 rows of

the truth table. Hence, the testing is exhaustive.

4

Exhibit 3

5

Exhibit 4

I then use 8 copies of this component to implement the eight 1-bit additions required for an 8-bit

addition. I note again that for the least significant bit, the carry input equals 0. Note that I include

the final carry term as a separate output, in addition to the 8-bit sum. I also output the XOR of the

final two carries in order to determine whether there is a 2s complement overflow (V=1 implies 2s

complement overflow). See Exhibit 5 for the circuit.

6

Exhibit 5

To test this circuit, I consider the following inputs assuming unsigned integers (see Exhibit 6 for

waveform). I choose certain base cases for specific reasons and others randomly. In addition to

this, I cycled through many different iterations of the two inputs, incrementing one of the inputs by

1 each time to verify that the sum was incremented by 1 as well (except when there was overflow).

V represents 2s complement overflow. Unsigned overflow is indicated by Carry=1.

X | Y | Expected Sum/Carry/V | Actual Reasoning

0 | 0 | 0/0/0 | 0/0/0

255 | 255 | 254/1/0 | 254/1/0 Tests carrying/overflow

128 | 128 | 0/1/1 | 0/1/1 Tests carrying/overflow

50 | 100 | 150/0/1 | 150/0/1 Tests symmetry

100 | 50 | 150/0/1 | 150/0/1 Tests symmetry

10 | 200 | 210/0/0 | 210/0/0 Random even sum

101 | 201 | 46/1/0 | 46/1/0 Random odd sum

31 | 20 | 51/0/0 | 51/0/0 Random odd/even sum

Note that overflow in unsigned addition occurs when adding 101 and 201 because the addition is

performed modulo 256:

101+201 = 302 (mod 256) = 46

If we instead interpret our numbers using 2's Complement signed numbers, then overflow is an

issue only when exactly one of the final two carry terms is 1. Note that when we reinterpret

unsigned 101 and 201 as 2's complement numbers we get 101 (=01100101) and -55 (=11001001).

When these two numbers are add, we get:

7

Carry 1 0 0 0 0 0 1 0

101 0 1 1 0 0 1 0 1

55 1 1 0 0 1 0 0 1

Sum 1 0 0 1 0 1 1 1 0

The final two carry terms (in bold italics) are both 1. Here, overflow is no issue, since when we

limit to the final 8 bits, we get 46 (=0010 1110), as required. In addition of 2's complement

numbers, there is overflow only when exactly one of the last two carry terms equals 1.

Exhibit 6

8

Project 2: 8-Bit ALU

The purpose of this project is to construct an 8-bit ALU which has the following inputs and outputs.

Inputs:

• Enable (1-bit) – enables circuit

• ALU_SEL (3-bit) – chooses action to be performed

• A (8-bit) – first operand

• B (8-bit) – second operand

• c_in (1-bit) – input bit used to obtain more operations

Outputs:

• M (8-bit) – result of operation performed

• mi7 (1-bit) – sign bit

• V (1-bit) - overflow

• c_out (1-bit) – carry out

The outputs are determined by one of 8 different actions performed on the inputs A, B, and c_in.

The action performed is to be determined by the input ALU_SEL. The chosen action will be output

only if the circuit is enabled (I.e., Enable=1).

In order to construct an 8-bit ALU, I first construct the eight separate components which perform

the eight computations peformed by the ALU:

• A OR B [ALU_SEL=000]

• NOT(A) [ALU_SEL=001]

• A + NOT(B) + c_in [ALU_SEL=010]

• A+B+c_in [ALU_SEL=011]

• A XOR B [ALU_SEL=100]

• A AND B [ALU_SEL=101]

• A – 1 + c_in [ALU_SEL=110]

• A + c_in [ALU_SEL=111]

There are several alternatives to creating the ALU (e.g., implementing all eight of these components

directly in a single circuit, implementing the eight components independently without using parts

individual components to build the others, etc.). Creating these components individually will

simplify the circuit. Furthermore, some of these components can be used to build others, thus

simplifying the circuit. E.g., A+B+c_in can be built from A + NOT(B) + c_in by adding a not gate.

In order to improve readability, I chose to use subcomponents to build others. I constructed the

components consecutively (as listed above) and only used another component if it had already been

built (i.e., if it comes earlier in the list above). Hence, I used the A + NOT(B) + c_in circuit to

build the A + B + c_in because they occured in the order. It is arguably more intuitive to reverse

this build order, but I chose not to do this so that this report could more easily follow the

specifications of the circuit required.

After the construction of these 8-bit components, several other components will be required. These

will be discussed and tested below as they are needed. They include a 1-bit 8-1 MUX, an 8-bit 8-1

MUX, a 1-8 bit duplicator, and an 8-bit OR gate with eight inputs. A list of component required to

build each subcomponent is listed as part of the description of each subcomponent. A final list of

9

components and subcomponents required for the ALU circuit is listed below in the discussion of the

ALU.

(1) A OR B

Inputs:

• A – 8-bit operand

• B – 8-bit operand

Components

• 2 1-8 bit expanders

• 8 2-bit OR gates

• 1 8-1 bit merger

Outputs:

• A OR B – 8 bit output

The OR operation applied to two 8-bit inputs creates an 8-bit output where each bit is the pairwise

2-bit OR operation applied to the corresponding bits from the two inputs. This circuit (shown

below in Exhibit 7) merely extracts the individual bits from the two inputs, combines them into 8-

separate OR gates and merges the eight results into a single 8-bit bus. Test cases should include

cases such that for each bit, I test (1) 1 OR 1 maps to 1, (2) 0 OR 1 maps to 1, (3) 1 OR 0 maps to

1, (4) 0 OR 0 maps to 0. Hence I choose1:

• 11111111 OR 00000000 = 11111111

• 11111111 OR 11111111 = 11111111

• 00000000 OR 11111111 = 11111111

• 00000000 OR 00000000 = 00000000

• 10101010 OR 01010101 = 11111111

These results are shown in the following waveform (see Exhibit 8).

1 Note that 11111111, 00000000, 10101010, and 01010101 in binary represent 255, 0, 170, and 85 in base 10.

10

Exhibit 7

Exhibit 8

11

(2) NOT(A)

Inputs:


Components

• one 1-8 bit expanders

• 8 inverters

• one 8-1 bit merger

Outputs:

• NOT(A) – 8 bit output

NOT(A) takes the complement of the individual bits in the 8-bit bus input A, and merges the

complements into a single 8-bit bus output. See Exhibit 9 for the circuit.

Test cases must be chosen to ensure that each individual bit is properly complemented and that the

bits are merged in the appropriate order. See Exhibit 10 for the waveform showing the following

test cases:

• NOT(11111111) = 00000000

• NOT(10101010) = 01010101

• NOT(00000000) = 11111111

12

Exhibit 9

Exhibit 10

13

(3) A + NOT(B) + c_in

Inputs:



• c_in – 1 bit operand

Components

• one 1-8 bit expanders

• one 8-bit NOT gate from part(2)

• two 8-bit adders see Part 1B

• one ground input

• two 2-bit OR gates

• one 8-1 bit merger

Outputs:

• A + NOT(B) + c_in – 8 bit output

• c_out – 1-bit carry term

• V – 1-bit overflow term

This sum requires adding two 8-bit numbers and a 1-bit number. I will do this in three stages. First,

I will add A and NOT(B) using the 8-bit adder from Part 1B. Then I will convert the one bit

number c_in to an 8-bit number by merging on seven extra 0-bits. Finally, I will add the 8-bit

version of c_in to the previous 8-bit sum. See the circuit in Exhibit 11 below.

The carry and overflow outputs require some additional analysis. Note that we are now adding

three 8-bit numbers instead of two. Hence, our standard test to determine overflow must be

checked (recall that the test when adding two 8-bit numbers is to check equality of the final two

carry terms). Let us first consider what the sum of our 8-bit numbers would be if we had as many

bits as we needed. A+B results in the following:

Carry C8 C7 C6 C5 C4 C3 C2 C1 C0

A A7 A6 A5 A4 A3 A2 A1 A0

B B7 B6 B5 B4 B3 B2 B1 B0

A+B D8 D7 D6 D5 D4 D3 D2 D1 D0

Next, we add 00000001:

Carry X9 X8 X7 X6 X5 X4 X3 X2 X1 X0

1 0 0 0 0 0 0 0 0 1

A+B D8 D7 D6 D5 D4 D3 D2 D1 D0

A+B+1 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0

Note that F9 is necessarily 0. We can see this by observing that the largest possible unsigned value

of A and B is 1111 1111. Hence, the largest possible value for A + B is:

1111 1111 + 1111 1111 = 1 1111 1110

But 1 1111 1110 + 0000 0001 = 1 1111 1111. Hence, it is not possible for F9 to equal 1 when

adding 8-bit numbers. Observe that F8 = XOR(D8, X8) since we cannot have X8=D8=1

(otherwise, it would be possible to have F9=1). Since we know F9=9, we can conclude that F8 can

also be computed using an OR gate (we will never have D8=X8=1).

I also need to know when overflow is an issue. Note that I am applying the 8-bit adder twice, so I

14

use an OR gate to check both of these conditions to determine overflow. If this condition is true,

then overflow occured in at least one of my calculations.

Exhibit 11:

Testing of the 8-bit sum and of NOT was done previously. Hence, testing must check that the three

steps above are correctly implemented.

• A>0, NOT(B)>0, c_in=0 will check that the 8-bit sum is properly implemented.

• A=0, NOT(B)=0, c_in=1 will check that the 1-bit sum is properly implemented.

• A>0, NOT(B)>0, c_in=1 will offer further verification that all pieces of the sum are correct.

I consider the following test cases. See Exhibit 12 for the waveform.

• A=10101010, B=10101010, c_in=0 should produce 11111111 / 0 / 0



15

Exhibit 12:

(4) A + B + c_in

Inputs:




Components

• one 8-bit NOT gate from part (2)

• one A + NOT(B) + c_in gate from part (3)

Outputs:

• A + B + c_in – 8 bit output



This circuit, like (3) takes two 8-bit inputs and a 1-bit input and produces an 8-bit sum, as well as

single bit outputs for overflow and the final carry term. This result can be easily obtained by

feeding NOT(B) into the circuit in (3). I reuse (3) rather than building the circuit from scratch

because most of the work has already been completed and tested in part (3). I use the same cases as

in (3) to test the circuit, but with B inverted so that the output is remains the same. See Exhibit 13

for the circuit and Exhibit 14 for the waveform.

16

Exhibit 13

17

Test cases (as in (3) but with B inverted):

• A=10101010, B=01010101, c_in=0 should produce 11111111



Exhibit 14

18

(5) A XOR B

Inputs:



Components


• 8 2-bit XOR gates


Outputs:

• A XOR B – 8 bit output

This circuit takes two 8-bit inputs and outputs a single 8-bit bus. The values of the output bus are

the merged results of eight 2-bit XOR gates applied pairwise to the eight pairs of bits in the inputs A

and B. See exhibit 15 for the circuit. Testing must guarantee that the pairwise mappings are

correct. I.e., 0 XOR 1 = 1, 0 XOR 0 = 0, 1 XOR 0 = 1, and 1 XOR 1 = 0. The following cases are

considered, with waveform results shown below in Exhibit 16:

• 10101010 XOR 01010101 = 11111111

• 11110000 XOR 11110000 = 00000000

• 11111111 XOR 00000000 = 11111111

Exhibit 15

19

Exhibit 16

(6) A AND B

Inputs:



Components


• 8 2-bit AND gates


Outputs:

• A AND B – 8 bit output

An 8-bit AND gate performs the AND operation on each of the corresponding pairs of bits in two 8-

bit inputs. This circuit takes two 8-bit inputs and outputs a single 8-bit bus. This component is

created by expanding the eight bits of the two 8-bit input buses, sending the individual

corresponding bits through eight different 2-bit AND gates, and merging the results into a single 8-

bit bus. See Exhibit 17 for the circuit.

20

Exhibit 17

In order to test this circuit, it is necessary to be sure the AND operation works properly in each of

the eight output bits. Recall that AND(0,0)=AND(0,1)=AND(1,0)=1 and AND(1,1)=1. I consider

the following test cases. See Exhibit 18 for the waveform demonstrating these results, in order.

• 11111111 AND 00000000 = 00000000

• 10101010 AND 01010101 = 00000000

• 10101010 AND 10101010 = 10101010

• 01010101 AND 01010101 = 01010101

21

Exhibit 18

(7) A – 1 + c_in

Inputs:



Components

• one A + B + c_in gate from part (4)

• one VCC input

• one 8-bit merger

Outputs:

• A – 1 + c_in – 8 bit output



This circuit will take in two inputs, an 8-bit bus and a 1-bit input. This circuit could be constructed

similarly to the sums created above, but this is inefficient. Instead, to simplify the overall circuit, I

observe that subtracting 00000001 is the same as adding 11111111. With this information, I can

then use the previous component [A+B+c_in] where B is fixed at 11111111. The resulting circuit is

shown below in Exhibit 19.

22

Exhibit 19

I test several cases, including an instance where there is no overflow and and instances where

overflow is caused by either -1 or c_in. Test cases are in the form A – 1 + c_in = Sum / Cout / V.

See Exhibit 20 for the waveforms.

• 10101010 – 1 + 0 = 10101001 / 1 / 0

• 10000000 – 1 + 0 = 01111111 / 1 / 1

• 01111111 – 1 + 1 = 01111111 / 1 / 0

23

Exhibit 20

(8) A + c_in

Inputs:



Components

• one 8-bit adder from Part 1B



Outputs:

• A + c_in – 8 bit output



This circuit will take one 8-bit bus and one single bit input. It will output an 8-bit sum, a single bit

carry term, and a 1-bit output that indicates overflow for 2s complement arithmetic. This circuit

could be implemented using one of the previous sums (e.g., A+B+c_in where B=00000000), but I

choose to implement it by converting c_in to an 8-bit bus (by appending 0s to the front) and then

using the 8-bit adder from part 1B. I choose this method because it is less confusing than

implementing a special case of one of the previous circuits from Part 2. See Exhibit 21 for the

circuit.

24

Exhibit 21

Testing must include cases that check that adding 0 produces A and that adding 1 handles carrying

and overflow properly. See Exhibit 22 for the waveforms. Test cases are in the form A + c_in =

Sum / c_out / V, where V is the overflow indicator.

• 10101010 + 0 = 10101010 / 0 / 0

• 10101010 + 1 = 10101011 / 0 / 0

• 01111111 + 1 = 10000000 / 0 / 1

• 11111111 + 1 = 00000000 / 1 / 0

25

Exhibit 22

Combining the Components

The ALU_SEL input will be used to determine which of the 8 subcomponents I will use to compute

the outputs (M, m7, V, and c_out). Note that I did not include V and c_out in all the

subcomponents. In the instances where I omitted them, V and c_out are necessarily 0. E.g.,

NOT(A) will not require a carry or overflow term because all it does is flip 0s and 1s.

Note that there are four required outputs. M7 is simply the last bit of M, which I can simply extract

at the end of the circuit. Hence, we will need only 3 8-1 MUXes. An 8-bit 8-1 MUX for M, an 1-

bit 8-1 MUX for c_out, and a 1-bit 8-1 MUX for V. The 3 ALU_SEL input bits provide the

selectors for each 8-1 MUX.

I now present the circuits and testing for the 1-bit and 8-bit MUXes and for the final components

required to combine the outputs from the eight action components.

26

1-bit 8-1 MUX

Inputs:

• three 1-bit selector inputs

• eight 1-bit inputs

Components

• eight 3-input 1-bit AND gates

• eight 2 input 1-bit AND gates

• two 4-input 1-bit OR gates

• one 2-input 1-bit OR gate

Outputs:

• one 8-bit output

An 8-1 MUX has 8 inputs and 3 1-bit selectors. For a 1-bit MUX, the inputs are a single bit and the

output is the one bit that is chosen by the selectors. E.g., If the selectors equal 111, then input 7 (of

inputs 0 to 7) is chosen since 7 is the decimal equivalent of 111. There are alternative methods to

create the 8-1 MUX, e.g., combining a 2-4 decoder with another input to create a 3-8 bit decoder.

In order to decrease the number of components to test, I instead construct the 8-1 MUX directly

from the three selectors and eight inputs. The three selectors are decoded into the eight possible

outputs by feeding them through eight 3-input 1-bit AND gates. Each of the results is ANDed with

a different input. These are then fed through a series of 4-input and 2-input OR gates (these two

stages are necessary due to the unavailability of an 8-input 1-bit OR gate, which I do not create

because I will not be needing it again).

27

Exhibit 23A

28

I test that the appropriate bit is returned from 10101010 as I cycle through the 8 selector

possibilities. The results should return 1, 0, 1, 0, 1, 0, 1, and 0 for selectors 000 to 111. This testing

is not exhaustive, but is justified because I use mostly the same circuit to create the 8-bit 8-1 MUX

which is easier to test due to the ability of setting each of the eight inputs to different values. See

below for the testing of the 8-bit 8-1 MUX.

Exhibit 23B

29

8-bit 8-1 MUX

Inputs:

• three 1-bit selector inputs

• eight 8-bit inputs

Components

• eight 3-input 1-bit AND gates

• eight bit duplicators (see below for schematics)

• eight 8-bit AND gates from part (6) above

• one 8-input 8-bit OR gate (see below for schematics)

Outputs:


The structure of the 8-bit 8-1 MUX is parallel to the structure of the 1-bit 8-1 MUX. The key

difference is that the inputs are 8-bit, which means that the selector must be duplicated (using the

Bit duplicator designed and tested below) and 8-bit ANDed with the eight inputs using the A AND

B circuit designed above. See exhibit 24A for the circuit.

Exhibit 24A

30

I test the circuit by assigning the eight inputs to unique outputs and cycling through the 8 selector

possibilities to be sure the appropriate value is chosen. I set input N to the value N, where N = 0,

1, ..., 7. For example, in Exhibit 24A, the selectors are set to 111, thus the last input, I7=7 is chosen.

See Exhibit 24B for the waveform confirming the results for all 8 selector values.

Exhibit 24B

31

Bit Duplicator

Inputs:

• one 1-bit selector inputs

Components


Outputs:


In order to select among the 8-bit output buses, I will need to apply a 1-bit selector to an 8-bit bus.

In order to do this, I create an 8-bit version of the single bit and then use the 8-bit AND created

above to select the required 8-bit output.

Exhibit 25

32

Testing: There are only two possible cases, so I test both for an exhaustive test. 0 should map to

00000000 and 1 should map to 11111111. See the waveform results in Exhibit 26.

Exhibit 26

8-bit OR with 8 inputs

Inputs:

• one 1-bit selector inputs

Components

• seven 8-bit OR gates from part (1)

Outputs:


Because each of the 8 components will output an 8-bit bus, and I need to select only one of these, I

will need an 8-bit OR gate that excepts eight 8-bit inputs. See Exhibit 27 for this circuit. While this

circuit could have been built by expanding the buses into bits and using 2-bit OR gates, I instead

simplify the circuit by combining several stages of 8-bit OR gates as created and tested above. This

simplifies testing so that we need only test that the connections work properly. We can do this by

ensuring that if the eight inputs are the 8 iterations of 0s and 1s with a single 1, then the output is

11111111. Rather than showing a waveform, I test this directly as shown in Exhibit 27.

33

Exhibit 27

34

ALU Circuit

Inputs:



• c_in – 1-bit operand

• Enable – 1-bit enabler

• ALU_SEL – 3-bit selector

Components

• one A OR B gate from part (1)

• one NOT(A) gate from part (2)

• one A + NOT(B) + c_in gate from part (3)

• one A+B+c_in gate from part (4)

• one A XOR B gate from part (5)

• two A AND B gates from part (6)

• one A – 1 + c_in gate from part (7)

• one A + c_in gate from part (8)

• two 1-bit 8-1 MUX

• one 8-bit 8-1 MUX

• two 2-bit AND gates

• one 3-bit expander

• one 8-bit expander

• one 1-8 bit duplicator


Outputs:

• M – 8 bit output

• m7 – 1-bit output



In the final circuit, I feed the ALU selectors and the outputs of the eight ALU components into two

1-bit 8-1 MUXes and one 8-bit 8-1 MUX. The same selector is used for each of the 3 MUXes to be

sure consistent outputs are chosen. One 1-bit MUX chooses the appropriate c_out value. The other

chooses the appropriate V (overflow) value, which equals 0 if not explicitly calculated. The 8-bit

MUX chooses the appropriate 8-bit output. From the final 8-bit output, I extract m7 for output. All

outputs are ANDed with the enable input so that selected output is produced only if the circuit is

enabled. Note that the enable must be converted to an 8-bit enable to enable the 8-bit output using

an 8-bit AND gate. The 1-8 bit duplicator I created is used to convert the 1-bit enable to an 8-bit

enable.

35

Exhibit 28

I test the following for each of the 8 ALU selectors. Expected outputs are stated. The Exhibits

indicate that all actual outputs match expected. Note that scenarios are tested in consecutive order.

Outputs for each ALU_SEL value are written as ALU_SEL=XYZ: M, m7, c_out, V. Many of the

scenarios were tested on individual components and continue to be satisfied here. Note in particular

that the tests on ALU_SEL=010 verify the carry and overflow are successful. Adding 10101010 to

NOT(01010101) is the same as adding 10101010 to itself. In 2s complement, this is the addition of

two negative numbers. The sum of two negative numbers should be negative, however the output is

positive. This is reflected by the observation that V and c_out equal 1.

• A=10101010, B=01010101, c_in=0, Enable=1 for all ALU_SEL permutations (see Exhibit

29)

• ALU_SEL=000: 255=(11111111)2, 1, 0, 0

• ALU_SEL=001: 85=(01010101)2, 0, 0, 0

• ALU_SEL=010: 84=(01010100)2,0, 1, 1

• ALU_SEL=011: 255=(11111111)2, 1, 0, 0

• ALU_SEL=100: 255=(11111111)2, 1, 0, 0

• ALU_SEL=101: 0=(00000000)2, 0, 0, 0

• ALU_SEL=110: 169=(10101001)2, 1, 1, 0

• ALU_SEL=111: 170=(10101010)2, 1, 0, 0


30)

• ALU_SEL=000: 255=(11111111)2, 1, 0, 0

36

• ALU_SEL=001: 85=(01010101)2, 0, 0, 0

• ALU_SEL=010: 85=(01010101)2, 0, 1, 1

• ALU_SEL=011: 0=(00000000)2, 0, 1, 0

• ALU_SEL=100: 255=(11111111)2, 1, 0, 0

• ALU_SEL=101: 0=(00000000)2, 0, 0, 0

• ALU_SEL=110: 170=(10101010)2, 1, 1, 0

• ALU_SEL=111: 171=(10101011)2, 1, 0, 0


31)

• All outputs should be 0, regardless of ALU_SEL value

Exhibit 29

37

Exhibit 30

Exhibit 31

38

Documents

Project 1A: 4-to-1 Multiplexer using 8-bit Buses on inputsi266/spr12_hw10/5381.pdfAlternatively, we can create this circuit using eight 1-bit 4-to-1 line multiplexers. The resulting