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Multiplexers

Lecture L6.6v

Section 6.2

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Multiplexers

• A Digital Switch• A 2-to-1 MUX• A -to-1 MUX• A !ua" 2-to-1 MUX

• #he $erilog if…else State%ent• ##L Multiplexer

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Multiplexers

Y4 x 1

MUX

s0s1

C0

C1C2

C3

Ys1 s0

0 0 C00 1 C11 0 C21 1 C3

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Multiplexers

Y

4 x 1MUX

s0s1

C0

C1

C2

C3

Ys1 s0

0 0 C00 1 C11 0 C21 1 C3

& 1

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Multiplexers

Y

4 x 1MUX

s0s1

C0

C1

C2

C3

Ys1 s0

0 0 C00 1 C11 0 C21 1 C3

1 &

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A 2 x 1 MUX

2 x 1

MUX

A

B

Z

s0

s0 Z

0 A

1 B

Z = A & ~s0 | B & s0

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A x 1 MUX

2 x 1

MUX

A

B

Z

s1

s0

2 x 1

MUX

2 x 1

MUX

s0

C0

C1

C2

C3

A = ~s0 & C0 | s0 & C1

B = ~s0 & C2 | s0 & C3 Z = ~s1 & A | s1 & B

Z = ~s1 & (~s0 & C0 | s0 & C1)| s1 & (~s0 & C2 | s0 & C3)

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A x 1 MUX

4 x 1MUX

C0

C3

Z

s1

s1 s0 Z

0 0 C0

0 1 C1 1 0 C2 1 1 C3

s0

C1

C2

Z = ~s1 & (~s0 & C0 | s0 & C1)

| s1 & (~s0 & C2 | s0 & C3)

Z = ~s1 & ~s0 & C0| ~s1 & s0 & C1| s1 & ~s0 & C2| s1 & s0 & C3

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Ys

0 A

1 B

'ro(le%)ow woul" *ou %a+e a

!ua" 2-to-1 MUX,

s

[A3..A0][B3..B0]

[Y3..Y0]!ua"2-to-1MUX

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mux.v

module mux24(A,B,s,Y);

input [3:0] A;input [3:0] B;input s;output [3:0] Y;

wire [3:0] Y;

assign Y = {4{~s}} & A | {4{s}} & B;

endmodule

s

[A3..A0][B3..B0]

[Y3..Y0]!ua"2-to-1MUX

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mux.v

module mux24(A,B,s,Y);input [3:0] A;input [3:0] B;input s;output [3:0] Y;

wire [3:0] Y;

always @(A,B,s) i (s == 0)

Y = A;

elseY = B;

endmodules

[A3..A0]

[B3..B0][Y3..Y0]

!ua"2-to-1MUX

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##L Multiplexer 1

2

3

45

6

7

8 9

10

11

1213

14

15

16

GND

Vcc1G

B

1C3

1C21C1

1C0

1Y

2G

A

2C32C2

2C1

2C0

2Y

74LS153

X X X X X X 1 00 0 0 X X X 0 00 0 1 X X X 0 10 1 X 0 X X 0 00 1 X 1 X X 0 11 0 X X 0 X 0 01 0 X X 1 X 0 1

1 1 X X X 0 0 01 1 X X X 1 0 1

B A C0 C1 C2 C3 G Y

Dual -to-1-line %ultiplexer