PHILIPS TECHNICAL TRAINING

L05 ATSC TRAINING MANUAL

PHILIPS CONSUMER ELECTRONICS64 PERIMETER CENTER EASTPO BOX 467300ATLANTA, GA 31146-7300

MM032405

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Table of Contents

ATSC Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Introduction to L05ATSC Chassis . . . . . . . . . . . . . . . . . . . . . . . . . .11

Customer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Main Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Video Signal Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Family Board Video Processing . . . . . . . . . . . . . . . . . . . . . . . . . . .20

ATSC Video Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Deflection panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

CRT board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Scan Velocity Modulation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . .27

Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

ATSC Audio block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Audio Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Locating Defective panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Service Alignment Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Customer Service Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

NTSC SYSTEM

To better understand the ATSC system, a short discussion of the present day NTSC systemwould be helpful.

A committee set up by the FCC in 1939 approved the present NTSC (National TelevisionSystem Committee) television system. Except for the addition of Color, Stereo, ClosedCaption, and Text, the NTSC system has changed very little.

The NTSC system is based upon a scan rate of 30 frames per second with a four by threeaspect ratio. The aspect ratio is the ratio of the picture width, which is four, and the pictureheight, which is three. This aspect ratio is based on 16mm film which was the most widelyused form of visual entertainment at the time television was being developed.

The scan rate of 30 frames per second is achieved by the picture being scanned with 262.5lines at a vertical rate of 59.94times per second. (Figure 1) Thepicture is scanned with two fieldsusing an interlace scan making525 lines per frame. With the num-ber of scan lines used, flickerwould develop if interlace scan-ning were not used. The even fieldstarts in the upper left hand corner.The Odd field starts its scan in theupper center portion of the picture.Because 40 horizontal lines areused for Closed Captioning,Teletext, and Color Correction,there are only 242.5 lines in eachfield that are actually visible.

ATSC SYSTEM

The Digital broadcast system, also know as ATSC (Advanced Television System Committee),delivers a high quality picture using complex video and audio compression. The ATSC channels use the same UHF frequencies and 6 Mhz bandwidth as the NTSCchannels.

There are two types of sets sold today, HD ready and Integrated. HD Ready sets do nothave an ATSC tuner, but are capable of displaying a High Definition picture. These sets showan enhanced picture when used with a progressive scan DVD player. However, this is notHigh Definition. A set top box is required to received the Digital TV broadcast. TheIntegrated sets have the ATSC Digital tuner built in.

As required by the FCC, all stations are co-broadcasting the Digital channels. If the plan isfollowed, all NTSC transmission in the United States will end on December 31, 2006.

FIGURE 1 - INTERLACE SCANNING

Page 1

When viewing the new ATSC receivers, the first difference one would notice is the widerscreen. The ATSC receiver has an aspect ratio of sixteen by nine. The screen width is 16units and the screen height is 9 units. NTSC uses a 4 by 3 aspect ratio. The next noticeabledifference would be a much sharper image. The picture definition of an ATSC receiver ismeasured in the same way as is in a computer monitor. The highest definition in the ATSCreceiver is 1920 pixels in the horizontal direction by 1080 lines. The NTSC display measuredin pixel resolution would be 313 by 243. The possible compression formats for the ATSCsystem are shown in Table 1 below. Although the ATSC tuning system is capable of receivingthese formats, the AV inputs are more limited as will be discussed later. Notice that bothprogressive and interlace scanning are possible. Whichever format is being transmitted, thePhilips L05 ATSC chassis will convert the aspect ratio to 1080 by 1920 pixels with a PictureRate of 60I. That is 1080 interlace scanning with two fields, each having 540 visible lines.Some signals may broadcast a 4:3 aspect ratio picture with sidebars. The actual picture

being transmitted has a 16:9aspect ratio. However, thevisible picture will have a 4:3aspect ratio.

Only the 1080i and 720P for-mats are considered to beHigh Definition signals. Allother formats are consid-ered to be a StandardDefinition format. The 480 x

640 and 480 x 720 formats are equivalent to the 480P or progressive scan outputs ofDVD players. The NTSC signals are converted by this set to 1080i before being fed to theCRT. If a weak signal is present, artifacts may become more visible.

BANDWIDTH

The ATSC signal uses thesame six megahertz band-width as the NTSC signal.(Figure 2) To achieve thehigher resolution of the ATVsystem, up to 19.28 Mbps(Mega bits per second) ofdata is delivered with theTerrestrial broadcast sys-tem. A higher data rate of38.57 Mbps is possiblewhen using cable or satel-lite. The higher data ratesystem also uses the samesix megahertz bandwidth.A Pilot signal is added 310kilohertz from the lower

edge of the band to key the AFT circuit of the receiver. The Pilot signal power is 11.3 dB

TABLE 1 - PICTURE FORMATS

FIGURE 2 - ATSC FREQUENCY SPECTRUM

Page 2

below the data signal power. To reduce interference with NTSC channels, the ATSC signal isoffset by +45.8KHz. After processing, the transmitted data signal has a bandwidth of 5.38MHz.

ATSC BROADCAST ENCODING

As with NTSC signal processing, the ATSC signal starts out with analog Red, Green, andBlue drives from the signal source. (Figure 3) The signal source could be a Camera, TapeDeck, or one that is computer generated. The signal could be either the higher resolutionHDTV or the lower resolution SDTV from a Composite NTSC signal. These signals are fed toa Matrix which produces a Y (luminance) signal, a Pr (red), and a Pb (blue) signal. Thesethree signals are fed to their respective A/D (analog to digital) converters. If the RGB signalsare of HDTV origin, the luminance-sampling rate for the A/D converters is 74.25 MHz. Forsignals from an SDTV source, the sampling rate is 13.5 MHz. These signals are then fed to

an MPEG-2 com-pression systemto reduce theamount of datanecessary tobroadcast thesignal. In asimilar manner,six channels ofaudio are fed totheir respectiveA/D convertersand then to theAC-3 audiocompressionsystem. TheVideo, Audio,Text, and Controldata streams are

combined into a single data stream by the Multiplexer.

ATSC COMPRESSION

The ATSC system uses the MPEG-2 compression format. It uses a 4:1:1 digital samplingsystem. (Figure 4 ) For every four Luminance samples, two Chroma samples are taken.These samples are placed in 8 x 8 arrays containing 64 samples. By using a complexmathematical function called a DCT (Discrete Cosine Transform), the amount of data neededto store an array is reduced. Four Luminance Arrays and two Chroma Arrays make up oneMacro block. In the 1080 by 1920 display mode, there are 68 rows of Macro blocks and 120blocks per row. In the SDTV mode which is 640 by 480, there are 30 rows with 40 blocks perrow displaying 1200 Macro blocks.

The Macro blocks make up an "I" (Intra) frame or a complete frame of video. (Figure 5) If

FIGURE 3 - ATSC ENCODING

Page 3

there is very little changein the video for the nextthree frames, the nexttwo frames are skipped.Only changes in the "I"frame are placed in the"P" (Predictor) frame.The "B" frames or theskipped frames arereconstructed in thereceiver. The Video and Audiodata streams along withthe Control and TextData are fed to theMultiplexer which pro-duces data packets thatare 187 bytes in lengthcontaining informationfrom all four sources. AllPicture, Audio, Control,and Text information arenow in a single data bitstream.

TRANSPORT

To prevent data loss intransmission, there arefour Forward ErrorCorrection circuits.(Figure 6) The four arethe Data Randomizer,Reed Solomon encoder,Data Interleaver, andTrellis Encoder. In theHigh Data rate system,there are only three

Forward Error correction circuits. The Trellis Encoder is replaced by a map per in the HighData rate system. The output of the Forward Error correction circuits are fed to aMultiplexer as an eight level digital data stream in the Terrestrial system. In the High DataRate system, this is a sixteen level digital data stream. The Multiplexer adds data segmentand data field sync. This Sync is for data signal synchronization and has no relationship tothe scan rate of the TV receiver. The Scan rate and Synchronization of the picture and audioare encoded in the video data stream. The Pilot is then added to the signal before it is sentto the Modulator and Up Converter. The Pilot is used to key the AFT circuit in the receiver.

FIGURE 4 - COMPRESSION

FIGURE 5 - FRAME ORDER

Page 4

DATA STRUCTURE

The Data Symbols are grouped into Data Frames,each containing two Data Fields. (Figure 7) EachField contains 313 Data segments. Each Segmentbegins with 4 symbols to provide segment synchro-nization and 828 Symbols of Data. The 828 Symbolsof the data segment contains the data of the 187bytes of a transport packet and the Forward ErrorCorrection overhead. In the Terrestrial broadcast

system, the Symbols are an eight levelsignal, each carrying 3 bits of data. Inthe high data rate system, the symbolsare a 16 level signal, each carrying 4bits of data. Each Data field is separat-ed by a sync segment. The DataSegment Sync is 4 symbols wide.(Figure 8) Three bits of data aremapped into 8 level VSB symbols.The voltage level of each symbols rep-resents a 3 bit data code. Since theTrellis encoder changes each 8 bit word

to a 12 bit word, 4 symbols are required to represent one byte of data. At the start of eachData Field, the Data Segment contains Field Data information and voltage reference levels to

FIGURE 6 - TRANSPORT

FIGURE 7 - DATA FIELDS

FIGURE 8 - 8VSB SEGMENT ENCODING

Page 5

train the data recovery circuits in the receiver.

Since the picture and audio information is in a Digital form, there will not be a problem withGhosting or Snow as with the present analog NTSC signal. Once sufficient signal is detectedby the ATSC receiver to operate the set, a clear picture will appear on the screen.

RECEIVER INPUT

In the receiver, the ATSC signal is fed to the Tuner from an Antenna, Cable, or Satellite.(Figure 9) The Tuner receives the ATSC signal and down-converts it in much the same

manner as in the NTSC tuner. The output of the Tuner, approximately 44 MHz, is fed to theIF filter and AFC circuit to separate the Pilot and Data signals. The Pilot is used to drive theAutomatic Frequency Control circuit to adjust the frequency of the 2nd mixer in the Tuner. Aprecise frequency and phase lock is necessary to recover the Data from the signal. The output of the IF circuit is fed to the Synchronous Detector and AGC circuit. It separatesthe Segment sync and provides AGC control for the Tuner. The level of the Segment synckeys the AGC circuit which feeds a DC control voltage back to the Tuner. The data signalfrom the IF circuit is also fed to an NTSC rejection filter. If the filter detects NTSCinterference, the circuit is switched On. If no interference is detected, the filter is switchedOff. The output of the NTSC rejection filter is fed to the Equalizer and the Data Field syncrecovery circuit. The Data Field sync recovery circuit is also synchronized by the Segmentsync from the Synchronous detector. The Data Field sync detector has as its output, DataField sync one and Data Field sync two. This sync has no relationship to the scan rate of theTV display. It is used to provide sync for data recovery. The picture will be processed andappear on screen once the Data Field Sync is detected. The output of the NTSC rejectionfilter is also fed to the Equalizer. The Equalizer compensates for linear channel distortions,such as tilt and ghosts. The output of the Equalizer is then fed to the Phase Tracker andTrellis Decoder or Map per. The Trellis Decoder is used when the signal is an eight levelterrestrial broadcast signal. The Trellis Decoder is switched Off and a map per is used if thesignal is a higher rate sixteen level 38.8 Mbps data rate signal. These circuits change theeight or sixteen level signal back to an eight bit data signal. The signal is then fed to theForward Error correction circuits which are the Data De-Interleaver, Reed Solomon Decoder,and Data De-Randomizer. This is the reverse order that was used by the Forward Errorcorrection circuits in the transmitter.

FIGURE 9 - ATSC TUNER

Page 6

DIGITAL DECODING

The output of the DataDe-randomizer is fed to aMultiplexer, which sepa-rates the Video, Text,Audio, and Control databit streams. (Figure 10)The MPEG-2 decoderdecompresses the Videodata bit stream to pro-duce a digital Y, R, and Bsignals. These signalsare fed to their respec-tive Digital to Analog(D/A) decoders. The sig-nal is now analog at thispoint. The analog Y,Pr, and Pb signals arethen fed to the monitor

section. Horizontal andVertical sync from thedecoder are also fed to themonitor to operate thesweep circuits. The Audiobit stream is fed to the AC-3decoder which produces sixdigital audio output signals.These are fed to theirrespective digital to analogdecoders. Six analog audiosignals are then output tothe monitor.

The decoder decompressesthe "I" frames of video andstores it in memory. (Figure 11) The decoder then processes the "P" frame and "I" frame toproduce a complete frame of video for the "P" frame. The "I" and "P" frames are interpolatedto recreate the two "B" frames of video. Once four frames are processed, they are read bythe sync generator to produce the "Y", "Pr", and "Pb" outputs to the monitor. The frames arestored in the 1080 by 1920 format by the DPTV120 decoder. The DPTV 110 monitor uses a1080 interlaced display. The odd lines are read for the first field and the even lines are readfor the second field. Each field displays 540 lines.

The Control data bit stream from the Multiplexer is fed to the Microprocessor. The Controldata contains information about the transmitted signal. For example, the number of Bitstreams, the Compression format used, Channel guide information, and the Closed Caption

FIGURE 10 - DECODING

FIGURE 11 - RECEIVE FRAME ORDER

Page 7

ATSC Cable Transmission

The previous material shows the 8VSB terrestrial broadcast system. Since cable TV is aclosed system, a faster data transfer method can be used. The 8VSB system can transmit amaximum of 19.2 megabits of data per second.

Cable uses either 64QAM or 256QAM to distribute digital TV data. This system uses acombination of amplitude and phasemodulation to transmit the signal.Compression methods and error cor-rection are the same as with the 8VSBsystem.

The 64QAM system is shown in Figure12. The 64QAM system is capable of adata transfer rate of 26.97 megabits persecond.

Figure 13 shows the 256QAM mapping.The 256QAM system is capable oftransmitting 38.4 megabits per second.

FIGURE 12 - 64QAM

FIGURE 13 - 256QAM

information. When the signal is transmitted in the lower bit rate SDTV mode, four or morevideo and associated audio bit streams can be transmitted. This allows up to four sub-channels in each channel.L05 ATSC CHASSIS

Page 8

Introduction

The L05 ATSC chassis is designed for the model year 2005. This set has a fully integratedATSC as well as a NTSC tuning system. This set will come in a 26 and 30 inch screen sizesin a 16x9 format. There will be a 32 inch version using a 4x3 ratio screen.

The set consist of a Main panel, CRT board, Side I/O panel, ATSC module, and Deflectioncontroller panel. The panels consists primarily of conventional components with some sur-face mounted devices.

The functions for the 1fH video processing is performed in one IC (TDA1200xx, IC7200), theHercules chip. This IC is located on the solder side of the Main panel. NTSC tuning andswitching for AV1, AV2, and CVI inputs are performed on the Main panel. The CVI inputlocated on the Main panel are for 1fH (480i) signals only.

The ATSC Tuner and 1fH to 2Fh conversion is performed on the ATSC module. Componentinputs for the CVI HD and HDMI are located on the ATSC module. This input can accept480i, 480p, 1080i, or 720p signals. The ATSC module converts whatever signal is applied toa 1080i format. The ATSC tuning system can tune all channels in the VHF, UHF, and Cablebands.

The Microprocessor communicates with the memory IC located on the Main panel, Keyboard,Remote Receiver, NTSC Tuner, Deflection Controller panel, and ATSC module. The MemoryIC retains the settings for favorite stations, customer-preferred setting, and circuit settings.The circuit settings can be accessed by the service technician via the Service AlignmentMode.

On-screen graphics and Closed Caption decoding are performed in IC 7200 for NTSC. IC7200 is located on the Main signal panel. On-screen graphics and Closed Caption for theATSC channels are performed in the ATSC module.

Customer Operation

There are two different menu structures in the L05 ATSC, one for the Analog and one for theDigital mode. Press the A/D button on the Remote control to toggle between the two modes.There is no selection in menu to switch between Digital and Analog. It can only be performedwith the Remote.

The Digital channels may have one or more subchannels if the station is transmitting in theSDTV mode. The customer must press the A/D button to place the TV in the Digital mode.Then press the channel number followed by a period and the sub channel number. If thestation is transmitting in the 1080i format, the sub channel number should be one.

Page 9

Rear input jacks

Family boardATSC Module

Side JackPanel

Page 10

Auto Program Channel 12

Main Picture Sound Features Install

LanguageTuner ModeAuto ProgramChannel EditFine Tune

Install Language Tuner Mode Auto Program Channel Edit Fine Tune

Auto Program Channel 13

Auto Program Channel 14

Analogue modeDigital mode

Auto ScanTuner Input: CableAutoscanning /

Digital 80

MainPictureSoundFeaturesInstall

LanguageTuner ModeAuto ProgramChannel EditAuto Chron...More

InstallLanguageTuner ModeAuto ProgramChannel EditAuto ChronWeak Dig Sig

Auto ScanTuner Input: AirAutoscanning /

Digital 35

OR

24

35

16

24

This page shows the channel installmenus. Note that there are differentmenus in the Digital and Analog modes.

The Digital mode in most cases willrequire 20 to 40 minutes to install thechannels.

Page 11

Install Language Tuner Mode Auto Program Channel Edit Auto Chron Weak Dig Sig

Channel Edit Channel Skipped

12

Install Language Tuner Mode Auto Program Channel Edit Fine Tune

Channel Skipped

Channel Edit Channel Skipped On

Channel Edit Channel Skipped Off

Main Picture Sound Features Install

LanguageTuner ModeAuto ProgramChannel EditFine Tune

Analogue modeDigital mode

MainPictureSoundFeaturesInstall

LanguageTuner ModeAuto ProgramChannel EditAuto ChronWeak Dig Sig

Channel edit

3 NTSC Skipped 4 NTSC Added 5 DTV Skipped 6 NTSC Added 7 NTSC Added 8 NTSC Skipped 9 NTSC Added ¸

5 DTV WATE-DTV

Channel edit

3 NTSC Skipped 4 NTSC Added 5 DTV Added 6 NTSC Added 7 NTSC Added 8 NTSC Skipped 9 NTSC Added ¸

5 DTV WATE-DTV

24

358

19

2476

68

8

USE THE A/DBUTTON TOSWITCHBETWEENANALOG ANDDIGITAL

This shows how to edit channels in boththe Digital and Analog modes.

It is necessary to have the remote con-trol to switch between the Digital andAnalog mode.

Page 12

Power Supply

Power Supply Block (Figure 14)

Both power supply sections are located on the Family Board. The supplies are divided intotwo sections, the Auxiliary and Main section. A single filter and rectifier circuit supplies bothsections. The Auxiliary supply operates in a low power mode when the load is reduced. Inthe standby mode, the 3.3 and 6 volt supplies are operating. The 3.3 volt supply providespower to the processor section of the Hercules. The 6 volt supply provides power to the IRreceiver. The Main supply is switched Off via the Standby line.

When the set is turned On, the "B" line from the Hercules processor goes High switching7547 which turns 7535, 7509, and 7545 On. The +3V3A, +6VA, +12VA, and +8VA suppliesare then switched On. The load placed on the Aux Power supply will cause it to switch to thefull power mode. At the same time, the STBY line switches Low turning the Main SMPS sup-ply On. The supply produces a +6 volt, +140 volt, -16 volt, and +16 volt supplies.

The +Vaudio (+16 volt) supply switches on the degauss relay.

FIGURE 14 - POWER SUPPLY BLOCK

Page 13

Auxiliary Power Supply (Figure 15)

IC 7510 is the heart of the Auxiliary Power supply. In the Standby mode, VIA the currentsensing and Control circuits, a low power condition is detected by the IC. The IC then goesinto a Burst Mode operation to reduce the power used by the circuit. In the Burst Mode, thesupply will operate at approximately 25 kHz. In full power operation the frequency will beapproximately 66 kHz.

When power is first applied to the set, Start up is supplied to the IC by the internal Start-Upcurrent through Pin 14. Startup voltage is also applied to the IC to Pin 2 by the AC_IN linewhich is tied to the neutral side of the AC line. During normal operation, power is supplied tothe IC by the HOT windings, Pins 1 and 2, of transformer 5504. Output drive from Pin 11 isapplied to the Gate of Transistor 7525. Voltage developed across the current sensing resis-tors in the Source of 7525 provides current sense information to the IC. When 7525 isswitched Off, the voltage on Pin 1 of 5504 goes High. This winding supplies the operatingvoltage the power supply circuit. It also turns Transistor 7567 On causing the Gate of 7525 tostay Low as long as Pin 1 of 5504 is High. This prevents 7525 from turning On until the fieldof 5504 has collapsed.

Regulation is accomplished by monitoring the +3 volt supply. This voltage is fed to Shunt reg-ulator 7542 which controls the current through opto-isolator 7516. Shunt Regulator 7542begins conducting when Pin 3 of the IC reaches 2.5 volts. At this point current flows throughthe opto-isolator, 7516. The transistor inside 7516 turns On applying a control voltage to Pin6 of 7510. If a problem should develop in the feedback circuit causing an excessive voltageon Pin 6, Transistor 7549-2 will turn On, switching Transistor 7532 On. This will a voltage tothe Demag circuit on Pin 7 causing the IC to latch Off. The IC will stay latched until power isremoved and reapplied to the set.

In the Standby mode, the "B" control line from the Hercules Processor is Low. Only the +3,+3V3, and +6 volt supplies are present. When the set is turned On, the "B" line will go High,turning Transistors 7509, 7545, and 7535 On. This will switch On the +8VA, +12VA, +8V,+3V3A, +6VA, and +5V supplies.

In normal operation, voltage from Pin 12 of 5504 is rectified by 6540 to produce a negativevoltage which prevents Transistor 7561 from turning On. If AC is removed from the set, thisnegative voltage will disappear. The voltage across the filter capacitors on the +3V line willturn 7561 On. The Power Down line will then go Low signaling the processor to shut the setdown.

Page 14

Mono Carrier: AUX Power Supply

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Vaux_GND

2523

1n0

I589

6546

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100n

2543

HEATSINK0083

1 2

BAS316

6543

5523

4551

I538

I599

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3528

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68K

3535

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9523

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2520

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Vaux_GND1

3594

6542

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22K

3586

5K6

82K

I510

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I547

Vaux_GND

Vaux_GND

Vaux_GND

4523

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3534

F577

3533

14

3 2

7516TCET1103(G)

Vaux_GND1

Vaux_GND1

Vaux_GND

BZ

X38

4-C

6V8

6547

3588

470K

1n0

2538

F534

7575PDTC143ZT

2579

10n

I593

Vaux_GND1

F582

100n

2576

4540

220R

3561

5527

Vaux_GND

9524

3525

47n

2521

2588

2589

2u2

Vaux_GND

1m0

2536

F537

Vaux_GND1

3562

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95544567

I539

Vaux_GND1

I568

PDTC143ZT

680R

3542

7547

470u

2587

3549

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Vaux_GND

Vaux_GND

BC857B

3583

5K6

7585

3596

10K

2525

470p

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470u25

34 16V

BA

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6

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6553

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6550

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1n0

2544

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I540

Vaux_GND1

F581

I595

F585

2582

100n

3527

47K

3565

15K

2546

2u2

Vaux_GND

2557

47u

16V

Vaux_GND1

9515

7567BC847B

Vaux_GND

3595

100K

7525

10u

2583

3539

1K0

3550

220K

7510

3547

68K

3K3

3567

Vaux_GND

F580

9

2577

100u

10

11

12

2

4

5

6 7

8

SS28411-00

5504

1

3553

27K

3543

10K

STPS10L60D

6552

56K

3530

I590

I529

2528

470n

Vaux_GND

2K2

3545

F586

I528

I531

3589

10K

Vaux_GND13551

4R7

123

MAINSUPPLYGND

1535

6539

SB340L-7010

7576BC847BW

I560

2535

I597

3526

68K

3566

3597

47K

68p

2592

SI2307DS7509

5524

10u

9536

21

335

31

1K0

TL4

31C

Z-A

P75

42

Vaux_GND1

I530

BA

S31

6

6536

3598

Vaux_GND1

Vaux_GND1

F583

2556

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9530

16V

2

1 3

2555

47u

16V

7543L78L33ACZ

+3V

+5V

+8VA

Stdby_con

+6VA+5V

+3V3A

+6V

+6VA

VDC

+3V3A+8V

AC_IN

VCC

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B

3139 123 5933.1

A10

---JMP

REGION

354027VRF-HD

---

---

JMP

95309534

NAFTA30WSRF-HD

------------

SIZE

354835513566452345404548455145664585552365537535951595249529

---

---100MHZ 120R

BAS316SI2307DS-E3

---------------

---

---

------------

JMP---

JMP---

---100MHZ 120RBAS316

SI2307DS-E3---------------

FIGU

RE

15 - AU

XILIA

RY

PO

WE

R S

UP

PLY

Page 15

Main power supply (Figure 16)

The Main Power supply provides the VBAT (141 volt), and Audio voltage supplies. This sup-ply is switched Off during the Standby mode. During Standby the STBY_Con line is Highwhich turns Transistor 7573 On. This causes the opto-isolator 7513 to turn On hard. Thisplaces a higher voltage on the control Pin of IC 7511 causing the IC to shut down. The oper-ating voltage from the Auxiliary supply keeps a small voltage on Pin 2 of 7511 to prevent itfrom cycling On and Off.

When the set is turned On, the STBY_Con line goes Low switching 7573 Off. The VBAT sup-ply is the reference voltage for regulation. Since this voltage is missing during startup, theShunt Regulator 7571 is turned Off. The voltage on Pin 6 of 7511 goes Low, which turns thedrive from the IC On. When the set is On during normal operation, the supply voltage on Pin2 of the IC is supplied by Pin 2 of Transformer 5512. When the VBAT supply reaches thecorrect voltage, Pin 3 of the Shunt Regulator 7571 reaches 2.5 volts switching it On. Thisswitches the opto-isolator On to provide a regulation feedback path.

Transistor 6551 provides a power on ramping of the VBAT supply.

Power FET drive points

Page 16

-T

V

-T

+T

Rs

Rh

KA

RE

F

Vcc

Gnd

Ctrl

START-UP

CURRENT SOURCE

VALLEY

START-UP

CURRENT SOURCE

CURRENTSENSING

OUTPUTDRIVER

OVERPOWER

LOGIC

CONTROL

CIRCUIT

MAXIMUMON-TIME

PROTECTION

VOLTAGECONTRLLEDOSCILLATOR

OVERTEMPERATUREPROTECTIOM

POWER-ONRESET

SUPPLYMANAGEMENT

FREQUENCY

PROTECTION

CONTROL

INPUTCONTROLCIRCUIT

BURSTDETECTOR

Drain

HVS

Sense

Demag

Driver

9V3

*

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D

RE

S

15V5

HOT

G

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Front Interface Panel

6

*

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100n

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*

*

RE

S

(For

TEA1506T/N1

2V3

..V.. Normal Operation

POWER SUPPLY

*

160V

0V

T4E.250V

Lightning Protection

"$"

140V

Provision For

15V6

COLD

*

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7

*

16V4

2506

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To P14 Of

Panel

**

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6551

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9506

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9

13

14

15

16

17

182

3

4

5512

10

11

12

1M5

3504

2503

2n2

I502

F573

1K0

3515

F503

I527

Audio_Gnd

2502

PFC50001501

12

3M3

1505

F506

3501

22u

5563

AUDIO_GND2

1510

2574

1n0

1500

9513

9512

3509

2R0 2n2

2504

I522

9511

TCET1103(G)7513

14

3 2

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2562

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3523

3

2

1

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2541

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9503

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62

5551

6575

27u

5552

3502

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PDTC114ET7573

F509

3519

15K

9510

MainSupplyGnd

47K

3522

2518

10n

I515

I508

3574

7511

I511

15n

2571

2542

F501

F552

3524

47K

9505

I576

F504

3575

82K

3K3

AUDIO_GND1

3521

3573

15K

BC857B7541

1n0

2517

3571

F502

MainSupplyGndA

I551

9500

2515

470p

5511

F500

I573

I578

AUDIO_GND2

I574

2K2

3513

4K7

3576

I520

I519

F507

6511

I514

AUDIO_GND1

Vaux_GND1

F51

0

6562

9563

F508

F542

2512

3M3

3506

4R7

3511

F564

F5659577

1577

2.5AF

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2551

1n0

2563

2501

100p

2519

2.5AF

1572

I571

F561

5562

3505

2570

2507

10n

2572

3510

7514BC847B

3517

330K

2R0

1K2

I524

I572

3512

I517

BZ

X38

4-C

12

6541

2 3

5500

1 4

2514

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2561

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9502

Vaux_GND1

3K3

9501

1 4

2 3

I518

DMF2405H60

5501

1503

3

4

1

2

AUDIO_GND2

470n

I507

2500

1 4

9504

6500

2355061 4

2 3

12

DMF35

1504

3514

3503

DSP-301N

2509

2513

470p

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I516

5513

1u0

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Stdby_Con

+Vaudio

VDC

Vbatt

+6V

A1

FIGU

RE

16 - MA

IN P

OW

ER

SU

PP

LYP

age 17

Video Signal Flow

Overall Block (Figure 17)

The video processing section located on the Family Board (Mono Carrier board) performs allof the 1fH processing. AV1, AV2, CVI, and Side inputs are fed to this board. The CVI inputon this board will only accept 1fH signals. 1fH RGB signals from the Family board is fed tothe Deflection board and then to the ATSC module. The ATSC module rescales the picturefrom the Family board. It also has an HDMI and CVI connection. The HDMI and CVI con-nections can accept either 480i, 480p, 720p, or 1080i. The ATSC module also has a built inDigital Tuner. The ATSC module resizes the picture to 1080i regardless of the input.

The YPbPr output of the ATSC module is fed to the Deflection Controller board for video pro-cessing and deflection control. RGB from the Deflection Controller board is fed to the CRTpanel.

Customer adjustments such as Brightness, Contrast, Color, and Tint are performed on theDeflection Processor panel.

FIGURE 17 - OVERALL VIDEO SIGNAL FLOW BLOCK

Page 18

FIGURE 18 - FAMILY BOARD VIDEO PROCESSING Page 19

Family Board Video Processing (Figure 18)

Video processing on the Family board is performed by IC 7200, Hercules. IF from the NTSCTuner, 1000, is fed to SAW filer 1002 and then to 7200. The demodulated video is fed to aninternal switch which selects between the Tuner video, AV1, AV2, or the Side Jack panel.Monitor video is output on Pin 81. There is no monitor out for the ATSC section. The video isfed to an internal Comb filter to separate the Luminance and Chrominance, YC. The Chromais fed to the Color Demodulator and to the YUV switch along with the Luminance. The YUVswitch selects between the internal demodulated signal and the YPbPr signal. This is a 1fHonly input.

NTSC Tuner (Figure 19)

The Tuner for the NTSC signals is located on the Family board. The VT_Supply is derivedfrom the VBat supply. It is regulated to 33 volts by zener diode 6001. The Tuner is controlledby the I2C bus from the Hercules processor.

INRF

*

*

*

*

34V

5

**

FOR ITV ONLY

4.3V

4.3V

OF

A4

*

FOR EMC ONLY

RES

TUNER IF

RE

S

*

*

*

4.9V

*

POWER SUPPLY

TO 0282

*

A4

For

Com

pair

only *

RES

CGND

CGND

*

CGND

6001

BZ

X79

-C33

F003

4001

30

I016

60I001F007

F004

2003

2007

F008

I014

4000

I015 3001 40

5002

CGND

2002

2008

CG

ND

F005

CGND

CGND1011

2001

I00240

03

F011

F002

3000

CGND

2

VT

47n

2004

1415

6N

C1

NC

2

104

SC

L

5

SD

A

7V

S9

VS

T

TUNER

8

AD

C

1

AG

C

AS

|CE

3

IF

11

1213

1000

2005

10u

50V

1005123

F001

3009

BAS

60

1010

2006 47

0u

CGND

VT_Supply

SCL

SDA

+5V

3

FIGURE 19 - NTSC TUNER

Page 20

Video Test Points (Figure 20)

The connection points between modules can provide test points to determine which circuitboard requires repair or replacement. The RGB and Sync signals from the Hercules is fed tothe Deflection Controller board on connector 1254. These signals are buffered by transistors7492, 7491, and 7490 before being fed to the ATSC module on connectors 1401 and 1254.After the signal is processed, it is fed back to the Deflection panel on connectors 1255 and1403. Refer to the wiring interconnect diagram for additional check points.

FIGURE 20 - VIDEO TEST POINTS

1403 1255

Page 21

ATSC Block (Figure 21)

RGB from the Deflection module and Component video from the YPbPr input if fed to U1201,switch. The YPbPr input on the ATSC module can be 480i, 480p, 720p, or 1080i. The A/D,U201 shares a 16bit bus with the HDMI receiver. The Customer selected signal is fed toU201, the ATSC processor. The ATSC processor enhances and rescales the signals fromthese inputs. The ATSC tuner, U701, is fed to the IF section, U703, and then to filters U704and U703. The ATSC processor can decode either 8VSB terrestrial, 64QAM, or 256QAM sig-nals.

The output of the ATSC processor is fed to the POD processor IC. Most of the POD process-ing circuit is not present since this set does not have that feature. Two memory ICs, U502and U503 stores the picture information while the video is being processed. The analogYPbPr 1080i signals are output to the Deflection panel.

FIGURE 21 - ATSC BLOCK

U1201

Page 22

FIGURE 22 - DEFLECTION BLOCK

Deflection Panel Block (Figure 22)

The Deflection panel performs the signal processing and Deflection processing functions.YPbPr from the ATSC module is fed to 7402 signal processor. This circuit performs the Color,Tint, Brightness, and Contrast control functions. The Y signal is fed to a Sync Separator toseparate the Horizontal and Vertical Sync which is output on Pins 37 and 35. RGB is outputon Pins 12, 13, and 14. These signals are sent to the CRT panel.

Horizontal drive is output on Pin 37 where it is fed to the deflection circuits on the Familyboard. Vertical Sync is output on Pin 35 of 7402 to IC 7404. IC 7404 develops the Verticaland EW drive for the deflection circuits.

DC monitor signals are output on Pins 4, 6, and 7 of 7402 and fed to an Under voltagedetection circuit. If a positive or negative voltage develops on any of these lines, this circuitwill force Pin 21 of 7404 Low, causing the set to shut down. The shutdown is activated whenPin 21 goes below 5 volts.

CRT board

As shown in figure 23, the Filament voltage, 200 volt, 8 volt, and 12 volt supplies are fed tothe CRT panel on connector 1351. The 141 volt supply powers the SCAVEM.

Page 23

Deflection Controller board

Page 24

Deflection (Figure 23)

Horizontal drive from 7221 is fed to Transistor 7404 located on the Family board. This drivecircuit has two power sources. During startup, it is powered by the +6 volt supply. Once theHigh Voltage circuit is running, it is powered by Pin 9 of the IFT. 7404 drives Transformer5402 which drives the HOT (Horizontal Output Transistor). The HOT drives the IFT and theHorizontal Deflection Coil. The IFT is powered by the VBAT (141 volt) supply.

The IFT produces High voltage, Focus voltage and G2 voltage to drive the CRT. In addition,a 200 volt supply is produced to drive the CRT panel, a +14 and -14 volt supply for theVertical output, Filament voltage, +200 volt VideoSupply, and a +12V_lot supply.

Transistor 7408 monitors the IFT secondary to sense the presence of over voltage. If theHigh Voltage goes High, the voltage on Pin 6 of the IFT will go High. When the voltage ondiode 6480 exceeds 15 volts, transistor 7408 will turn On. If 7408 turns On, it will turn 7407On causing the x_ray protect line to go Low. The Processor will then shut the set down. Inaddition the EW_DRIVE circuit is monitored. If the EW_DRIVE fails, transistor 7406 will turnOn constantly placing a dc voltage on the source. This will turn 7407 On.

IC 7451 is the Vertical Output IC. It is powered by the +14 and -14 volt supply from the IFT.The Vertical pulse is rectified by 6458, keeping the V_PROTN line High. If the vertical outputshould fail, the V_PROTN line will go Low. The Hercules processor will then shut the setdown.

G2

FOCUS

EHT

VV

NC

*

10K

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CRT Socket

RES

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A5 COILA5

A

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A5,B1

3432

A2,A5

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6461

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CRT_GND

F404

CRT_GND

3435

10RD

MV

1500

M64

04

MainSupplyGnd

I482

GND_EW

I424

2433

I453

3466

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2421

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3426

100K

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6

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1234567

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6457

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3425

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36

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3477

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6

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6487

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8V2

6492

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CR

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2418

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CRT_GND

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2461

6482

BZX384-C6V8

CRT_GND

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100n

2471

6476

3n3

BZ

V85

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8

3458

4R7

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2432

F401

3460

68K

6488

BZX384-C33

CRT_GND

GND_HOR

9490

3478

10R

3472

2494 470p

3453

56K

100K

F453

3408

I455

F483

2u2

2466

100R

3489

470u

2449

CRT_GND

+12V_LOT

6453

5458

I466

RGP10G

CRT_GND

F457

3414

4R7

GND-LINEDRIVE

+12V_LOT

CRT_GND

470u

CRT_GNDVT_Supply

GND_EW

2460

5459

560n

150R

3413

3480

Vbatt

F452

GND_EW

3459

680K

3441

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2412

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100n

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2464

2426

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10K

3497

6464

BZ

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CRT_GND

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10K

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2448 470p

I425

7405

3427

680K

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15

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3488

220K

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3493

GND_DEF

BYV29X-500

6467

2435

1K0

3481

GND_DEF

GND_HOR

Vbatt

BC857B7410

CRT_GND

F459

GND_HOR

3439

10K

2451

BZV85-C6V8

6452

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4R7

3451

F402

2n2

2463

I430

2477

4434

CRT_GND

BC857B7408

+6V

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3461

F461

I468

BAS316

6458

100n

2410

1405

F419

I494

I411

BZ

X38

4-C

6V8

6434

3485

I415

9440

I489

5457

3491

33K

2467

220n

CRT_GND

I416

2454

470u

F455

I412 3433

4R7

RGP10D

6471

9476

I418

2470

220n

CRT_GND

1R0

3450

BA

S31

6

6490

680K

3436

3428 22K

2411

I457

2468

100n

5452

10u

44013467

6489

BA

S31

6

GND_EW

33n

2409

F472

GND_DEF

I410

I499

CRT_GND

I417

+14V

9402

2416

I492

3402

330R

22K

3469

6486

BY

D33

D

I469

4R7

3419

9435

I434

I432

2R2

3440

2495

100n

CR

T_G

ND

2422

I435

I460

3468

3463

F462

3462

18K

CRT_GND

I462

3456

1R0

150R

3412

BZX384-C15

6449

F475

F464

GND_HOR

I458

CRT_GND

33K

3492

220n

2465

2493

GND_DEF

I440

470p

7407

I456

PDTC144ET

MainSupplyGnd

220p

2497

GND_EW

GND_EW

I461

470p

2492

Frame_FB

HFB

EHTinfo

Filament

EHTinfo

-14V

EHTinfo

Filament

X_RAYHD

EW_DRIVE

Vguard

+12V_LOT

VDRA

V_PROTN

+14V

VDRB

SVM_ROT

F_15050_017.eps

A2

SIZEREGION

100R100V 100N

---

2KV 220P1K6V 12N630V 27N

------

250V 330N250V 1U22KV 330P2KV 330P

NAFTA27VRF-HD2KV 820P1K6V 12N630V 27N

2411241224132413241724182419

---

30WSRF-HD

242124222433245134183424342534343435

1MA 612V1MA 612V

------

------

250V 390N250V 560N

------

2KV 220P100V 220N

100R---------

SIZEREGION

---

34783489440144185408545054566476941194359440944294769489

NAFTA27VRF-HD

---820K

------------

W7132-004 YJF0101-85039 B

---BZV85-C6V8

JMPJMP---

JMP------

30WSRF-HD34423459

---470K

------------

W7131-003 YJF0101-85038 BSD20417-02 YBZV85-C6V8

---JMP---

JMP---

FIGU

RE 23 - D

EFLECTIO

NPage 25

B1

VV V

Blue

Green

Red

330853249306930893099324

------

100MHZ 50RJMPJMPJMP---

DC_FilamentFrom 1401 of

2313

47u

2347

470u

*

CRT SOCKET

*

EHT-INFO

A2,B3

DY

N F

OC

US

AQUADAG

3R3

F397

11354

200V EHTDeflection

*

FOCUS

*

LINE + FRAME DEFLECTION

VG2

VG

23R3

33R

CRT

**

B2

FROM LOT, MAIN CHASSIS

B2

ST

AT

IC F

OC

US

WIRE

3306SET

REGION

*

30WSRF-HD

TO CRT SOCKET

VG

1

Line + Frame

B2

NAFTA

I336

I333

TO

CR

T S

OC

KE

T

I351 I323

F339

5324

3999

1K2

3351

150R

3357

I331

GND_LS1

GND_RGB

9309

10n

2357

1335

GND_LS1

F342

3336

1K0

3334

1K0

1K0

3332

5308

5u6

F341

GND_LS1

I379

3307

12

56789

1

1011

4567

1351123

GND_LS1

3306

3345

9308

3308

1K0

3333

100R

3331

100R

2324

10n

2320

820p

GND_LS1

F338

2321

10n

F399

I335

GND_RGB

I377

F340

BAV21WS

6331

BA

V21

WS

6332

6333

I332

GND_RGB

BA

V21

WS

10n

2319

101112

56789

GND_RGB

9324

+12V_SVM

F331

F354

F347

5304

+8V_+12V

13363347

1K5

GND_LS1

F352

F398

I322

4n7

2317

RE

S

+3V

F383

GND_RGB

+200A

+12A1

3391

3390

I327

GND_RGB

I334

5u6

5303

+200A

I308

9306

3305

1R0

6325

3335

100R

BZ

X79

-C3V

3

+12A13325

1K8

9310

F345

I302

I330

GND_RGB

9328

GND_LS1

+141VI373

I348

GND_LS1

+8V_+12V

+12A

I350

R

SVM_ROT

G

B

FIGU

RE 24 - C

RT

Page 26

B2

Def

lect

ion

Con

trol

ler

- A

TS

C

I3471K

0

F34

8

9302

C

3V4

158V

5

5V

139V

E

B

C

E

3V4

3V4

B

E

3V4

B

3V3

3V3

12V

7

C

3V6

3V3

3V3

3V3

128V

7

158V

5

5V

128V

4

127V

820

0V

To

1404

Of

Or

B-C

RT

G-C

RT

G -

AM

PLI

FIE

R

B1

B -

AM

PLI

FIE

R

140V

B2

B2

R -

AM

PLI

FIE

R

162V

13V

3

**

***** *

*

*

129V

3V6

RG

B A

MP

LIF

IER

3V3

CU

T O

FF

Fro

m 1

202

of

Def

lect

ion

Con

trol

ler

of T

riden

t Pan

el

B1

B1

R-C

RT

GN

D_R

GB

I328

4n7

2332

1 2 3 4 5

F33

4

1340

F33

2

GN

D_R

GB

F33

6

2341

8p2

8p2

233723

35

8p2

3327

220R

+12

A

2334

100n

2K7

3342

+12

A

BA

S31

6

6308

GN

D_R

GB

3V

IN

VIP

1V

OC

8

3353

2K2

MIR

RO

R

MIR

RO

R

GND 4

IOM

5

VC

N7

VDDH6

2VDDL

VFB9

DIF

FE

RE

NT

IAL

ST

AG

E

MIR

RO

R

MIR

RO

R

V B

IAS

CU

RR

EN

T S

OU

RC

E

7330

TD

A61

11Q

2336

33n

+20

0A

6307

3317

I391 I3

46

I399

GN

D_R

GB

120K

3341

3323

470R

I313

+3V

9304

I390

9303

I397

GN

D_R

GB

I309

I394

GN

D_R

GB

GN

D_R

GB

BC

847B

7353

2K7

3354

3352

120K

22p

2355

I344

100n

2340

GN

D_R

GB

GN

D_R

GB

100R

3322

GN

D_R

GB

GN

D_R

GB

3326

100R

4314

2369

330p

I395

+12

A

3338

100n

23311K

0

3340

2K2

I310

GN

D_R

GB

GN

D_R

GB

1K0

3344

100R

GN

D_R

GB

22p

2360

3328

I382

4315

0078

4313

2330

100n

F33

5

I342

I389

I329

GN

D_R

GB

GN

D_R

GB

4312

+3V

GN

D_R

GB

GN

D_R

GB

680p

2343

VIN

VIP

1V

OC

8

TD

A61

11Q

GND 4

IOM

5

VC

N7

VDDH6VDDL 2

VFB9

3

MIR

RO

R

MIR

RO

R

DIF

FE

RE

NT

IAL

ST

AG

E

MIR

RO

R

MIR

RO

R

V B

IAS

CU

RR

EN

T S

OU

RC

E

7350

7352

BC

847B

I384

3337

120K

GN

D_R

GB

3339

2K7

220R

3321

0077

GN

D_R

GB

I383

I396

I398

0069

GN

D_R

GB

2333

680p

33n

2346

+20

0A

2339

100n

22p

2358

9301 G

ND

_RG

B

4311

GN

D_R

GB

GN

D_R

GB

GN

D_R

GB

2356

33n

2353

680p

6

2VDDL

VFB9

VIN

3

VIP

1V

OC

8

MIR

RO

R

MIR

RO

R

DIF

FE

RE

NT

IAL

ST

AG

E

MIR

RO

R

MIR

RO

R

V B

IAS

CU

RR

EN

T S

OU

RC

E

4GND

5IO

M

VC

N7

VDDH

TD

A61

11Q

7340

F33

7

4n7

2344

220R

3324

GN

D_R

GB

GN

D_R

GB

GN

D_R

GB

2K2

3343

3320

+20

0A

+12

A

+3V

470R

100n

2338

3355

1K0

I311

BC

847B

7351

470R

3329

GN

D_R

GB

I392

4n7

GN

D_R

GB

GN

D_R

GB

2352

+12

A1

I393

+12

A1

R CU

T_O

FF

B +12

A1

CU

T_O

FF

G

FIGURE 25 - CRT DRIVE Page 27

Vcc

TEMPERATUREPROTECTION

ANDSHORT CIRCUIT

20K

20K

STANDBY/MUTE LOGIC

C

BC327-40

ROTATION

B

2R7

*

*

8V1

5V5

120V3

0V3

For ATSCE

B6V

TO

For HD

B

121V

5V2

B125V

C121V

E125V

E

B6V4

TDA8941

C

3V9

ROTATION & SCAVEM

RO

TA

TIO

N C

OIL

E

B1

0V7V4

SC

AV

EM

CO

IL

E

C

SCAVEM

3V1

52V2

5V1

5V3

For ATSC Only

C

*

B

TO

C

13V

E

*

B

4V1

5V3

0V8

47K

E

2V8C

**

52V2

E2V8

C

*

*

*

0V

4V

B

F382

270R

I361

0087HEATSINK

470p

2365

120K

3366

56R

3393

GND_RGB

2383

GND_RGB

560R

3371

220p

I364

KTD600K7364

470p

2364

2387

10n

GND_RGB

GND_RGB

I368

BA

V99

6363 GND_RGB

I325

270R

3392

1362

123

I370

2368

100n

GND_RGB

F361

150K

3372

7365BC847B

236110

0n

2382

100n

GND_RGB

GND_RGB

2392

4n7

560R

3361

3364

+12V_SVM

3396

1K8

9325

GND_RGB

GND_RGB

GND_RGB

10u

2390

+12V_SVM

6362

1N41

48

560R

3368

4362

I375

I315

3399

4363

3398

47K

+12V_SVM

7363KTB631K

7361BC847B

3R3

3370

GND_RGB

100n

2389

GND_RGB

100n

2367

I314

2370

100n

GND_RGB

9323

6K8

3350 I381

3377

3379

GND_RGB

1K8

2393

220p

3365

4K7

150R

3378

100n

2385

5361

73325362

1u0

3397

2381

47n

50V

18K

3381

33K

3380

100n

2391

3310

22R

3309

I366

220R

100n

2384

150K

3369

9393

3374

10R

3384

330K

GND_RGB

4K7

3385

4K7

3395

F381

I317

I321

GND_RGB

8

IN+3

IN-5

4 MODE

2OUT+

7OUT-

6 SVR

1

VCC

I365

I320 7366

GND

3394

5K1

3373

1K5

22R

123

3311

1361

10R

3362

7331BC847B

I362

GND_RGB

9322

I387

3383

1K0

I371BC337-407333

560R

3363

7362BC857B

+12V_SVM

I326

I386

I380

120K

3367

I319

6334

BZ

X38

4-C

3V3

I360

1381123

6361

BA

V99

47u

200V

8K2

3382

2363

I367

GND_RGB

GND_RGB

I369

F362

GND_RGB

I316

SVM_ROT

+141V

FIGU

RE 26 - SC

AVEM AN

D R

OTATIO

NPage 28

CRT Drive (Figure 25)

RGB drive is fed to the CRT board on connector 1340 to transistors 7351, 7352, and 7353.The signal is then fed to the three CRT drive amplifier ICs, 7330, 7340, and 7350. Theseamplifiers are powered by the 200 volt supply.

SCAVEM and Rotation (Figure 26)

The Rotation and SCAVEM (SCAn VElocity Modulation) signals are both on the SVM_ROTline. The Rotation signal is a low frequency signal. The high frequency is filtered out bycapacitor 2367. The Rotation signal is blocked by capacitor 2391.

The Rotation signal is amplified by 7366. A four transistor output circuit drives the SCAVEMcoil.

Audio

Family board audio input (Figure 27)

NTSC IF for audio, Side input, AV1, and AV2 are fed to the Hercules, 7200. The selectedaudio is output on Pins 66 and 67 and fed to the ATSC module. Audio demodulation forNTSC in done in the Hercules.

FIGURE 27 - FAMILY BOARD AUDIO INPUT

Page 29

FIGURE 28 - ATSC Audio BlockPage 30

ATSC Audio Block (Figure 28)

All of the audio in the set is routed through the ATSC module. Audio for the HD CVIconnection located on the ATSC module and audio from the Family board is fed to switchU104. The selected audio is fed to A/D U103. Digital audio is fed to the ATSC decoder,U201. Digital audio from the HDMI receiver, U802, is also fed to U201. The ATSC decoderselects between the HDMI, Analog inputs or the internal ATSC decoder. After processing,digital audio is output to U101, buffered by U102, and then fed back to the Family board.

Audio Output (Figure 29)

Selected audio output from the ATSC module is fed back to IC 7200, Hercules. The Herculesperforms the audio control functions, Volume etc. The audio is then output on Pins 68 and 69and fed to the audio amplifier, 7990. The audio amplifier is a dual 10 watt amplifier. It ispowered by the +VAUDIO and -VAUDIO supplies which are +16 and -16 volts. To mute theamplifier, the VOL_MUTE line goes Low, switching transistor 7992 Off, switching transistor7991 On. The output of the amplifier is fed to the Side Jack panel.

Page 31

FIGURE 29 - AUDIO OUTPUTPage 32

Side Jack Panel (Figure 30)

The output of the audio amplifier is fed to the Headphone Jack located on the Side Jackpanel. The output to the speakers is switched Off when the headphone plug is inserted.

Locating the Defective panel (Figure 31)

When troubleshooting the set, the defective panel requiring replacement or additional repairmust be located. The Power supplies, Deflection, NTSC Tuning, 1 fH inputs, and Audiooutput are located on the Family board. The 2 fH inputs, ATSC Tuning, Digital Audioprocessing is located on the ATSC panel. Video processing and Deflection signal circuits arelocated on the Deflection Controller panel.

If the set turns On without a picture or sound, first check the Power supplies located on theFamily board. If the set comes On, then shuts Off, there may be a problem with the shut-down circuits also located on the Family board. If the picture is missing, but sound is present,switch to an ATSC channel. If the picture returns, the problem is most likely on the Familyboard. If the picture is still not present, check the YPbPr signals on connector P1255 locatedon the ATSC module. If video is present at this point, then check the Deflection Controller.Check the RGB out to the CRT panel on connector 1340 on the CRT panel.

If High Voltage is not present when the voltage supplies turn On, check the Horizontal andVertical drive from the Deflection Controller panel. These signals can be checked on connec-tor 1251 located on the Family board.

*

*

470p

F47

0pF

HEADPHONE

ECO SUB

TO

TO

SPEAKERS

I166

I168

3157123

1279

6

7

8

9

12321

2

3

4

5

I162

I163

2181 1u

I170

I169

I171

39K

3161

12345

1254

2176

2178F154

3156

1278

1234

FIGURE 30 - SIDE JACK PANEL

Page 33

FIGURE 31 - WIRING INTERCONNECT DIAGRAMPage 34

System Control (Figure 32)

The Main system control is performed by the microprocessor located in the Hercules, IC7200. The customer communicates with the processor via the IR sensor and Keyboard. TheI2C bus communicates with the Tuner 1000 and the EEPROM 7601 located on the Familyboard. It also communicates with the TV Signal Processor 7402 and Deflection Processor7404 located on the Deflection Controller board.

The Hercules Processor communicates with the ATSC module via the A through E controllines. Line E is the Data transmit line. Line D is the Data receive line from the ATSC module.Line C is the Bus Request line. Line B gives the ATSC module the command to turn Onwhen the set is switched On. Line A sends a reset command to the ATSC module when theset is turned On.

Page 35

FIGURE 32 - SYSTEM CONTROLPage 36

FIGURE 33 - SERVICE ALIGNMENT MODEService Alignment Mode SAM (Figure 33)

Making changes in the settings requires entering the SAM. To enter SAM, press 0 6 2 5 9 6Info on the remote control. Use the cursor-up and cursor-down buttons to highlight a selec-tion. Press the cursor-right, cursor-left buttons, or enter a value to make changes.

Customer Service mode CSM (Figure 34)

To enter the Customer Service Mode, press 1 2 3 6 5 4 on the remote control. This allowsthe customer to read settings after being directed to this mode by service personal. Nochanges can be made in this mode. The screen show is with the set in the Digital Mode. To

Page 37FIGURE 34 - CUSTOMER SERVICE MODE - DIGITAL

view the Analog settings, place the set in the Analog mode by pressing the D/A button on theremote and then re-entering the Customer Service Mode. (Figure 35) Refer to the Servicemanual for an explanation of the CSM and SAM settings.

Page 38

FIGURE 35 - CUSTOMER SERVICE MODE - ANALOG

SDM (Service Default Mode)

The Service Default Model allows the Error Codes, Operation Hours, and Software versionto be read if the OSD is working. The SDM can be entered by pressing 0 6 2 5 9 6 Menu onthe remote control.

If the picture is not present, error codes can be read by shorting the SDM Jumper to ground.Remove power from the set and short the SDM jumper, 9252, to ground. Reapply powerand turn the set On. After a short period of time, the Power LED will blink to indicate theerrors. The LED will blink the number of times for the first error. The LED will then pauseand then blink the number of times for the second error, etc.

If a critical error exist, the Power LED will blink when the set is turned On for the number oftimes for the error.

Abbreviation list

Description

1080i 1080 visible lines, interlaced1080p 1080 visible lines, progressive scan480i 480 visible lines, interlaced480p 480 visible lines, progressive scanADC A/D Analogue to Digital ConverterAFC Automatic Frequency Control: control signal used to tune to the correct

frequencyAGC Automatic Gain Control: algorithm that controls the video input of the

feature boxAM Amplitude ModulationAV Audio VideoC-FRONT Chrominance front inputCBA Circuit Board Assembly (or PWB)ComPair Computer aided rePairCSM Customer Service ModeCVBS Composite Video Blanking and SynchronizationCVBS-EXT CVBS signal from external source (VCR, VCD, etc.)CVBS-INT CVBS signal from TunerCVBS-MON CVBS monitor signalCVBS-TER-OUT CVBS terrestrial outDAC Digital to Analogue ConverterDFU Directions For Use: owner's manualDNR Dynamic Noise ReductionDRAM Dynamic RAMDSP Digital Signal ProcessingDTS Digital Theatre SoundDVD Digital Video DiscEEPROM Electrically Erasable and Programmable Read Only MemoryEPLD Electronic Programmable DeviceEXT EXTernal (source), entering the set by cinches (jacks)FBL Fast Blanking: DC signal accompanying RGB signalsFLASH FLASH memoryFM Field Memory / Frequency ModulationFMR FM RadioFRC Frame Rate ConverterFRONT-C Front input chrominance (SVHS)FRONT-DETECT Front input detectionFRONT-Y_CVBS Front input luminance or CVBS (SVHS)H H_sync to the module HD High DefinitionHDMI High Definition Multimedia Interface HP HeadPhoneI2C Integrated IC busI2S Integrated IC Sound bus

Page 39

IC Integrated CircuitIF Intermediate FrequencyInterlaced Scan mode where two fields are used to form one frame. Each field contains

half the number of the total amount of lines. The fields are written in 'pairs', causing line flicker.

IR Infra RedIRQ Interrupt ReQuestLast Status The settings last chosen by the customer and read and stored in RAM or in the

NVM. They are called at start-up of the set to configure it according the cus-tomers wishes

LCD Liquid Crystal DisplayLED Light Emitting DiodeLINE-DRIVE Line drive signalLVDS Low Voltage Differential Signalling, data transmission system for high speed

and low EMI communication.MPEG Motion Pictures Experts GroupNVM Non Volatile Memory: IC containing TV related data (for example, options)OSD On Screen DisplayProgressive Scan Scan mode where all scan lines are displayed in one frame at the same

time, creating a double vertical resolution.RAM Random Access MemoryRC Remote Control transmitterRC5 Remote Control system 5, the signal from the remote control receiver RGB Red, Green, and Blue. The primary colour signals for TV. By mixing

levels of R, G, and B, all colors (Y/C) are reproduced.RGBHV Red, Green, Blue, Horizontal sync, and Vertical syncROM Read Only MemorySAM Service Alignment ModeSIF Sound Intermediate FrequencySC SandCastle: two-level pulse derived from sync signalsSCL CLock Signal on I2C busSDA DAta Signal on I2C busSDRAM Synchronous DRAMSIF Sound Intermediate FrequencySTBY STandBYVGA Video Graphics ArrayXTAL Quartz crystalYPbPr Component video (Y= Luminance, Pb/Pr= Colour difference signals)Y/C Luminance (Y) and Chrominance (C) signalY-OUT Luminance-signal

Page 40

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