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Philips DVDR75
Technical Training Manual
Philips Service and Quality/TrainingOne Philips DriveKnoxville, TN 37914-1810P. O. Box 14810PH: 865-521-4397FAX: 865-521-4818EMAIL: [email protected]
Introduction
This manual is intended for use by the ServiceTechnician. There are two versions of theDVDR75. The first four digits of the ProductNumber indicates the version. The ProductNumber is similar to a Serial Number. It will readVN02 or VN04. The VN04 is the newer of thetwo. The VN04 uses an updated Digital Boardthat contains the functionality of the DVIO Board.When there are two versions of a circuit, the titleto the section will have one or the other in thetitle, VN02 or VN04.
The first portion of this manual contains a basicdescription of disc based data playback andrecording technologies. Self Diagnostics areincluded to aid in troubleshooting. TechnicalDescriptions of the circuitry are followed by aTroubleshooting Section.
The DVDR75 is the forth generation in a line ofDVD recorders. Recordings can be made frombroadcast transmissions, and from other analogor digital sources. The DVDRW format allowsthe user to record and erase a disc manytimes. The recorded discs will play on mostexisting and future DVD players. The DVDR75has a connection for DV or Digital camcordersvia an I-Link or Firewire connection. This con-nection technically is called an IEEE 1394 con-nection. This machine records on 4.7GbyteDVD+R and DVD+RW discs. This machineuses a real-time MPEG2 Variable Bit Rate,VBR, Video encoder. The DVDR75 plays backDVD Video, Video CD, Audio CD, CD-R, andCD-RW discs.
Its many features include: Favorite SceneSelection for easy editing, Index Picture Screenfor instant overview of contents, Digital TimeBase Corrector, Digital Audio output (DTS, AC-3, MPEG, PCM), TruSurround for 3D sound,Zoom + Perfect Still. It is Widescreen, 16:9compatible, and has a Universal RemoteControl, 20 disc resume, Disc Lock, and OneTouch Recording.
Virgin Mode
The DVDR75, when first hooked up, needs toget information from the user about what lan-guage and what local broadcast system the unitis going to operate with. Use the remote to makethose selections. The unit will not operate untilthis process is completed. If you want therecorder to start up in Virgin mode, unplug therecorder. Plug the recorder in again while hold-ing the STANDBY-ON button.
DVD Basics
Philips with nine other manufacturers chose aformat specification for DVDR and RW on March16, 2001. This format uses Real Time recording.Its recording is compatible with DVD-Video, andDVD ROM. The data blocks use lossless linking.The physical layout matches very closely to thatof a DVD ROM. See Figure 1. It also usesDirect Overwrite when a RW disc is used.
Figure 1 – DVD ROM Disc1
Laser Technology
The DVD and CD share much of their technolo-gy. We will start with CDs and work our way tothe DVD. CDs use a red laser created by adiode and lens system often called a Light Pen.Refer to Figure 2. The narrow beam of light isfocused onto the reflective layer of a disc. At theinstant that focus is achieved, the disc is spun.The laser starts on the innermost tracks of theCD and reads outward. At the beginning of thedisc is the Table of Contents. At the bottom ofthe Light Pen are Monitoring Diodes. TheMonitoring Diodes provide information aboutfocus and tracking. Data is retrieved from thedisc in the form of pulses of light reflecting fromthe disc. The pulses are created by Pits in theReflective Layer of the disc. The Pits reflect lesslight than the intact surface of the ReflectiveLayer, called Lands. The data is binary. A 1 isgenerated when the light transitions from brightto dim and dim to bright. The time between is aseries of zeros determined by the data rate.
Disc Mechanical Layout
The CD is a plastic disc 120mm in diameter, witha thickness of 1.2mm. Refer to Figure 3. It hasa silver colored Reflective Layer. The maximumplaying time for a music recording on a CompactDisc, CD, is 74 Min.
Figure 2 – CD Laser Operation
2Figure 3 - CD Disc
The CD is less vulnerable to damage than ananalog record. That does not mean it does nothave to be treated with care. Dirt and heavyscratches can interfere with playability.
As shown in Figure 4, the CD is subdivided intothree parts: the Lead In Track, the ProgramArea, and the Lead Out Area. These three sec-tions together are considered the InformationArea. There is a hole in the center for holdingthe disc. The disc is held between two equallysized concentric rings. The rings have an innerdiameter of 29mm and an outer diameter of31mm.
The Data on the disc is recorded on a spiralshaped track with pits and lands. The reflectiveside of the disc contains the tracks.
The production of a disc is a high tech processexplained in Figure 5. The process starts withglass that is photo etched. The glass is silverplated and is used as a form for a metal cast.The metal cast is used to stamp a nickel MotherStencil. The Mother Stencil is used to stamp theSon Stencil. Son Stencils are used to stamp thefoil of the discs. A protective layer and label areadded.
Figure 4 - The Disc
Figure 5 - Creating a CD3
Read ProcessThe Servo circuit is responsible for focusing thelaser and moving the Light Pen to follow the spi-raling tracks on the rotating disc. The digital HighFrequency information, HF, is demodulated andstored in RAM. When the RAM is half full, thedata is fed out to the Digital to Analog Converters.
The speed of the rotating disc is servo controlledto keep the RAM half full. The analog signals areamplified and sent to the output connectors.
Record Once Technology
Disc Mechanical Layout From an external point of view, a DVD is thesame as the CD. Recordable media creates theneed for three physical layouts. There are threepossible states of a disc: a blank disc, a partiallyrecorded disc, and a full or finalized disc. Thedifference is in the way the Information Area isdivided. The Information Area of a blank discextends from 22.35 mm centered on the disc to59 mm centered on the disc. Refer to Figure 6. A partially recorded disc’s Information Area has
four sections: a PCA/RMA area, a Lead In Area,a Recorded Program Area, and a RecordableProgram Area. See Figure 6 for the dimensions.The PCA Area is the Power Calibration Area,PCA. The RMA Area is the RecordingManagement Area. A fully recorded or finalizeddisc’s Information Area has three sections: A
lead in Area, the Program Area, and the LeadOut Area. See Figure 7 for the dimensions.
The disc’s recordable layer contains major differ-ences from that of a stamped disc. The blankdisc has a Pre-groove stamped into the record-able layer of the disc. This is polycarbonant forDVD+Rs and organic dye material forDVD+RWs. This spiral Pre-groove is for theServo circuit to provide a mechanical reference during recording. The dye based RW recordablelayer provides a reflectivity of 40% light returnand 70% light return. 40 percent reflectivity rep-resents Pits and the 70% represent the Lands.
Record ProcessThe record process shares most of its mechani-
Figure 6 – A Partially Recorded Disc.
Figure 7 – Fully Recorded or Finalized Disc4
cal operation with that of the play process. Themain difference is how the Servo is locked to thedisc. The Servo follows the Pre-groove for RadialTracking and disc speed. The speed of the discis locked to a wobble signal that is part of thespiral grove stamped into the disc.
The intensity of the laser beam is modulatedfrom playback intensity to write intensity. As thedisc reads the Pre-groove, the laser arrives at aposition where a Pit is to be formed. The laserpower increases from 4mW to 11mW. This raisesthe temperature of the disc to 250 degreesCelsius. The recordable layer melts, reducing itsvolume. The polycarbonate flows into the spacevacated by the dye. The modulation from readlaser power to write laser power forms a pit andland pattern effectively the same as a prerecord-ed disc.
Re-recordable Technology
Disc Mechanical LayoutDisc usage mechanically is identical to therecordable media. The only difference is thechemical make up of the recordable layer. Therecordable layer is made up of an alloy of silver,indium, antimony and tellurium.
Re-Recording Process
The Re-Record process shares much of its oper-ation with that of a CDR. The blank disc’s
Information Area is in a polycrystalline state.During recording, the laser power is modulatedfrom 8mW to 14mW. 8mW is the playback laserpower and 14mW is the record laser power. Thepolycrystalline state of the recordable surfacechanges, or melts at 500-700 degrees C into anamorphous state. The melted, amorphous areasreflect light less than the crystalline areas, creat-ing a pattern similar to the stamped CD. A majordifference of CDRWs from CDRs is the ability toerase.
The Erase ProcessTo Erase a CDRW disc, the recordable layermust be returned to its polycrystalline state. Thisis done by heating up the temperature of therecorded surface to 200 degrees C. This is lessthan the melting point. This is done at X2 record-ing speed. The slower speed allows time for thealloy to return to its proper state. This takesapproximately 37 min. Some software erases thejust the TOC on the disc and allows the disc tobe rewritten. This method is not as reliable
Over Writing ProcessOver writing combines the processes of erasingand writing. When the disc and Light Pen are inposition to start writing the new data, the laserpower starts modulating in the same manner asit does for normal recording with one difference.During the time there is to be a land, the laserpower goes to the erase level rather than theplayback level.
Figure 8 – Mechanical Layout of a DVD5
DVDsAll of the previously discussed technologiesapply to the DVD. Like CDs, DVDs are alsostamped into play only discs. In this discussion,we will point out the differences between DVDsand CDs. If you are new to disc based technolo-gy, you will want to start with the information pre-ceding this discussion.
DVD Disc Mechanical Differences
Most DVDs are single sided, however, the DVDspecification allows for two readable layers, andthe disc can be double sided. We will start ourdiscussion with single sided, single layereddiscs. A Digital Versatile Disc, DVD, looks verysimilar to a CD. Refer to Figure 8. The ClampingArea is larger, starting at 11 mm centered to 16.5
mm centered. The Lead In Area is smaller,measuring 22.7 mm centered to 24 mm cen-tered. The Information Area is limited to 116mmcentered.
Two of the big differences between DVDs andCDs are the Pit and Land sizes, and the trackwidths. Refer to Figure 9.
The Manufacturing process of a DVD is compa-rable to that of a CD. The main difference is thethickness. The DVD can be a double sided prod-uct. Each side is .6mm. The two sides are gluedback to back, producing 1.2mm total thickness.
Figure 8 - DVD Mechanical Layout
Figure 9 – DVD and CD Pit Structure.
CDDVD
6
WobbleA Pre-groove is stamped on writable discs. All recordable DVD media types feature a micro-scopic wobble groove embedded in the plasticsubstrate. This wobble provides the recorderwith the timing information needed to place thedata accurately on the disc. During recording,the drive's laser follows this groove, to ensureconsistent spacing of data in a spiral track. Thewalls of the groove are modulated in a consistentsinusoidal pattern so that a drive can read andcompare it to an oscillator for precise rotation ofthe disc. This modulated pattern is called a wob-ble groove because the walls of the grooveappear to wobble from side to side. This signal isonly used during recording, and therefore has noeffect on the playback process. Among the DVDfamily of formats, only recordable media usewobble grooves.
Dual Layer DiscsTwo information layers are separated by a thintransparent layer. Refer to Figure 11. The firstlayer is partially transparent. This allows the sec-ond layer to be read through the first layer. Bothlayers are read by controlling the focus. Thereare two methods for reading the data of a DualLayer disc, PTP and OTP. Refer to Figure 12.
PTP is Parallel Track Path. That means the LeadIn and Out Areas of the two layers correspond toeach other. Each Lead In Area is on the innerportion of the disc, and the Lead Out Area is onthe outer portion of the disc. This is useful to linkdata between the layers.
This allows instant access to the additional dataor scene. OTP is Opposite Track Path. Thismethod links the end of one layer to the begin-ning of the other. The Lead In Area is still on the
Figure 11 – Dual Layer DVD7
Figure 10 - Wobble Pregroove
inner portion of the disc. There is a Middle TrackArea on both of the layers located on the outerportion of the layers. The Middle Track Area linksthe data on the two layers together. The LeadOut Area is on the second layer on the inner por-tion of the disc.
CapacityBecause a stamped DVD can be Dual Layeredand Double Sided, there are four different capac-ities. Refer to Figure 13. These capacities strict-
ly pertain to raw data. The time available forVideo and Audio has many extra factors thatdetermine the length of time on each side orlayer. The picture complexity and the amount ofmovement in the picture affect compression andtime on a disc. The number of languages affectthe time on a disc. The type and quality of theAudio has an affect on the time also. It can bemono, stereo, or AC-3. Therefore, the mediaitself determines the capacity in time on the disc.
Figure 13 – DVD Multi-Layered Capacities8
Figure 12 – PTP and OTP Layout
Description
The VN02 products have this feature. The EndUser/Dealer Self Diagnostics work without theneed for other equipment. A number of hardwaretests are automatically executed to check forfaults in the recorder. The final test, number one,routes video to the Composite Out jack. The sig-nal is a Pal Color bar signal. Most televisions willshow the bars in B+W. This is dependent on thepull in range of the monitor, as the frequenciesare shifted as compared to NTSC. The diagnosisends with a “FAIL” or “PASS” message.
If the message “FAIL” appears on the display, anError Code is displayed. If the message “PASS”appears, the tests have been executed success-fully. There can still be a failure in the recorder.
The tests do not cover the complete unit. Thefollowing list describes the tests being performedwhile the test number is being displayed on theFront Panel.
To place the unit in the Self Test Mode, hold thePlay pushbutton on the Front Panel while sup-pling AC power to the unit. The word BUSYappears on the display followed by test number.The display counts down numerically to test if itis performing.
The following is a list of the tests.
“Test Number” is displayed on the Front Panel“Name” of the testDescription of the test
22SdramWrRChecks all memory locations of the 4MbyteSDRAM
21HostdDramWrRChecks all the DRAM connected to the micro-computer on the Digital Board
20HostdI2cNvram
Checks the data line (SDA) and the clock line(SCL) of the I2C bus between the host decoderand NVRAM
19SAA7118I2cChecks the interface between the Host I2C con-troller and the SAA7118 Video Input Processor
18VideoEncI2cChecks the interface between the host I2C con-troller and Empress
17AudioEncI2cChecks the I2C connection between the hostdecoder and Empress
16AudioEncAccessTests the HIO8 interface lines between the hostdecoder and the audio encoder
15AudioEncSramAccessChecks the access of the SRAM by the audioencoder (address and data lines).
14AudioEncSramWrRTests the SRAM connected to the audio encoder
13AudioEncInterruptTests the interrupt line between the host decoderand the audio encoder
12VsmAccessChecks whether the VSM interrupt controllersand DRAM are accessible
11VsmInterruptChecks both interrupt lines between the VSMand the host decoder
9
User Self Diagnostics (VN02)
10VsmSdramWrRTests the entire SDRAM of the VSM
9Clock11.289MHzSwitches the A_CLK of the micro clock to11.2896 MHz
8Clock12.288MHzSwitches the A_CLK of the micro clock to 12.288MHz
7BeS2BengineChecks the S2B interface with the Basic Engineby sending an echo command
6DisplayEchoChecks the interface between the host processorand the slave processor on the display board
5AnalogEchoChecks the interface between the host processorand the microprocessor on the Analog Board
4AnalogNvramChecks the NVRAM on the Analog Board
3TunerChecks whether the Tuner on the Analog Boardis accessible
2LoopAudioUserDealerTests the components in the audio signal path:The host decoder on the Analog Board, theaudio encoder, the VSM. The Audio is internallylooped back thru the Digital Board
1LoopVideoUserDealerTests the components on the Video signal sys-tem path: - The VIP- The Video encoder- TheVSM- The host decoder. The Analog Board OnVideo signal is internally routed back to theDigital Board.
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The User Self diagnostics in the VN04 productare very different than the VN02 product. It has adifferent Digital Board.
Press Play and apply AC power. The display willflash quickly through a more technical display ofthe Nucleus (test) it is performing. If an error isfound, the Nucleus Code and an Error Code willbe displayed. Use the Service Manual to look upthe code.
User Self Diagnostics (VN04)
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Description
The VN02 products have this feature. TheManual Diagnostics provide the opportunity toperform tests and exercise the unit in a way thathelps determine which of the DVD recorder’s cir-cuit boards are faulty. If no Errors are found, itperforms an endurance loop test.
To successfully perform the tests, the DVDrecorder must be connected to a monitor via thevideo out. The Servicer must respond to what isseen and heard on the monitor. (i.e. to approve atest picture or a test sound). Some tests requirethat a DVD+RW disc be inserted.
Structure of the Player ScriptThe player script (Manual Diagnostics) tests thecircuit boards in the DVD recorder: the DisplayPCB, the Digital PCB, the Analog In/Out PCBand the Basic Engine.
The Player tests are done in two phases, inter-active tests and a burn in test. The interactivetests depend strongly on user interaction andinput to determine the results and to progressthrough the full test. The Burn-in Loop test willperform the same set of tests as the dealer test,but it will loop through the list indefinitely. Is isespecially useful if you reset the Error Log. Youcan do this using ComPair. You can then readthe error codes using ComPair.
Step by Step Description
1Press OPEN/CLOSE and PLAY buttons at thesame time and provide AC to the recorder tostart the player script. Press Play to perform thetest described on the display. Press Stop to skipthe test and go to the next test. Press Record toindicate to the Microcomputer the desired resultmalfunctioned.
2The display shows FP SEGM. Press PLAY tostart the test. First the starburst pattern is lit.Press Play each time to advance. Then the hori-zontal segments are lit, followed by the verticalsegments and the last test lights all the seg-ments. After each of the four tests, the user hasto confirm that the correct pattern was lit.Pressing PLAY confirms the correct pattern waslit. Pressing RECORD indicates that the correctpattern was not successfully lit. Press STOP toskip this or any test.
3The display shows FPLABELS. Press PLAY toadvance. All labels should be lit.
4The display shows FPLIGHT ALL. Press PLAYto advance. Everything should be lit.
5The display shows FP LED. Press PLAY toadvance. The red Record light comes on. PressPLAY to confirm it lit. Press STOP to skip thistest.
6The display shows FP KEYBRD. All keys haveto be pressed to get a positive result! Thisincludes the Power button. Press PLAY for morethan two seconds to confirm that all the keyswere pressed and that it was shown on the dis-play. Press STOP for more than one second toskip this test.
7The display shows FP REMCTL. Press PLAY toconfirm that a key on the remote control waspressed and shown on the local display. Onlyone key has to be pressed to get a successfulresult.
Manual Diagnostics VN02
8The display shows FPDIMMER. Press PLAY toactivate the dimming feature. Press Play to con-firm that the text on the local display wasdimmed.
9The display shows ROUTE VID. Press PLAY toadvance.
10The display shows ROUTE AUD. Press PLAY toadvance.
11The display shows COLORBAR ON.Press PLAYto advance. An NTSC Colorbar Pattern shouldappear at the output. Press PLAY to advance.
12The display shows PINKNOISE ON. The monitorshould produce Pink noise.
13The display shows PINKNOISE OFF. PressPLAY to advance.
14The display shows BE RESET. Press PLAY toReset the Basic Engine (Mechanism/ServoPCB).
15 The display shows BE TRAY OPEN. PressPLAY to open the tray. Place a RW disc in thetray.
16The display shows BE TRAY CLOS. PressPLAY to close the tray.
17The display shows BE WRITE READ. Thisrequires a RW disc to be in the machine. The BEresets and a small write is preformed, and then aread. This will take 20 seconds or so.
18The display shows BE TRAY OPEN. This opensthe tray.
19The display shows BE TRAY CLOS. This closesthe tray.
20The display shows ERRORLOG READ. If therewas an error, a code will be displayed. If youpress PLAY, the diagnostic script will start anendless loop. If the unit fails a test, the local dis-play will display FAIL and the error code.
In case of a failure, the display shows “ FAILXXXXXX “The description of the shown errorcode should be found in the list in the ServiceManual. Once an error occurs, press the STOPkey to jump over the failure and to continue thediagnostics.
There is a Error Code Table in Force Manual2064.
VN04 product does not haveManual Diagnostics.
If you try to place the unit in diagnostic mode inthe same manner as the VN02 product, there isno display and the unit is locked.
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Overall Block
Key Components
The unit is made up of: the Power Supply/AnalogBoard, the Front Panel, the Basic Engine, theDigital Board, and the Digital Video Input/OutputBoard. Refer to Figure 14. The DVIO board’scircuitry is contained on the Digital Board of theVN04 product.
Block Diagram Descriptions
Power SupplyThe Power Supply is a SMPS using Hot Groundon the primary side of the transformer. There isno MAINS power switch. It is operating when ACis applied. It supplies power to: the AnalogBoard, the Digital Board, the Basic Engine, andthe Front Panel..
Front Panel DisplayThis module contains a microcomputer that dou-bles as a fluorescent display driver. It receivesthe IR inputs and the keyboard inputs. It commu-nicates the user input from the Keyboard and IRReceiver via the I2C Bus to the Microcomputeron the Analog Board.
Basic Engine (BE)This consists of the Mechanism and Servo con-trol PCB. The Mechanism is essentially the sameas a DVD with the exception of the OpticalPickup Unit, OPU. The OPU has a dual directionsignal and light path, one for the write signal andone for the play signal. The OPU has three ICsmounted on it for processing laser signals.These include: the Laser Drive IC or LADIC, theDvd Recordable Optical Preprocessor IC orDROPPI, and the Non-Volatile RAM or NVRAMto store its electro-mechanical settings.
The Servo controls the Mechanism. It handlesthe HF signal to and from the OPU. It uses aMicrocomputer to control all aspects of the Servooperation. This includes: tray operation, spindlespeed, focus, HF preprocessing, and radial posi-tioning of the OPU.
Digital PCB
This module performs many functions. It inter-faces between the Basic Engine and the rest ofthe unit. There are two Digital Boards in theDVDR75. The Product Number is different signi-fying which Digital Board is in the unit. The onedescribed here is the VN02 product. The func-tionality and connections are the same. TheVN04 product contains the DVIO circuitry, and adifferent chipset. A separate block diagram fol-lows the Digital Board’s Circuit Description.
During record, it encodes analog video and digi-tal audio into a recordable digital data stream.The Analog to Digital Converter for video is partof a Video Input Processor, VIP, that supplies theMPEG2 Encoder. The VIP sends parallel digitalvideo to the EMPRESS and the VSM. TheEmpress is the MPEG2 Encoder. It receivesvideo from the VIP and audio from the AnalogBoard. The Audio is A/D converted on the AnalogBoard. The EMPRESS is a microcomputer. Ithas its own SDRAM. It supplies MPEG2 data tothe VSM, Versatile Stream Manager. Using syncfrom the Digital Video coming from the VIP, theVSM converts the signal into an I squared S seri-al signal. The serial data is sent to the BE to berecorded on the disc.
During playback, the MPEG2 Decoder receivesits I squared S input directly from the BE. Itdecodes the data stream into analog Video anddigital Audio. Both are sent to the Analog Board.Digital Video is provided to the Line Doubler. TheLine Doubler receives 11 bit digital YUV. TheLine Doubler produces progressive scan digitalY/U/V that goes to the Digital to Analog Encoder.Y, Pr, and Pb are sent to the Analog Board.
The Host Decoder is the Master of the I squaredC bus that provides communication between theMicrocomputers: Empress, VIP and the LineDoubler. The VSM Communicates to the SystemControl Microcomputer Via UART1. UART2 pro-vides communication between the Digital Boardand the DVIO Board. EMI uses Flash memory toprovide the Boot up sequence and the opera-tional firmware. Updates can be loaded to
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Figure 14 – O14
Overall Block
enhance operation of the unit. At present, theupdate disc is version 6.1.
Analog PCBThis module contains: the Power Supply, theSystem Control Microcomputer, all the A/V inputsand outputs including a Tuner/RF Modulator.Source selection and output type are controlledby the microcomputer. The microcomputer con-trols many functions throughout the unit includ-ing: Power up, user input, input/output selection,the Tuner, the D/A, and A/D functions of theAudio. It also controls the Fans.
Input selection is an important function per-formed by the analog board. The user selectsbetween: External 1 and 2, DVIO, Tuner Video,and Front Panel jacks.
Audio processing is performed on the AnalogBoard. The Audio signal coming from the Tunerhas a separate demodulator. The Multi SystemProcessor, MSP, demodulates the audio andsends the signal to the Routing Switch. The MSPselects between Tuner Audio and the DVIOAudio signals. The selected audio is sent to theA to D Converter. Digital Audio is supplied to theDigital Board for recording.
DVIO PCBThe Digital Video Input Module provides IEEE1394 translation to the DVD recorder. It sepa-rates the Digital Video and Audio. The DigitalAudio is decoded and sent as Analog Audio tothe Analog Board. Digital Video (DV) is suppliedto the Video Input Processor on the DigitalBoard. The DVIO board communicates with theDigital board via UART2.
Power Supply
This unit uses a Switch Mode Power Supply,SMPS. It operates whenever ac is applied. AMOSFET transistor turns On and Off in an oscil-lator fashion, driving a transformer. The primaryhalf of the supply uses a Hot Ground. The prima-ry side of the circuit provides drive and coarsecontrol of the power supply. The secondary sideof the circuit rectifies and filters the output of thetransformer to produce many output voltages. Ituses a cold ground, signal ground system. Theoutput is monitored for precise regulation. The5Vdc is supplied to the anode of the OpticCoupler’s diode and fed to the Shunt Regulator.The regulation path includes an Optic Coupler toaccommodate the different grounding systems.
Circuit Description
AC Input CircuitThe AC input is rectified by diodes 6301, 6302,6305, 6306, and filtered by C2309. Refer toFigure 15. The voltage on C2309 is approxi-mately 155V. It can vary from 150V to 160V,depending on the AC input voltage.
Start CircuitThe start up of this power supply is mostly con-tained in IC7313. The Drain supply voltage goesto Pin 8 of the IC. The running supply for the ICis Pin 1 of the IC. The Supply Control provides ameasured supply to the VCO and the Driver forstart up. The power supplied is not enough tokeep the unit operating. If the supply does notoperate and supply Pin 1 with operating power,the unit stalls.
When the power plug is connected to AC, theMOSFET 7307 will start conducting when thegate voltage reaches the threshold value. A cur-rent starts to flow in the primary winding of 5300,Pins 7 and 5. While the MOSFET is conducting,energy is building up in the transformer. The cur-rent flow through the MOSFET is sensed byR3352, and 3321. When the current level riseshigh enough to provide a voltage drop on thesecomponents, 7307 is turned Off by the driver cir-cuit. Diode 6311 protects the control circuit in
case of failure of the MOSFET by providing anupper-limit to the voltage that can remain on thesource of the MOSFET.
Coarse RegulationThe positive portion of the signal on Pins 2 and 3will be rectified via D6316, charging C2325. Intime, the voltage on C2340 will reach 9 to13Vdc. This value depends on the value of theMains voltage and the load. This is also used asa regulation supply for the optic coupler IC7314.
The control circuit consists of a VCO, the Driver,an Op Amp and Gate that are fed by the sensingresistors, 3352 and 3321, and C2340. This cir-cuit controls the conduction time and the switch-ing frequency of the MOSFET. It switches Off theMOSFET as soon as the voltage on the sourceof 7307 reaches a certain value.
Demagnetization or complete magnetic field col-lapse is desired before the next drive signal isapplied to the MOSFET. This improves efficiencyby reducing the power necessary to build a mag-netic field in the transformer. Pin 4 is the Demaginput. When Pin 4 is near 0Vdc, the gate isenabled, allowing the next oscillation to occur.
Secondary Rectifier/Smoothing CircuitThere are six Rectifier/Smoothing circuits on thesecondary side. Each supply voltage depends onthe number of windings in the transformer. Fromthese circuits, several voltages are derived.
Precise Regulation The 5VREG is monitored for regulation. The reg-ulation circuit consists of an Optic-Coupler, 7314,a shunt regulator, 7315, and a voltage dividernetwork. The Optic-Coupler isolates the HotGround on Pin 2 of 7313 from the Cold Groundvoltage on 7315. 7315, a Shunt Regulator, hastwo component characteristics. It is a very stableand accurate reference diode and a high gainamplifier.
7315 will conduct from cathode to anode whenthe 5VREG is rises higher than the 5Vdc. The5VREG is divided down to a 2.5V reference volt-age. If the 5VREG and subsequently the refer-ence voltage is lower, the cathode current is
almost zero. The cathode current flows throughthe LED of the Optic-Coupler, controlling the cur-rent through the transistor portion of the Optic-Coupler. The collector current of 7314 will adjustthe feedback level of the error voltage at Pin 3 of7313.
There are standby and switched supplies. The5VSTBY, 12VSTBY, 5NSTBY, 33VSTBY and theVGNSTBY supplies are always present when ACis supplied. The VGNSTBY supply ia a -33Vdcdedicated to the Front Panel Fluorescent Tubeas a grid supply. The 5SW, 8SW, 12V, 5V, and3V3 supplies are switched.
The STBY control voltage switches On the 5SWand the 8SW. As part of the first layer of PowerUp, the System Control Microcomputer pulls theSTBY line Low. This removes bias to 7308 and7321. This allows the standby supplies to bias7319 and 7320 On. These supplies go to the RFUnit, the Sound IF and the Input Matrix.
The ION control voltage turns the unit On andOff. When the user turns the power On, the IONcontrol voltage goes Low, turning 7306 Off. The33VSTBY supply is allowed to turn On 7318.The switched 12V becomes available. TheSwitched 12V switches On the 3V3 and theswitched 5V supplies. The 3V3 and 5V suppliesare regulated by shunt regulators, controllingMOSFETs.
Overcurrent Protection CircuitWhen the output is shorted, the current throughthe FET will produce a large voltage drop acrossthe source resistors of the FET. When Pin 5 iselevated, the Op amp’s output is low, disablingthe output of the Driver. This switches Off thedrain current of the MOSFET, 7307. The start cir-cuit will try to start up the power supply again. Ifthe short still exists, the complete start and stopsequence will repeat. The power supply is in ahiccup mode and is ticking.
Overvoltage Protection CircuitIf the regulation circuit does not function due toan error in the control loop, the regulated outputvoltage will increase. This overvoltage is sensed
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Figu
re 1
5 - P
ower
Sup
ply
Circ
uit
on the hot ground side of the transformer at Pins2 and 3. When an overvoltage is detected, theDemag circuit will activate the inverter. Thepower supply will be shutdown until the voltagereturns to zero. it will then try to restart.
The IPFAIL signal is used as a Power Fail mea-surement signal. During normal operation, 7310is biased On by 6315 and 6312. When power isinterrupted that Bias is removed prior to the Filtercapacitors draining off their charge. 7310 turnsOff, allowing the 5VSTBY to turn On 7311. TheIPFAIL goes low. This signal goes to the SystemControl Microcomputer and Mute circuits.
Microcomputer
The Microcomputer, IC7804, is a 16-bit processorwith internal ROM and 4kB RAM. It uses ExternalRAM, IC 7803, and Flash, IC 7805. It is mountedon a Sub Board soldered into the Analog Board.Refer to Figure 16. The System Clock operates at24MHz. It uses an I2C interface to communicatewith the other Microcomputers in the unit. Theclock rate is approximately 95kHz. The Reset Pinis high during normal operation. The microcom-puter uses non-volatile EEPROM, 7805. TheEEPROM stores data specific to the device, suchas the AFC-reference value, clock-correction-fac-tor, etc.
Power up
7804 controls power up of the unit. There arethree layers to the power up sequence. The firstlayer involves the Analog Board and the FrontPanel. The second layer involves the DigitalBoard and the BE. The third involves the FrontPanel and the Analog Board.
The first layer controls the first set of switchedsupplies. After the System Control Micro-computer receives its reset, the STBY controlvoltage goes Low to turn On the first set ofswitched supplies, the 5SW and the 8SW. Itcommunicates on the I2C bus initializing the RFUnit, the Sound IF, and the Input Matrix ICs. Ifthey respond properly, it then communicates on
the I2C to the Front Panel Microcomputer. If theFront Panel Microcomputer responds properly,the ION control voltage goes Low.
The second layer occurs when the ION switchingvoltage goes Low. It comes from the SystemControl Microcomputer. The ION control voltagepasses through the Digital Board to the PowerSupply and turns On a second set of switchedvoltages. These include the 3.3Vdc supply. The3.3Vdc supply is the main B+ to many of themicrocomputers throughout the unit. The SystemControl Microcomputer then sends out theIReset signal to 7902 on the Digital Board. ThisIC produces a delayed Resetn signal line for7200. 7200 activates its I2C and provides sever-al reset and initialization signals for the DigitalBoard, DVIO, and the BE. They all go through aself test. If the self test succeeds, the VSM com-municates through UART1 that the system is op-erating, and the unit can enable the Front Panelto accept a response. The Front Panel Micro-computer then places four dashes on the FrontPanel Display. ION goes High placing the unit inStandby, waiting for keyboard input. This normal-ly takes 6-8 seconds. The System Control Micro-computer allows 10 seconds for the UART1response. If it does not come, the unit goes intosleep mode, and will not accept keyboard input.
When the Front Panel Microcomputer receives akeyboard response, it communicates that actionto the System Control Microcomputer to switchback On the second layer of switched voltages.
The System Control Microcomputer controls theoperation of the entire unit. It uses UART1 forcommunication with the Microcomputers on theDigital Board. It uses the I squared C Bus ,I2C tocommunicate with devices on the Analog Board.It receives composite sync from the Selectedvideo source. This is to determine that a goodsignal source has been selected before the unitis allowed to record.
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Front Panel
The main elements of the Front Panel are themicrocomputer, 7103, the Display Tube, and thekeyboard. Refer to Figure 17. 7103 is an 8-bitmicrocomputer fitted with 96kB ROM and 3kBRAM and is responsible for the following func-tions:
Fluorescent Display driver
Monitoring the keyboard matrix
Communicating with the System Control Microcomputer
Decoding the remote control commands from the infrared receiver, 7107.
Activation of the display
The Fluorescent Tube operates using a grid andsegment scanning matrix. AC is supplied by aswitching regulator consisting of 7106, 7108, and7109. A squarewave is produced by theMicrocomputer on Pin 19. The Signal is amplifiedby 7109 and supplied to the Push/Pull outputAmp.The signal passes through 5104 going tothe tube. With AC supplied, the microcomputerscans the elements in the tube to determinewhat segments light up. The system clock isgenerated with the 8MHz crystal, 1100.
Keyboard Matrix
There are 6 keys on the display board and 1 onthe Standby board. A resistor network is used togenerate a specific voltage value, depending onthe key pressed, via the resistors 3300, 3103,3104, 3106, 3108, 3110, and, 3130. This RTLdata (voltage Level) is sent to 7103 on Pins 36and 37. Pressing keys simultaneously may leadto undesired functions.
Communication with the System ControlMicrocomputer occurs on a I Squared C bus,SDA and SCL. The Front Panel receives standbysupplies, so it is always live when AC is suppled
to the set. The System Control MicrocomputerHosts the I squared C Bus. The System Controlresets and initiates the I squared C bus. TheFront Panel Microcomputer resets simultaneous-ly and communicates to the System ControlMicrocomputer that It is operating. The push but-tons and IR receiver are then monitored.
IR Receiver
The IR receiver, 7107, contains a bandpassamplifier as well as a photo-diode. The photo-diode receives approximately 940nm infraredpulses. The pulses are amplified and demodulat-ed. On the output of the IR receiver, 7107, is apulse sequence at TTL levels. The IR signalappears on Pin 20 of 7103.
The Front Panel contains a Thermal Sensor. It isa temperature coefficient resistor. As the temper-ature rises, so does the resistance. This voltageis sent to the Fan Control Circuit.
The Record LEDs are controlled by the FrontPanel Microcomputer. 7105 and 7112 are theLED drivers. Pin 3 of the microcomputer goeslow to turn on the lights. That turns On 7112which in turn turns On 7105. 7105 pulls currentthrough the diodes illuminating them.
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Analog Processor Board
The Analog Board controls all analog input/out-put selection, and routing. It houses the SystemControl Microcomputer. The System ControlMicrocomputer controls the routing and otherfunctions on the board. One of its other mainfunctions is to control power and initialization ofthe unit. It implements Keyboard instructions.The board has the Optical Audio Out and theCoax Digital Audio Output circuits. It controls theTuner. The Audio D/A and A/D conversion is per-formed on this Board. It contains the Fan Controlcircuit and houses the first Reset circuit for theSystem Control Microcomputer.
There are three circuits that can Mute the audio.The Digital Board produces the D_KILL signal.There is a power fail circuit, which is necessaryto mute AUDIO when power is lost, IPFAIL. TheSystem Control Microcomputer produces the Killsignal.
Tuner/RF Unit
The Tuner is part of and RF Unit. It contains theTuner, An RF Modulator and the Demodulator/IF.The Tuner is capable of receiving 125 channels,and is cable ready. Refer to Figure 18. The RFconnections on the back are part of the Tuner,RF Modulator. The RF Unit receives two supplyvoltages, 33Vdc and SW5Vdc. The channelselection information is communicated via theI2C lines. The output channel is selected byCSW_SSW control voltage. Video is output fromPin 24. 7700 buffers the signal before it goes toInput Matrix. The RF Unit does not performaudio demodulation. The audio signal leaves theRF Unit as Sound IF, from Pin 15 of the RF Unit.The Digital Board’s output video, D_CVBS goesto the RF Unit for the RF Modulator to output thesignal on channel 3 or 4. The audio signalreturns to the RF Unit on Pin 2 to be used by theRF Modulator. The AFT signal comes from theMicrocomputer.
Audio Demodulator
The Sound Processor, 7600, demodulates theAudio. MPS means Multi System Processor. TheI2C bus controls its operation. It uses two powersupplies, the 5Vdc and the 8V Switched. IC 7600has its own oscillator on Pins 5 and 6. Amplitudeand bandwidth of the demodulated audio signalscan be determined in 7600 using the I2C bus. Itsends analog audio back to the RF Unit from Pin26. The audio coming from the Digital Board,ARDAC and ALDAC, go into the Sound IF. TheI2C bus controls what Audio is output, the TunerAudio, or the Digital Board’s output. The Audiosignal output from the MSP is available at Pins30, AFER, and 31, AFEL. 7600 controls theaudio input selection via RAS1 and RAS2switching voltages. They go to the InputSelection Switch, 7501.
7419 and 7420 perform level matching betweenthe 5V serial clock and data lines of the Tunerand Demodulator to the 3.3V levels coming fromthe Microcomputer.
Input Matrix
The A/V I/O switching is controlled by a switch-ing matrix, 7408. It is controlled via the I2C Bus. The Matrix controls what source will be suppliedto the Digital Board. There are several choices:Tuner Video, External 1(Y/Pr,Pb), External 2Video, and Front Video. In addition there are 2Y/C inputs. All switches have 6 dB amplificationon the outputs. The Matrix is not responsible forhandling the Y/Pr,Pb. It goes directly to theDigital Board when present.
The user selects what source is to sent to theDigital Board on Pin 9 of 1947. The I2C Buscommunicates this data to the Matrix IC. Theselected source comes out Pin 21 of 7408. TheMatrix communicates channel selection controlfor the RF Unit on Pin 44.
The unit can receive a 16 by 9 input using theY/C inputs. The Microcomputer must detect thisformat and communicate it to the Digital Board.
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This is done using the Chroma signal of the Y/Csignal. The DC level of the Chroma is elevated3.3V. The DC level is detected 2 places. WideScreen Rear In (WSRI), and Wide Screen FrontIn (WSFI). The unit communicates the samething to the monitor when outputting 16 by 9using Wide Screen Rear Out, WSRO.
The Audio I/O switching is controlled by 7501 viathe I2C Bus using the Sound IF and 2 controllines, RAS1 and RAS2. Analog Audio comingfrom Rear External Inputs 1,2, Tuner Audio, andFront In are suppled to IC7501. 7501 selects theaudio source to be sent to the A to D Converter. The A/D Converter uses the A_PCM_CLK togenerate the Digital Audio signal sent to theDIgital Board a A_DAT on Pin 5 of 1900.
During playback and Powered On Standby, theDigital Board sends back to the Analog Boardthe same format of Audio as it received. This
goes to the D to A Converter, 7001. The D/Aconverts the signals back to analog left and rightaudio, ARDAC and ALDAC. These signals godirectly to the Audio Out jacks and the Sound IFIC 7600. The Sound IF selects what audio issupplied to the RF Unit.
Fan Control
The Fan Control circuit is necessary to controlthe speed of the BE Fan according to thechanges of operating temperature. The tempera-ture is measured via a Negative TemperatureCoefficient, NTC, thermistor on the Front Panel,3134. The sensor's output voltage is labeledTemp_Sense.
The Fan Control circuit uses an Op Amp toamplify the BE_FAN signal. The Microcomputercontrols the On/Off function of the fan via con-trol line FAN_OFF. FAN _OFF goes Low to turn
Figure 19 - Fan Drive Circuit
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Off the fan. When High, the Fan is turned On.7903 is biased On, removing bias to 7906 and7908. The divider resistors, 3917 and 3925 pro-vide approximately 3Vdc to the non-invertinginput to 7902-1. The inverting input receives asimilar supply via 3919 and the 10K NTC resistoron the Front Panel. When the operating temper-ature is warm enough to decrease the resistenceof the NTC, the inverting input will drop belowthe non-inverting input. The ouput of the Op Ampwill go High. this high is sent to the BE to turnOn the fan.
7902 is a saftey circuit. If the NTC were to openor be disconnected, the non-inverting input to7902 would jump to approximately 12Vdc. thiswould turn on the fan any time the SystemControl’s output FAN_OFF allowed the fan tooperate.
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Figure 20 - Digital Processor Block25
Digital Signal Processor VN02
The Digital Signal Processor has many respon-sibilities. Refer to Figure 20. It is responsible forencoding Digital Video and Audio into MPEG2and AC3 respectively. It supplies MPEG2 andAC3 via an I squared S serial protocol to theBasic Engine (BE) for recording. It also receivesthe MPEG2 Video via I2S from the BE, decodesthe signal, and supplies Digital Video to theProgressive Scan circuit. It supplies AnalogVideo to the Analog Board, and Digital Audio(I2S) to the Analog Board. The entire operationstarts with the B+ supplies and the SystemClocks.
Most of the data going to the BE passesthrough the Versatile Stream Manager, VSM.The VSM is a microcomputer, using SDRAM topreform its functions. The Empress suppliesMPEG2 Video to the VSM. The VSM combinesthe Audio and Video into one data stream. TheVSM is a hub for data streams. The VSM alsosends the Digital Video/Audio Data to berecorded back through the playback signal path.This output from the VSM is called the ParallelDigital Video path. Most of the data going to andfrom the Digital Board and the BE goes throughthe VSM. The exceptions are the Digital VideoPlayback Stream, and some control signals.The S2B signal communicates most of the con-trol signals to the BE. The Reset and Downloadcontrol signals come from the Decoder. The Isquared S playback stream goes directly to theMEG2 Host Decoder, IC7200.
The MPEG2 Decoder IC7200 contains a micro-computer. It uses SDRAM to perform its func-tions. It is the Host to the I squared C Bus, I2C.Using the I2C Bus, the Host Decoder is theSystem Control of the Digital Board. It controlsthe following IC’s: IC7100, IC7403, IC7500,IC7700, and IC7801. The I2C Bus is the majorcommunication avenue for the Digital Board. TheHost Decoder communicates to the AnalogBoard’s Microcomputer Via the VSM using the
EMI. The Decoder’s second responsibility is signalprocessing. The Decoder receives the Parallelvideo and the BE’s I2S signal. One or the otherwill be present at all times, depending onwhether the unit is in powered up Standby, Playor Record. The Decoder separates the Videoand Audio, then Demodulates the MPEG 2 videointo several outputs. It produces CompositeVideo, Y/C, and RGB to be sent to the AnalogBoard. It produces an 8-bit digital Y/UV for theProgressive Scan circuit. It produces two typesof Audio, I2S and SPDIF. They both go to theAnalog Board.
The Progressive Scan, Pscan, circuit sendsY/Pr/Pb analog, 480P, Video to the Analog Boardto be provided to the output jacks. The Pscan,circuit contains a Line Doubler and a DigitalEncoder. The Line Doubler receives the 8-bitY/UV from the Decoder. It doubles the verticalscan lines and produces separate Y, U, and V.10-bit Y, U, and V are translated into analog Y,Pr, and Pb by the Digital Encoder. The signalsare passed through Low Pass Filters to removeany switching noise left in the signals. The sig-nals are amplified before they are sent to theAnalog Board.
EMI BusThe VSM and the MPEG2 Decoder share a DataBus called the External Memory Interface, EMI. The EMI contains 4 Megabytes of FlashEEPROM. The EEPROM contains the firmware forthe Digital Board. The firmware contains the bootROM and software for the two microcomputers.
The Digital Video Input Output, DVIO, Board is asecond source of Digital Video to the MPEG2Encoder circuit. It is a 1394 IEEE compliant seri-al input device, sometimes called a Firewire or Ilink. This kind of output is commonly found onDigital Camcorders.
The Video Input Processor, VIP, receives theselected Analog Video from the Analog Boardand the DVIO Board’s output. It converts theselected signal to digital Y/UV for recording. TheDigital Y/UV is provided to the EMPRESS.
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System Clocks
The System Clocks (27MHz) of the HostDecoder, the VSM, the EMPRESS, and theProgressive Scan circuits are generated by anoscillator, 7906. Refer to Figure 21. The clocksignal is buffered and inverted by 7904, a quadinverter. These signals go to their respective cir-cuits as SYSCLK_XXXX.
The audio clock, ACC_ACLK_OSC is generatedby IC7102. During record mode, the audio clockmust be synchronized with the incoming VideoField Identifier, VIP_FID. During playback mode,the audio clock, ACC_ACLK_PLL, is generatedby the clock synthesizer, IC7900. BothACC_ACLK_OSC (also goes to the EMPRESSas ACLK_EMP) and ACC_ACLK_PLL are fed tothe VSM. The VSM selects the appropriateclock. The EMPRESS IC derives from the incom-ing ACLK_EMP clock, the I2S audio encoder Bitclock and Word clock, AE_BCLK and AE_WCLK.They are sent to the VSM with the digital audio.
On/Off
The signal IOn, coming from the Analog Board’smicrocomputer, enables the switched power sup-plies. IOn goes Low to turn power On. Theswitched supplies are: the 3V3, the 5Vdc and12Vdc on this module.
Reset
Control signal IRESET_DIG, controlled by themicrocomputer on the Analog Board is sent tothe Reset Logic circuit. The IRESET_DIG transi-tions to High when the whole system is reset. ALow is output on Pin 1 of 7902. This signal islabeled RESETn. The n on the end of many sig-nal names means enable. The Host Decodergenerates several Reset signals after it is opera-tional. the Serial Clock and Data lines providecommunication to many of the Microcomputerson the Digital Board.
Audio PLLs
During Playback, the Audio Decoder uses aphase locked clock signal to decode the digitalaudio, ACC_ACLK_PLL. This signal is generatedby 7900. It uses the system oscillator signal thatthe decoder is using and compares that signal toa feedback signal representing the data comingfrom the disc, SEL_ACLK1.
During Record, the Audio Encoder and VSM usea phase locked clock signal to Encode the digitalaudio, ACLK_EMPRESS/ACC_ACLK_OSC. Thissignal is generated by 7102. It uses the feed-back clock signal that the encoder is using andcompares that signal to the Field Identifier signal,FID_VIP_FF. This locks the Encoder and theVSM to the vertical sync of the video.
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Video Input Processor
The Video Input Processor Receives the Videoinput signals, selects one as a source, and con-verts it to parallel Digital video to be sent to theEMPRESS.
The VIP receives many signal types. AnalogVideo input signals CVBS, YC, and YUV arerouted via the Analog Board to connector 1601on Pins 14, 16, 18, 20, and 22. The signals aresent to IC7500. If a Digital Video input source isavailable, 8 Digital Video input signals,DV_IN_DATA (0-7), are sent from the DVIOBoard via 1603 to IC7500.
IC7500 converts the Analog Video to DigitalVideo. The SCLK and SDA control the operationof the VIP. This includes the signal selection.
It then processes the Digital Video to complywith the CCIR656 Digital Video Stream format.The VIP IC selects between the sources andsupplies an 8-bit output stream, VIP_Y/UV (0-7).This Digital Video stream goes to IC7403,EMPRESS, and to IC7100, Versatile StreamManager, VSM. The VSM uses the Digital Videofor Vertical Blanking Information, VBI, extraction.
A Field Identifier signal is generated using verti-cal and a 1/2 V signal using two flip flops. 7504Areceives the 1/2 V pulse producing a 1/2Vsquarewave on Pin 6. This signal is fed to thesecond FF that is triggered by sync.
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EMPRESS
The EMPRESS IC encodes supplied digitalvideo and audio to be sent to the VSM. TheDigital Video stream is converted into an MPEG2Video stream. Refer to Figure 23. I2S Audiocoming from the Analog Board is compressedinto a AC3 Audio stream.
The EMPRESS contains a microcomputer. It hasa dedicated regulator, 7404. It receives theSYSCLK_EMPRESS as its main clock. It is resetby the RESETn_VE signal. It is controlled by theHost Decoder via the I2C bus. The EMPRESSuses SDRAM to perform its functions.
Parallel digital video and digital audio areprocessed by the EMPRESS. 8 bit VIP_YUVcomes from the Video input Processor. This isaccompanied by support timing signals: VIP_HS,VIP_VS, VIP_IDQ, VIP_FID_FF and VIP_CLK.The Audio Comes in as AE_DATA1, with theWOrd and Bit Clocks, AE_BCLK and AE_WCLK.The Signals are compressed into MPEG2 andAC3. The leave the EMPRESS as VE_DATA andAE_DATA, going to the VSM.
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Versatile Stream Manager
The VSM encodes the Video, MPEG2 and audio,AC3 into a multiplexed I2S data stream to berecorded on the disc. The I2S data uses Pins101-107. It communicates control signals to andfrom the BE via the S2B bus on pins 24, 132,154, and 155. It communicates to the SystemControl Microcomputer on behalf of the entireDigital Board via UART1. It communicates con-trol signals to and from the DVIO Board usingUART2. It uses SDRAM to perform its functions.Its boot and operating firmware are in FlashEEPROM of the Extended Memory Interface. Itreceives its reset using the same signal as theHost Decoder. It also receives the same systemclock signal, SYSCLK_VSM_5508.
The VSM must receive data from severalsources. The Video comes into the VSM on twodata buses. One data bus comes from the VIP,and the other from the EMPRESS. The Video tobe recorded is the VE_Data signal lines. MPEG2has no sync information, so the VIP_YUV signalprovides this information for the multiplexingprocess. The Audio to be recorded comes fromthe EMPRESS as well. The audio data streamcoming in on Pins 177 and 178 uses two specialclocks for audio. One is the AE_CLK, and theother is ACC_ACLK_OSC, coming from theRecord Audio PLL. The VSM sends to the HostDecoder a Parallel video data bus of multiplexedAudio and Video. This is provided to monitor theVideo being recorded.
S2B InterfaceThe S2B interface between the VSM (IC7100)and the Servo processor MACE3 controls theBasic Engine during record and playback mode.This serial communication goes to the BE onPins 24, 132, 154, and 155.
Proper operation of the power up sequenceinvolves the VSM. The VSM communicates tothe Analog Microcomputer, during the Power UpSelf Test operation, using UART1.
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MPEG2 Host Decoder
The Host Decoder has several tasks. It is theHost of the I Squared C Bus for the DigitalBoard. It participates in the Power up sequence.It performs MPEG2 decoding. It generates theOSD and provides the Service UART serial port.IC7200 uses SDRAM for its many functions. Itreceives its main clock, SYSCLK_VSM_5508,from 7906 after being inverted and buffered by7904.
Power On
IC7200 participates in the initialization of the unit.Power up occurs in two stages. 7200 participatesin the second stage. After the Analog board andthe Front Panel Microcomputer check the unitand pass their tests, the Analog Microcomputerturns On the Standby supplies. It uses an IONcontrol voltage that passes through the DigitalBoard. This includes the 3.3Vdc supply for 7200.7200 then receives the DIG_Resetn signal fromthe Analog Board.
7200 creates reset outputs for the Digital Board,the DVIO Board and the BE: Resetn_VE goes tothe EMPRESS. RSTN_DVIO goes to the DVIOBoard. RSTN_BE goes to the BE. TheEMPRESS_BOOT signal goes to the EMPRESSfor its start up flag. The Decoder is a 2.5Vdcdevice. The BE and the DVIO microcomputersare 3.3Vdc devices. 7702 elevates the reset sig-nals to 3.3Vdc.
If 7200 passes its self test and the other ICscommunicate properly, the unit’s power will stayOn. If not, the unit will go into Sleep mode, neverlooking for keyboard input again. This processhas 10 Seconds to occur. If it does not, theAnalog Microcomputer will place the unit in sleepmode, turning Off the Standby supplies which isthe VCC for most of the ICs on the Digital Board.
Playback
During playback, the serial data from the BasicEngine goes directly to the MPEG2/AC3Decoder, IC7200. The serial Front End I2SInterface receives the signal on Pins 17-22.Refer to Figure 25. The A/V Demultiplexes, sep-arates the Audio and Video data. IC7200 thendecodes the MPEG2 video and AC3 audio. Itcontains the analog Video Encoder and has thefollowing outputs to the Analog Board: RGB, Y/C,CVBS, I2S Audio, (PCM format) and SPDIFAudio (Digital Audio output).
There is another video output path from IC7200.The Digital Video for the progressive scan circuit,PSCAN_YUV(0-7).
RecordIt receives the Parallel Video output of the VSM.The Parallel Video path sends the recordablevideo and audio back to the outputs duringrecord and powered up standby. It receives theselected Multiplexed Data stream from the VSMvia the D_PAR_D(0,7) lines. There are supportsignals for the Parallel Data Stream on Pins 196,201, 205, and 206. Because of the amount ofprocessing, the output video at the rear jacks isdelayed about 4 seconds from the video cominginto the unit.
ComPairThe ComPair service aid connects to 7200 via aserial communication port. Using ComPair soft-ware and a computer, service troubleshootingand adjustments can be performed.ComPair has a dedicated connection on theDigital Board, 1901. The input Pins for 7200 are2, 3, 197, 200, and, 204. ComPair cannot func-tion if 7200 does not initialize properly. The port’sinputs and outputs are buffered by 7905.
EMIThe Extended Memory Interface is used by theVSM and the Decoder. It is Flash EEPROM. Itcontains the boot and operating firmware for theVSM and the Decoder. Like all other memory, ituses an address Bus, a Data Bus, and supportcontrol signals.
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Progressive Scan
The progressive scan section is integrated intothe Digital Board and built around the SAGEFli2200 Deinterlacer/Line Doubler (7700). Referto Figure 26. This I2C controlled device uses64Mbit SDRAM (32bit x 2M) to perform highquality Line Doubling, or de-interlacing (mesh-ing). The Line Doubler gets Digital Y/UV inputdata on Pins 20-27, from 7200. The format of theDigital Y/UV input is CCIR656 with separated Hsync, V Sync.
Because IC 7200 doesn’t have a V sync output,the odd/even output of this IC has to be translat-ed to a V sync signal. Vertical sync is generatedwith a flip-flop IC7701 and an XOR, 7702.
Power and ClocksIC7700 uses two supplies, 3.3Vdc and 2.5Vdc.The system clock, SYSCLK_PROGSCAN, isrunning at 27Mhz.
7700 produces three 10-bit output signals, Y, Crand Cb. These are sent to the D/A converter7801.
D/A Digital Encoder
The output of 7701 (4:4:4 progressive Video) isfed to the Digital to Analog Device, 7801. TheRGB output is a current signal fed via a low passfilter to the output Op Amps, 7802 and 7803. TheAnalog Video, 480P, is fed via a 7-conductor flexcable to the Analog Board.
Power and ClocksIC7801 uses the 3.3Vdc supply. The systemclock, SYSCLK_PROGSCAN is running at27MHz.
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Digital Signal Processor VN04
The functionality of the two Digital Boards isIdentical. Refer to Figure 28. It is responsible forencoding Digital Video and Audio into MPEG2and AC3 respectively. It supplies MPEG2 andAC3 via an I squared S serial protocol to theBasic Engine (BE) for recording. It also receivesthe MPEG2 Video via I2S from the BE, decodesthe signal, and supplies Digital Video to theProgressive Scan circuit. It supplies AnalogVideo to the Analog Board, and Digital Audio(I2S) to the Analog Board. The DVIO Board’s cir-cuitry has been migrated to the Digital Board.
Most of the Digital Board’s operations are cen-tralized into one microcomputer, 7400. It usestwo DRAM ICs to perform its functions. 7400uses Flash EEPROM to store its firmware. Itperforms MPEG2 encoding. It combines theAudio and Video into one data stream. It com-municates control signals to the BE. The DigitalVideo/Audio Data is sent back through the play-back signal path. It perform MPEG Decoding andanalog signal generation. It produces an 8-bit
digital Y/UV for the Progressive Scan circuit. Itproduces two types of Audio, I2S and SPDIF.They both go to the Analog Board.
The Progressive Scan, Pscan, circuit, 7703sends Y/Pr/Pb analog, 480P, Video to the AnalogBoard to be provided to the output jacks. ThePscan circuit contains a Line Doubler and aDigital Encoder. The Line Doubler receives the8-bit Y/UV from 7400. It doubles the verticalscan lines and produces separate Y, Pr, and Pb.The signals are passed through amplifiers beforethey are sent to the Analog Board.
The Video Input Processor receives the selectedinput signals from the Analog Board. It has twomajor functions. It performa A to D conversionand Serial to Parallel conversion. it provides 8Bit Digital Y/UV to the Microcomputer. The Digital Video Input Output, DVIO, Board iseliminated using the VN04 Digital Board. TheMicrocomputer performs most of the signal pro-cessing. The Physical and Link circuits work thesame as the previous DVIO. It is a 1394 IEEEcompliant serial input device, sometimes called aFirewire or I link. This kind of output is commonlyfound on Digital Camcorders.
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Figure 27 - Buffers
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DVD Mechanism and ServoBoard
Basic Engine
The Basic Engine consists of a DVD-Mechanismwith dual laser Optical Pickup Unit (OPU), a trayloader, a fan unit, and a PCB containing all elec-tronics to control the module. The OPU containsthe Focus and Radial Motors. The Mechanismholding the OPU contains the Sled and the TiltMotors. The electronics of the module areresponsible for all the basic servo tasks. It readsand writes data to and from the disc.
The PCB is multilayer, using Surface MountedCircuitry with a very high component density.Detailed diagnostics and fault finding are avail-able via ComPair.
Some specifications:
* Record DVD+R and R/W* Lossless linking* Recording speed: 1.2 x* Playback DVD, DVD+R(W), DVD (SL/DL),
DVD-R, DVD-RW (V1.1)
* Playback speed: 1.2 x * Playback CD, CD-DA, CD-R, CD-RW, CD-
ROM, VCD/SVCD* Playback speed: 3 x* It controls all other functions like tray control,
start/stop, disc rotation, tracking, jumping,and communication to the Digital Board.
The Servo circuit provides the interface betweenthe Mechanism and the Digital Signal ProcessingBoard. It is mostly on one board attached to thebottom of the mechanism. It is made up of fourmain circuits:
* The SPIDRE is the Signal Processor IC forDVD Recordable
* The MACE3 is the Mini All in one CD Enginethird generation.
* The Encoder/Decoder is the Translation cir-cuit for data going to and from the disc.
* The AWSOME is the Adip Decoding, WobbleProccessing, Error Correction, Synchronousstart Stop and Occasionally Mend Errors.
Initialization processDuring power-up, a reset of the BE is preformed.This is parallel to the reset process of the DigitalBoard. After the MACE3 resets, a System reset
Figure 29 - Basic Engine
42
Figu
re 3
0 - S
ervo
Blo
ck D
iagr
am
occurs to reset the other microcomputers in theBE. A self-test will automatically start. Each ofthe microcomputers must respond to the I2Cbus. The SDRAM and flash are also tested. Ifthe self test passes, the SUR signal line will goLow. Part of the self test is the CPR switchingvoltage coming from the Versatile StreamManager. If it is ready to function, it will be Low.After the self test passes, the BE will wait for thefirst Serial to Basic Engine, S2B, user com-mand. E.g. "Tray_out".
Disc recognition processThe process of disc recognition is entirely per-formed within the BE. If the disc is not recog-nized, the problem is in the BE or somethingmissing supplied to the BE. Information aboutthe disc type is sent via the Subcode data pathto the MPEG2 Decoder microcomputer.
DVDR Mechanism
The DVDR-M is made up of three components:Optical Pickup Unit, OPU, the Sled, and theTurntable Motor. The OPU contains two lasers:one for CDs with a wavelength of 780 nm, andone for DVDs with a wavelength of 650 nm.
The OPU contains: the Optics, the Focus Motor,the Laser Drive IC (LADIC), the Tilt sensor, theDVD Rewritable OPU Pre-Processor IC (DROP-PI), and the EEPROM with the OPU adjustmentdata.
DROPPI
The DROPPI (DVD Rewritable OPU Pre-processor IC) is a multi-purpose analog pre-processor. It supports many photo detector con-figurations and output signal modes. It producesRF and servo feedback signals, Q1-Q6. Its out-put signals are on the same flex ribbon cablewith the wideband RF (differential signals). TheWobble, focus, and Sled Servo signals are rela-tively low bandwidth.
LADIC
The Laser Drive IC, LADIC, controls the data tothe lasers, and the supply to them. It performsthree main functions:
· It drives the laser for both playback andrecord functions. Its greatest stress is real-ized during record, producing data signalsand write pulses. The recording process isflexible with respect to the input modulationmethod (EFM, EFM+, 17 pp, etc.). This isnecessary to support CDR/RW andDVDR/RW. To accomplish this, the LADICuses two Random Access Memories (RAM)which can be loaded (non real-time) via theI2C Bus from the microcontroller.
· It drives the laser with a sequence of pro-grammable write pulses with high timingaccuracy and high peak current levels.
· It controls the exact light power levels comingfrom the laser and controls the exact powerabsorbed by the disc during recording.
The LADIC needs three independent powersupplies. These are the analog and digital powersupplies, and V Bias for the laser driver function.The supplies are separate to obtain maximumoutput performance where there are large andhighly dynamic current flows. The LADIC is controlled by an I2C bus. Thelaser is operated at three current levels:Playback, Record and Erase. During the initial-ization of a disc to be recorded on, and testrecording is performed in a special place on the
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Figure 31 - DVDM
innermost section of the disc. A series of randomdata is recorded with a wide range of current lev-els. The data is played back. Two feedback sig-nals are generated and sent to the MACE3 cir-cuit, A1 and A2. A second Fine tuning of theOptimal Laser Current is performed. The disc iswritten to again except the current range is cho-sen by the MACE3 using the feedback received.This fine tuning of the laser current produces theCalf feedback signal that is sent to the MACE3and it is stored in the MACE3’s operating RAM.
Figure 32 - Laser Drive IC
44Figure 33 - OPU
Servo Circuit Description
The Servo circuit provides the interface betweenthe Mechanism and the Digital Signal ProcessingBoard. It is mostly on one board attached to thebottom of the mechanism. It is made up of fourmain circuits:
The SPIDREThe MACE3The Encoder/Decoder The AWSOME.
Servo Power and ResetThe Servo receives: 12Vdc, 5Vdc, 3.3Vdc and-5Vdc from the Power Supply. There are three2.5V supplies on the Servo Board connected tothe 3.3Vdc supply. The MACE3 is reset by theDigital Board, via the Reset_BE signal. A Resetsignal comes from the MACE 3 for the rest of theservo. The Mace3 is the Host for the local I2CBus.
SPIDRE
The SPIDRE (Signal Processing IC for DVDREwritable) is a multi-purpose analog pre-processor IC specifically intended for writingapplications.
The SPIDRE receives two Power Supplies:-5Vdc and 5Vdc. Its has three main tasks. One isto interface the Servo signals that go to theMACE3 Servo Processor. The Second isPreprocessor for the RF signal coming from thedisc during playback. The third is to process theRF signal coming from the Encoder duringrecord.
The SPIDRE is controlled by the AWSOME via aserial bus on Pins 35, 37, and 38. The AWSOMEcommunicates: gain information, data type, andoperation mode, Play or record.
The Servo signals to be processed include:Playback HF/RF, the focus servo feedback sig-nals, the radial feedback, the track loss signal,and tilt sensor signal. The HF/RF (EMF) signalvaries greatly between disc formats. The FocusError and Radial Error signals come from themechanism on the Q1-6 signal paths. The TiltError has a Photo Tilt Sensor. The dynamic rangeof these signals is very large. They are convertedto Lower frequency RF data paths that theMACE3 can accommodate. This is required forplayability of the many different kinds ofdiscs.The error signals are all balanced to reducenoise interference. Thus, they are named XXpositive, and XX negative. The Output signalsinclude: the Focus Error, the Radial Error, the Tilterror, laser Power, and tracking loss signals.
The Record RF EFM data and EFM Clockcomes from IC 7402, Encoder circuit, and is sup-plied to the SPIDRE on Pins 48-51 of 7101. TheSPIDRE processes the RF signals for gain con-trol of the Error control signals going to theMACE3 during record. All of these signals arebalanced. Thus there is a negative and a posi-tive signal for all of them.
The LASP, Laser Power feedback signal isprocessed by the SPIDRE. During playback, theEFM coming from the disc is used by the ALFAcircuit to generate the AMEAS, ALFAMeasurement signal that goes back to theLADIC for precise control of the LASER power.During record, the EFM signal coming from theEncoder is used by the ALFA circuit to create theAMEAS signal.
The pregroove tracking error signal comes froma Preprocessor in the OPU. The PPN signal isamplified and sent to the Wobble Processor inthe Decoder circuit.
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46
Figure 34
- PRE- Processor
MACE3 Servo Microcomputer
The MACE3 IC is the Mini All Cd Engine thirdgeneration. Its vendor number is SAA7830. It isa combined servo processor and microcomputer. The servo processor handles the signals forfocusing and tracking for disc access. It also
generates the control signals for tray control. In aCD/DVD system, there are several active controlloops. Some of them are needed to adjust theservo error signals. It monitors and adjusts theoffsets, signal amplitudes, and loop gains(AGCs). The control loops determine the laserspot position on the disc in the radial (Sled),
Figure 36 - PCS Phase comparison
Figure 37 - PCS input Block
Figure 35 - PCS Motor
axial (focus), and tangential directions (Tilt). Thisaccess system consists of two parts, namely theFocus Actuator and the Sled, which are, within acertain range, mechanically and electrically inde-pendent.
The analog signals from the SPIDRE are con-verted into a digital representation using A/Dconverters. The digital codes are then applied tologic circuitry to obtain the various control sig-nals.
OPC (Optimum Power Calibration)This device has an integrated Optimum PowerCalculation block for use in CDR, CD-RW, andDVD+R applications. It reads three analog sig-nals: A1, A2, and CALF. These represent Max,Min, and Average values of the EFM comingfrom the disc, respectively. It also takes thePower (PW) signal from the laser controller andthen feeds an analog signal, ALPHA0, out tocontrol the laser power. The conversion frequen-cy is 88kHz per channel. Basically, the OPC pro-cedure tries to find out the optimum laser powerto be used on a specific disc. It consists of threephases:
1. WRITE - Random EFM data is written to thetest area of the disc at increasing levels oflaser power, controlled by ALPHA0.
2. READ - The data on A1, A2, and CALF isread back from the test area and stored inmemory.
3. CALCULATION - the embedded microcom-puter then calculates the setting of ALPHA0where the least jitter is encountered. Somepre-processing is carried out by the OPClogic to reduce the processor's load. Thissequence is performed twice - first a coarsecalibration, followed by a fine-tuning.
The micro controller has many responsibilities. Itprocesses the Serial to Basic Engine, S2B, com-mands from the Digital Board. It controls the var-ious processes in the mechanism via I2C.
The MACE3 uses a Parallel communication busfor access to its Flash ROM. Refer to Figure 38.The Flash Memory contains the firmware for theBE. The MACE3, the Encoder and AWSOMEshare a parallel bus with 32K of SRAM
When the power is applied to the unit, the DigitalBoard sends a reset signal to the MACE3. TheMACE 3 checks its SRAM, then reads its FlashRom and sends a System Reset signal to theICs on the Servo Board. When its memory testsare complete and they pass, a SUR control volt-age goes low, indicating to the Digital Board thatit is ready to receive commands. It then initial-izes its I Square C Bus and communicates to theDROPPI and LADIC on the Mechanism. The TiltMotor is exercised and centered. The PSEN sig-nal then appears.
The Microcomputer produces several outputs.Many of them are error signals. It produces: theRadial Error, the Focus Error, the Tilt Motor con-trol, and the Position Control Sled (PCS) signals.Each of the motors has a driver circuit.
The Microcomputer controls the Tray motor drivecircuit. The Tray switch goes directly to theMACE3.
The Microcomputer controls the PCS. ThePosition Control Sled must operate very accu-rately. It cannot track the Disc’s tracks of 1.6microns alone, but its precision is a must. Thereare two Hall sensors positioned 90 degrees apartin a circular fashion. A round magnet is attachedto the armature of the drive motor. The position-ing of the sensors gives them their name, Sineand Cosine. The motor is a basic universal type.The exact rotation of the armature is detected bythe Hall Sensors. The phase of the Hall sensorsignals are compared to a reference signal gen-erated internally by the MACE3. The focus actu-ator moves the lens side to side for tracking theindividual tracks. When the drive current to theactuator increases to a certain point, the micro-computer knows the Sled must be moved. TheSled is driven to minimize the actuator’s drivecurrent, meaning it is right under the propertrack. The microcomputer produces theReference DC offset for the Op amp inputs.
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48Figure 38 - MACE3 Circuit
Wobble
A Pre-groove is stamped on writable discs. Allrecordable DVD media types feature a micro-scopic wobble groove embedded in the plasticsubstrate. This wobble provides the recorderwith the timing information needed to place thedata accurately on the disc. During recording,the drive's laser follows this groove to ensureconsistent spacing of data in a spiral track. Thewalls of the groove are modulated in a consistentsinusoidal pattern, so the Wobble processor canread and compare it to an oscillator for preciserotation of the disc. This modulated pattern iscalled a wobble groove because the walls of thegroove appear to wobble from side to side. Thissignal is only used during recording, and there-fore has no effect on the playback process.Among the DVD family of formats, only record-able media use wobble grooves.
Lossless linking describes the need to connectdata streams on a disc without any unusedspace between the previous track and the newlyrecorded segment. For lossless linking, it is nec-essary to write data blocks in the correct positionwith high accuracy (within 1 micron). For thispurpose, the groove is mastered with a high
wobble frequency (817kHz), which ensures thatthe writing can be started and stopped at anaccurately defined position. The writing clock asobtained from this groove is very accurate.
ADIPAddress in Pregroove is the name of the processof knowing how far into a disc the laser positionis during recording. The Wobbles are counted,and an address location of the section of thedisc is calculated.
The CD HF signal path and the DVD signal pathneeds are different. The DVD signals are han-dled by the Signal Processor IC for DVDRecording, the SPIDRE. The CD HF signal ishandled by the Decoder, IC 7402.
Figure 27 - Wobble Tracks
Encoder/Decoder/HDR65
The Encoder/Decoder has the following func-tions:
· Encoder for DVD+RW. This part creates theEFM+ (16 bit) signals from the I2S datastream.
· Decoder for DVD and CD. This part process-es the HF-signal from the SPIDRE. It con-verts the EFM(+) signals to data, and per-forms error detection and error correction.
· Output to SPIDRE pre-processor for RF-AGC.
This IC decodes EFM or EFM+HF signals direct-ly from the SPIDRE. These include: HF, PLLdata recovery, demodulation, and error correc-tion.
The Encoder/Decoder has two independentmicrocontroller interfaces. The first is a serial I2Cbus and the second is a standard 8-bit multi-plexed parallel interface. Both of these interfacesprovide access to 32k of SRAM 8-bit registersfor control and status.
The analog front-end input on Pins 9 and 10converts the HF input to the digital domain via an8-bit A/D converter. The A/D is supplied by anAGC circuit to obtain the optimum performancefrom the converter. An external oscillator is sup-plied for this subsystem to recover the data fromthe channel stream. It corrects asymmetry, per-forms noise filtering and equalization, and finallyrecovers the bit clock and data from the channelusing a digital PLL.
The demodulator portion detects the frame syn-chronization signals and decodes the EFM (14bit) and EFM+ (16 bit) data and sub-code wordsinto 8-bit symbols. Via the serial output interface,the I2S data (audio and video) go to theDVD+RW interface.
The spindle-motor interface provides both motorcontrol signals from the demodulator and, inaddition, contains a tachometer loop that acceptstachometer pulses from the motor unit. Themotor is a standard three phase motor. Motorspeed is controlled by the Wobble Processorduring record. During playback, the Wobbleprocessor is monitoring the Data stacked up inthe SRAM of 7204. The Motor control signal ison Pin 98 which supplies the drive IC 7301.
AWESOME
AWESOME stands for: Adip decoding, Wobbleprocessing, Error correction, Synchronousstart/stop and Occasionally Mend Errors.
The AWESOME gate array chip, IC 7401, is afully digital DVD+RW add-on for the HDR65. Acombination of both ICs can do CD and DVDdecoding and CD, DVD-R(W), and DVD+RWencoding. It contains logic for:
· Wobble processing· Address detection· Write clock generation· Start and stop· ADdress In Pregroove decoding, Adip· Spindle motor control to do CLV on wobble· Link bits insertion (according to DVD+RW
standard).· Output to SPIDRE pre-processor for wobble-
AGC
It also receives the serial interface signal fromthe Encoder/Decoder IC on Pins 6, 7, and 8 andmerges the internal serial bus to be sent to theanalog pre-processor (SPIDRE), on pins 72, 78,and 79.
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50
Figure 39 - Encoder/Decoder
r
Motor Drivers
The motor drivers each receive an error or con-trol voltage. There are 6 motor drivers in thisunit: the Focus Motor Driver, the Radial Motordrivers, the Turntable Motor Driver, the Tilt Motordriver, the Sled motor Driver and the Tray motorDriver.
Focus Motor DriverThe Focus motor is located on the OPU. It con-trols the up and down motion of the laser’s lens.An error signal is produced by the MACE3Microcomputer. The FO signal comes into Pin 3of 7302. The Driver circuit amplifies the signaland converts it to a balanced output at Pins 1and 2 of IC7302. The Output goes to the OPU.
Radial Motor DriverThe Radial motor is located on the OPU. It con-trols the side to side motion of the laser’s lens.This is used in conjunction with the Sled Motorfor tracking. An error signal is produced by theMACE3 Microcomputer. The RA signal comesinto Pin 25 of 7302. The Driver circuit amplifiesthe signal and converts it to a balanced output atPins 26 and 27 of IC7302. The Output goes tothe OPU.
Turntable Motor DriverThe Turntable Motor is a standard three phasemotor similar to what is found in VCR capstanmotor circuits.The driver IC, 7301, receives twocontrol voltages. The Motor Error signal comesinto Pin 22. There is a Motor Enable switchingvoltage coming into Pin 23. A three-phase drivesignal is provided to the motor. Three hall ele-ments feed speed and phase data back to themotor driver IC. These signals are amplified.Three FG signals are output to the Encoder/Decoder from Pins 16, 17, and 18.
Tilt Motor DriverThe Tilt Motor driver contains two signal paths.The motor has two field windings. The Tilt Motorhas two error voltages supplied by the MACE3.The Tilt Output Cosine and Tilt Output Sine sig-nals go to Pins 17 and 18 of 7306. The Signalsare amplified and provided to the motor on Pins
12-5 of IC7306.
Sled Motor DriverTHe MACE3 produces the SL control voltage forthe driver circuit. The Sled motor drive signal isprovided to the Sled Motor by 7302. The SL sig-nal comes into IC7302 on Pin 20. A control volt-age is developed and amplifiers produce thedrive voltages on Pins 17 and 18. These areconnected to 1302 on Pins 7 and 8.
Tray motor Driver. Tray in and Tray out logic control lines arereceived from the MACE3 and a motor drive sig-nal is provided to the Tray Motor. The logic con-trol signal comes into IC7302 on Pins 15 and 16.A control voltage is developed and amplifiersproduce the drive voltages on Pins 12 and 13.These are connected to 1301 on Pins 3 and 4.
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52Figure 40 - Motor Drivers
Troubleshooting
The Power Supply
This Power Supply operates whenever AC poweris applied. The primary winding of the transformeroperates using Hot Ground. Be sure to use anisolation transformer on the AC input. Whenworking with Switch Mode Power Supplies, thereare three general symptoms to be considered: Nooperation or dead, improper regulation, and oneor more supply lines missing.
No OperationThis symptom can be caused by many compo-nents. Of course, check the Standby suppliescoming from the SMPS. If you can identify amissing supply, then move on to the next sectionSMPS problems.
When AC is applied to the unit, The SystemControl Microcomputer Resets and turns Onsome of the switched supplies, via the STBYcontrol voltage. The 5SW and 8SW supplies arethe first group of supplies to be switched On.The Analog Microcomputer Initializes its I2C busand communicates with the RF Unit, the SoundIF, the Input Matrix, and the Front Panel. If thosecircuits operate properly, the ION control voltagegoes low to turn On the second set of switchedvoltages. If the ION switching voltage does notappear, the problem is on the Analog Board orthe Front Panel. The Analog Board Micro-computer only allows 10 seconds for thisprocess. and it will only try once.
If the ION switching voltage appears, the AnalogBoard and the Front Panel are operating wellenough to turn On power. The 3.3Vdc is themain supply to most of the microcomputers onmany of the PCBs.
VN02 Product
The Analog Board’s Microcomputer also sendsout the IReset signal to 7902 on the DigitalBoard. This IC produces a delayed Resetn signal
line for the Host Decoder, the VSM, the VIP, andthe Line Doubler. The Host Decoder activatesthe I2C Bus on the Digital Board. The HostDecoder also produces four reset signals for: theDVIO Board, two of them go to the EMPRESSand one to the VSM. The Digital Board sends areset to the BE. The Host Decoder expects aresponse on the I2C Bus from: the EMPRESS,the VIP, and both Progressive Scan ICs. The BEperforms its own reset and self analysis andcommunicates to the VSM via two signals that itis ready to operate. The SUR line produces aclear to send signal to Pin 24 of the VSM andthe PSEN signal must appear. The PSEN signalis 5.3 MHz. If either the SUR line or the PSENsignals do not appear, the VSM will communi-cate to the Analog Board’s Microcomputer, andthe Power will be shut down.
If the BE has responded properly and the rest ofthe Digital Board operates properly, the Host Decoder communicates to the VSM whichcommunicates to System Control Microcomputeron the Analog Board to tell the Front Panel toturn On the Display and wait for customerKeyboard input.
The challenge is to figure out where in thisprocess the machine stops. The AnalogMicrocomputer allows 10 seconds for the VSMto give the all is well signal. If it does not occur,the ION switching voltage is removed and theunit goes into shutdown.
Listen for the BE reseting the Tilt Motor. It is avibration noise that is easily heard. The tiltMotor’s vibration occurs very near the end of theprocess. If you can hear it, the Digital Board andAnalog Board passed their own initial self test. Italso means the BE is nearing the end of itstests. Check for the SUR line coming from theBE to the VSM. If it goes high, the BE haspassed its self test and is ready to receive com-mands from the VSM. There is an ugly square-wave on the SUR line dureing times of communi-
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cation. In Powerd Up Standby, the Line is High.VN04 Product
The focus is going to be proving the problem ison the Digital Board from the inputs and outputs.The main conponent is a 308 pin Ball Grid Array.This makes replacing the Microcomputer verydifficult for most servicers. Once you haveproven the problem is on the Digital Board, youwill probably want to replace the Digital Board.
The ION switching voltage passes through theDigital Board. If the unit is not turning On, this isa good place to start. If it goes Low, The AnalogBoard and Front Panel have passed their initial-ization tests.
ION control voltage will only occur once if thereis a problem. You must have your meter orscope in place to make the check. The AnalogBoard only allows 10 seconds for the unit topass all of its tests. If it does not, it will go intoshut down until power is removed.
If the ION control voltage does not go Low, theproblem is likely on the Analog or Front PanelBoards. Check for the SCL and SDA on theSystem Control Microcomputer.
If the ION goes Low for 10 seconds and the unitlocks up the unit, the problem could be in theDigital Board. Listen for the BE’s Tilt Motor tovibrate. If it does, the Digital Board’sMicrocomputer and Reset circuits are functionalat a basic level. If the BE doesn’t vibrate, checkthe power to the BE and the Digital Board.When ION goes Low all supplies should be aval-able during the 10 second start up process. If theSupplies check out, manually reset the BE bypulling the RESET_BE line Low with a 100 ohmresister. If it still does not vibrate, the problem isin the BE. If it will manually Reset, the problem ison the Digital Board. If the BE vibrates and theunit still shuts down, the problem is likely in theDigital Board, but this is not rock solid. Check foractivity on the two UARTS: the one between theBE and the Microcomputer, and the one betweenthe Microcomputer and the System ControlMicrocomputer on the Analog Board. If UART3 isnot proper, the Digital Board is most likely the
problem. SMPS Problems
We are starting with a Dead unit. Connect it toan isolation transformer. Check for 160Vdc onthe drain of 7307. If it is not present, there is anopen in the AC input circuit. This includes thebridge rectifier and the primary winding of thetransformer.
Next, check for voltage on the gate of 7307. Itshould have about 5 - 6 volts on it. If it is near0Vdc, check two things. Check the FET for ashort. And, check Pin 6 of IC 7313 supplying thegate. If the gate voltage is 4Vdc or more, theFET should be conducting.
Check the voltage on the source. It should be afew tenths at most. If it is higher, replace thesource resistors and the FET, 3352, 3321, and7307. It is a good idea any time the FET isreplaced to replace the source resistors. Theycan read proper and be out of tolerance, causinga repeat failure in a short time.
Is the unit ticking? Place a scope on the drain ofthe FET. Is there a signal there? If the signal isabout 2 Hz, the Overload Circuit may be activat-ing. Remove AC power and check each of theoutput lines for a short. If no problem can beidentified, replace the source sensing resistors,3321 and 3352. Check Supply AC and monitorPin 5 of IC 7313. If it reaches .4V, there is animproper load in the circuit or the FET is bad.
Improper RegulationThis type fault will show itself in one of threeways: The outputs are too high, the outputs aretoo low, or alternate high and low outputs. Theprecise regulation loop monitors the 5Vdc supplyMeasure the voltage drop on the diode portion ofthe optic coupler, 7314.
If the voltages on the output lines are too high,the voltage drop on the diode portion of the opticcoupler should be 1-1.2Vdc. The transistor por-tion should be conducting hard with little or novoltage drop. If there is a voltage drop on thetransistor portion, the optic coupler or the driveto it are bad.
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If the transistor portion of the optic coupler haslittle or no voltage drop, the secondary side ofthe power supply is asking for less output. Theproblem involves 7313 and associated compo-nents. Check 6311. If it is leaky, the sense linewill be low in respect to the true output, causingan elevated output. If it is not, the problemreplace IC 7313.
If the optic diode has a volt or less, the shuntregulator (7314) and/or the voltage divider resis-tors can be the problem. Check the diode portionof the optic coupler.
If the voltages on the outputs are too low, thevoltage drop on the diode in the optic couplershould be less than a volt. The transistor sideshould have a 5-6V drop. If these voltages areproper, the secondary portion of the power sup-ply is asking for more output, and the problem ison the primary side.
Check the signal on Pin 5 of 7313. It should beless than .3Vp-p with low output voltages. if its 3.or higher, replace the Sense resistors, 3321 and3352. If the Sense input is low, IC7313 is likelythe problem.
If the diode portion has a volt or more on it, theShunt Regulator is improperly driving the opticcoupler. The problem is with the Shunt Regulatoror the voltage dividers.
If the diode portion does not have a voltage dropof .9V or more and the transistor side has asmall voltage drop 3V or less, the transistor por-tion of the optic coupler is faulty.
For a condition of having alternate high and lowoutput voltages, there is a rectification and filter-ing problem or there is an excessive load on oneof the output lines. If there is an excessive loadon the 5 Vdc line, the 5V could read normal whilethe other outputs rise to abnormal levels. Thesupply is working harder to maintain the 5V onthe monitored line but the other outputs receiveproportionally more energy. This effect makestheir output voltage elevated.
The condition would be very simular if the rectifi-cation and filtering were poor on the monitoredline.
If the non-monitored line(s) are low, the same twothings can happen on just one source. Poor recti-fication or filtering will cause low output. Anexcessive load will also cause this symptom.
For a condition of having just one output miss-ing, there is an open in the Rectification/ Filteringcircuit. This could include: a fuseable resistor,the winding of the transformer, or problems withthe foil pattern on the board. Once the open isidentified, measure the line for a short beforeproviding AC to the supply.
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The Front Panel/ Display Board
Problems on the Front Panel display fall intofour categories: no display function, improperdisplay function, no keyboard function, and noremote control function. Do not consider thisboard at fault first if all of the symptoms arepresent. The front panel cannot operate untilmany functions of self-check pass. A problemon this board more likely shows one of theabove symptoms.
The board has several power supply voltagesthat should be checked first before consideringa problem on the board.
No display unit operatesThere are three major elements to work withfor no display: the fluorescent tube, theMicrocontroller and the power supplies dedi-cated to the tube. The VGNSTBY supply isonly used by the tube. Measure the VGNSTBY.It should be -28V or more. If it is not present,trace it back to the power supply. If it is there,check the Filiment supply. It should be 6-8Vac.If it is present, check for the scanning signalson 7103. If they are present the tube is bad. Ifthe scanning signals are missing replace 7103.If the Filiment supply is missing, check for thedrive signal from Pin 19 of 7103. If it is pre-sent, there is a problem with the drive transis-tors, 7109, 7108, 7106, and associated com-ponents. If the drive is missing, replace 7103.
Improper displayThe self diagnostics have a test pattern routinethat can help when troubleshooting this type offailure. One of the choices is to light up all of thesegments. Set this up to show you what seg-ments are not functioning properly. A patternshould be visible. One row or a column may notbe lighting up. Trace out the pin that is responsi-ble for the row or rows that are not lighting.There are diodes connected to these pins.Normally, the diode(s) are bad or there is a for-eign substance on the board at that location.
No keyboard functionIt takes two Microcomputers to function proper-ly for the keyboard to function: theMicrocomputer on the Front Panel, an themicrocomputer on the Analog Board, If the dis-play is working, the Front Panel should beshowing four dashes. This means the Powerup Reset and self check has passed. Checkfor remote operation. If the remote functions,start with the Analog Board’s microcomputer.
Monitor the I2C Bus while pressing the key-board. The data should change. If it does, theproblem could be on the Digital Board. Checkthe INT output on Pin 5 of 1910. When a key-board button is pressed and theMicrocomputer reconizes this, the INT linegoes low. This communicates to the SystemControl IC to retreive the data from the FrontPanel Microcomputer. If the INT does not golow, the problem is on the Front Panel. If theI2C bus does not reflect a change in datawhen a key is pressed, the problem is on theAnalog Board. For problems on the FrontPanel, check the RTL logic for the keys on theFront Panel. If the Keyboard data seems to begetting into the microcomputer, check the sec-ondary switched supplies. The STBY goes Lowto turn on the SW5 and the SW 8Vdc suppliesas part of the power up.
No Remote Control Function It takes two Microcomputers to function proper-ly for the Remote control to function: theMicrocomputer on the Front Panel and themicrocomputer on the Analog Board. If the dis-play is working, and keyboard function are nor-mal, the Front Panel Microcomputer and therest of the unit is operating properly. Start withIR receiver’s output. The signal should be TTLlevel. If it is not, be sure the connections aregood, supplying the B+ and ground to theReceiver. If the signal is there, check for it onthe Front Panel’s Microcomputer, Pin 20. If it ismissing check 7107 and its support compo-nents.
If the signal going to the Front panelMicrocomputer is proper, monitor the I2C Bus
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while pressing the remote keyboard. The datashould change. If it does not, check all the vitalsto the Microcomputer, VCC, grounds, Clocks,and reset the microcomputer as a test. If none ofthese yield results, suspect the microcomputer.
The Digital Board
The Digital Board is central to the recorder’soperation. There are two categories of symptomsthat cause the Digital Board to be suspect. Oneis “No Power” and the other is a more conven-tional digital signal flow problem. The reason theDigital Board needs to be focused on for a NoPower problem is that the Digital Board commu-nicates the condition of the BE and Digital Boardto the System Control Microcomputer.
VN02UART1 of the VSM communicates to the SystemControl Microcomputer. The Host Decoder ICalso produces secondary reset functions formany ICs including the BE. If you are concernedwith “No Power” and the SMPS is functioning, goto the No power part of this write up where allthe circuits involved in power up will be dis-cussed. For digital signal path troubleshooting,proceed to the next paragraph.
Close scrutiny of the symptom is necessary. Ifyou are considering the problem to be on theDigital Board, you have basic operation of theunit. The unit powers up. The Front Panel’s dis-play is proper. The unit will try to play a disc. Thesymptom involves: no menu, no playback Videoor Audio, no record Video or Audio, or scrambledVideo or Audio. If you can play a known gooddisc, you can eliminate half of the circuitry in theDigital Signal Processor. If you see the Videoand Audio during the record process, the DigitalBoard is probably not where your problem is.The parallel loop thru condition that occurs dur-ing record utilizes most of the circuitry on theDigital Board and the Analog Board.
If the problem is apparent in playback, use play-back for troubleshooting. Use a disc that has colorbars recorded on it. Check the CVBS signalon the output of the Host Decoder. The bars sig-
nal allows you to closely scrutinize the signal onthe output. If the signal is good, follow the signalthrough the Analog Board to the output jacks.If the signal is missing or distorted, scrutinizewhether the distortion is caused by digitalencodin/decoding or an analog type distortion.Digital problems manifest themselves as blocksor sections of the picure being missing or dis-tored and portions being good. Analog distortionscould be smears or loss of detail, loss of color.The Analog Board could be loading the output ofthe Digital Board. Open the connection to theaudio board to separate where the problem is.Un loaded the Video signal should be 2Vp-p. Ifthe problem is on the Digital board. and, theproblem is in playback, the problem is likly in theHost decoder or its support circuitry. It receivesthe Signal directly from the BE and supplies theVideo to the Analog Board.
If the unit plays back properly, use the recordmode to troubleshoot. Most of the playback cir-cuitry is in operation as well. The output of theVSM supplying the BE is in the middle of the cir-cuitry on the Digital Board. Check the DigitalVideo stream here. If it is not present, check forit going to the Empress. If it is there, the probleminvolves the Empress and/or the VSM. If the sig-nal is not present on the inputs to the Empress,check the inputs to the VIP. If the signals arethere, stay on the Digital Board, checking forproblems with the VIP and/or the Empress. If thesignals are not coming into the VIP, the problemis on the Analog Board. For all of these checksyou are looking for clean digital transitions of thesignal.
VN04
UART3 of the Microcomputer communicates tothe System Control Microcomputer. It producesreset for the BE. If you are concerned with “NoPower” and the SMPS is functioning, go to theNo power part of this write up where all the cir-cuits involved in power up will be discussed. Fordigital signal path troubleshooting, proceed tothe next paragraph.
Close scrutiny of the symptom is necessary. Ifyou are considering the problem to be on the
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Digital Board, you have basic operation of theunit. The unit powers up. The Front Panel’s dis-play is proper. The unit will try to play a disc. Thesymptom involves: no menu, no playback Videoor Audio, no record Video or Audio, or scrambledVideo or Audio. If you can play a known gooddisc, you can eliminate half of the circuitry in theDigital Signal Processor. If you see the Videoand Audio during the record process, the DigitalBoard is probably not where your problem is.The parallel loop thru condition that occurs dur-ing record utilizes most of the circuitry on theDigital Board and the Analog Board.
If the problem is apparent in playback, use play-back for troubleshooting. Use a disc that has colorbars recorded on it. Check the CVBS signalon the output on Pin 11 of 1904. The bars signalallows you to closely scrutinize the signal on theoutput. If the signal is good, follow the signalthrough the Analog Board to the output jacks.If the signal is missing or distorted, scrutinizewhether the distortion is caused by digitalencodin/decoding or an analog type distortion.Digital problems manifest themselves as blocksor sections of the picure being missing or dis-tored and portions being good. Analog distortionscould be smears or loss of detail, loss of color.The Analog Board could be loading the output ofthe Digital Board. Open the connection to theAnalog Board to separate where the problem is.Unloaded the Video signal should be 2Vp-p. Ifthe problem is on the Digital Board, and theproblem is in playback, the problem is likely inthe Microcomputer or its support circuitry. Itreceives the signal directly from the BE and sup-plies the Video to the Analog Board. Replace theDigital Board.
If the unit plays back properly, and doesn record,the problem is likely on the Digital Board.Replace the Digital Board.
The Analog Board
The Analog Board can display many symptoms.There are three main categories to considerwhen looking for a problem on the Analog Board:
no Power, one or more function inoperative, or aVideo/Audio switching problem. If you are work-ing with a No Power problem, go to the NoPower portion of this write up. If you are workingwith a single function that is not operative, tracethe control of the function to the System ControlIC. For a Video/Audio routing issue, continuewith the next paragraph.
It has many inputs and outputs. It contains theTuner and Modulator functions. It D to A and A toD converts the Audio. Symptoms for this modulewill be: one or more type of output is missing, orthe Tuner does not function properly. Each of theinputs and outputs have separate paths in andout of the module. They all, however, passthrough the massive switch, IC7408. The key toan input/output problem will be determiningwhich inputs and outputs are affected. If it is asingle signal, follow that line through the circuitryto determine where the signal stops. If more thanone signal or all the signals are not passingthrough the board, 7408 is the place to start.
Tuner problems
This symptom involves two major components,the Tuner and the Demodulator IC7600. Tunerproblems fall into two categories: no Tuner func-tion or erratic Tuner function.
No Tuner FunctionsAs with any circuit, verify the 2 supply voltages.The 33Vdc supply is used exclusively by theTuner. Check for the presence of the I2C Bus onthe Tuner. This signal controls the operation ofthe Tuner. If those two conditions are met, thereshould be video on Pin 24 and IF going to theSound IF IC. If audio is a problem, provide asubstitute IF signal to check the Demodulator IC.If substitution shows the Demodulator is good,replace the Tuner. If no substitution is available,Noise can be introduced into the IF signal path.The Sound IF should amplify noise in the output.
Erratic Tuner FunctionProblems described here usually are: the Tunerdrifts or won’t lock in, certain bands of the Tunerdo not function. or, the picture is snowy. Slow
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lock in or continuous hunting for lock in is usuallyinternal to the RF Unit. In rare cases, the AFCsignal coming from the System Control. It wouldbe rare for the Microcomputer to be the cause.Check the Video input to the Microcomputer. it isprobably distorted, causing the Microcomputer tolock in incorrectly.
Audio selection problem.This type of problem will involve 7501. Check forthe control voltages on Pins 9 and 10. Monitorthem and select different inputs to be sure theychange as you make selections. Check for theoutput signals on Pins 3 and 13. If they are pre-sent check for the serial data coming from the Ato D converter. If the signal is at the output theproblem is on the Digital Board. If not Check theA/D. Be sure the PWSWON control voltage andsupply voltages are present. If they are finecheck the incoming clock on Pin 8. If they arepresent then the IC is bad.
Audio Playback problemThis type problem will also include Power OnStandby Audio. Check for the Audio at the inputto the Op Amps 7002. If it is present, check foraudio on the audio jacks. If it is not there, checkfor the Mute control voltage on the bases of7509 and 7511. If there is no signal on the out-puts of the Op amps, the Op amps are bad, orthe Mute transistors are active or shorted. If theAudio is present on the Outputs, the signalneeds to be traced through the Sound IF. The IFselects and combines the audio. Check for theaudio on the output of the Sound IF. If it is nothere, and all other functions of the Sound IF areworking, replace the IC. If it is here, the RF Unitis bad.
Basic Engine
If the PSEN signal is not present, there is aproblem in the BE that will interfere with the unitpowering up. Other symptom caused by the BEcan be playability and recording Problems.
No power up involves the MACE3Microcomputer. It is the System Control for theBE. Like any microcomputer, first check the sup-
plies, the Oscillator, and the Reset to the IC.Then check for a signal on the SUR line. It Is theServo Unit Ready. A clear to send clock signal isis seen after the MACE3 checks its memory.After the Tilt Motor vibrates it goes High duringStandby. If it doesn’t go High, the MACE3, theSRAM, or the Flash Rom are bad. If the MACEoscillator is present, at least part of the chip isfunctioning. Check for data on the Flash ROM. Itis read first. If there is activity, suspect theSRAM. If there is no activity on the FLASH sus-pect the Flash ROM as bad.
If the Symptom has in the display three wordsrepeating” Opening, Closing, Blocked”, the prob-lem is likely the OPU. Those three words couldappear when a tray motor problem is occurring,however, the OPU is a much more commonoccurrence.
There are many symptoms that involve playabili-ty, and recordability. Most common is that theunit will not recognize a disk, or a certain type ofdisk. Sometimes the symptom is that the unitwrites or reads for only a few minutes then anerror is shown in the display. Another is that theunit has a problem during the Menu update. Allof these symptoms and more are usually causedby a bad DVDM.
Edit Problems and Chapter problems have twoissues to be resolved. One is the software.There have been many updates to the Systemsoftware. Many of the updates were designed tofix those kind of issues. FF13g is the current ver-sion to be loaded. It is found on update disc ver-sion 6.1 If the Software upgrades does not fixthe problem, It is likely the OPU is the problem.
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1394 IEEE Serial Digital video and audio transfer protocol8SC2 Control voltage used by units having a SCART connector. Non U.S. +12V +12V Power Supply+2V5_FLI +2V5 Power Supply for Line Doubler and SDRAM+2V5_PLL +2V5 Power Supply for PLL+3V3 +3V3 Power Supply+3V3_ANA +3V3 Power Supply Analog+3V3_DD +3V3 Power Supply Digital+3V3_DLY +3V3 Power Supply for IC7500+3V3_DV +3V3 Power Supply for IC7404+3V3_FLI +3V3 Power Supply for FLI+3V3_FPGA +3V3 Internal Power Supply for IC7303 +3V3_FPGA_CONF +3V3 Power Supply for IC 7300+3V3_IEEE_A +3V3 Digital Power Supply for PHY IC 7101+3V3_IEEE_PLL +3V3 PLL Power Supply for PHY IC 7101+3V3_LINK +3V3 Power Supply IC7103+3V3_PLL +3V3 Power Supply IC7307 & IC7308+3V3_SRAM +3V3 Power Supply +3VREG +3Vdc Standby+5V +5V Power Supply+5V_BUFFER +5V Power Supply for Video Filters+5V_PROC +5V Power Supply IC7200, IC7201, IC7203 & IC7208+VCC_DV_RAM +3V3 Power Supply for DV_RAM (IC7400—> IC7404)1394_RSTN Reset of LINK IC (7103) and PHY IC (7101) 5508_HS Horizontal Synchronization from Host Decoder to Progressive Scan5508_ODD_EVEN Odd - Even control from Host Decoder to Progressive Scan-5V -5V Power Supply-5V_BUFFER -5V Power Supply for Video Filters+35V_DV_EDO +3V3 Power Supply EDO Bus IC7404 A (0:8) Address linesA1, A2 Power Calibration maximum and Minimum signalsA_EMPRESS (13:0) EMPRESS Address Output to SDRAMA_YCVBS Selected Luminance or Composite Video sent to the Digital BoardACC_ACLK_OSC Audio Clock PLL Output syncronized with incoming Video for recordACC_ACLK_PLL Audio Clock PLL Output for play backACLK_EMP EMPRESS Audio Clock OutputAD_ACLK Audio Decoder ClockAD_BCLK Audio Decoder I2S bit ClockAD_DATAO Audio Decoder Output Data (PCM)AD_SPDIF33 Audio Digital Output to the Analog BoardAD_WCLK Audio Decoder I2S Word ClockADIP Address in PregrooveADC Analog to Digital ConversionAE_ACLK Audio Encoder ClockAE_ACLK_OEN Audio Encoder Clock Output EnableAE_BCLK Audio Encoder I2S bit Clock
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List of Abbreviations
AE_BCLK_DV Audio Encoder I2S bit Clock to DVIOAE_BCLK_VSM Audio Encoder I2S bit Clock to VSMAE_DATAI Audio Encoder Input Data (PCM)AE_DATAI_DV Audio Encoder Input Data (PCM) from DVIOAE_DATAO Audio Encoder Output Data (PCM)AE_WCLK Audio Encoder I2S Word ClockAE_WCLK_DV Audio Encoder I2S Word Clock to DVIOAE_WCLK_VSM Audio Encoder I2S Word Clock to VSMANA_WE Analog Write Enable DecoderANA_WE_LV Analog Write Enable Low VoltageAUD_BCLK Audio Bit ClockAUD_MUTE Audio MuteAUD_SDI Audio Serial Data InputAUD_SDO_CON Audio Serial Data Output to buffer IC 7505AUD_SDO_DAC Audio Serial Data Output to DAC IC 7506AUD_WS_701 Audio Word Select to DV CODEC IC 7404AUD_WS_OUT Audio Word Select to buffer IC 7505AFCLI Audio from the Front connector Left InputAFCRI Audio from the Front connector Right InputAFEL Audio from the Front End LeftAFER Audio from the Front End RightAINFL Audio In Front LeftAINFR Audio In Front RightAKILL Control voltage for Mute circuitALADC Audio Left from the Analog to Digital ConverterALDAC Audio Left from the Digital to Analog ConverterAMCO Audio to the RF Modulator Combined OutputARADC Audio Right from the Analog to Digital ConverterARDAC Audio Right from the Digital to Analog ConverterASC1M Control voltage used by units having a SCART connector. Non U.S. AWSOME Adip decoding Wobble processing Error correction Synchronous
start/stop and Occasionally Mend Errors B_IN_VIP Video Blue Input to Video Input ProcessorB_OUT Video Blue Output from Host B_OUT_B Buffered Blue Video Output BA Bank AddressBCLK_CTL_SERVICE Bitclock control Service InterfaceBE_BCLK Basic Engine I2S bit ClockBE_BCLK_VSM Basic Engine I2S bit Clock to VSMBE_CPR Basic Engine Control Processor ready to accept DataBE_DATA_RD Basic Engine Data ReadBE_DATA_WR Basic Engine Data WriteBE_FAN Basic Engine FANBE_FLAG Basic Engine error FlagBE_IRQN Basic Engine interrupt requestBE_LOADN Basic Engine LOAD (LOW active)BE_RXD Basic Engine S2B received DataBE_SUR Basic Engine Servo Unit Ready to accept Data (S2B)
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BE_SYNC Basic Engine sector/abs time SyncBE_TXD Basic Engine S2B transmitted DataBE_V4 Basic Engine versatile Input pinBE_WCLK Basic Engine I2S Word ClockBE Basic Engine/Mechanism-Servo BoardBUFENN_AUD Buffer Enable Audio BUFENN_VID Buffer Enable VideoC_IN Video Chrominance InputC_IN_VIP Chrominance Input to Video Input ProcessorC_OUT Chrominance Output from Host DecoderC_OUT_B Filtered Chrominance OutputCALF Laser Calibration Final voltageCAS Column Address strobeCAV Constant Angular VelocityCB_OUT (9:0) Digital Chrominance Blue Out. One of Y, Cr/Cb CCIR656 Serial Digital Video transfer Protocol. It is widely used having many
resolutions CCLK Configuration ClockCFIN Chrominance Front Input signalCinch Standard Video and Audio connectorCLK4 SDRAM ClockCLK27M 27MHz ClockCLK27M_CON 27MHz Clock to Digital BoardCLK27M_DV 27MHz Clock Digital Video CodecCLK27M_OSC\ 27MHz Clock IC7304CLOCKGENAUD Clock generator AudioCLOCKGENVID Clock generator VideoCLV Constant Linear VelocityComPair Computer aided rePairCosphi Cosine Position of Hall infoCPUINT0 Control Processor Unit Interrupt CPUINT1 Control Processor Unit Interrupt CPR Control Processor ReadyCR_OUT (9:0) Digital Chrominance Red Out. One of Y, Cr/CbCS Chip SelectCSW_SWW Channel Select Switch control voltageCTS1P Clear to send (Service Interface)CTSN Clear to SendCVBR CD Variable Bit Rate recordingCVBS_OUT Composite Video Output out of the Host DecoderCVBS_OUT_B Buffered Composite Video OutputCVBS_OUT_B_VIP Composite Video to Video Input Processor (Digital Board Video loop)CVBS_Y_IN Composite Video/Luminance InputCVBS_Y_IN_A Composite Video/Luminance Input to Video Input ProcessorCVBS_Y_IN_B Composite Video/Luminance Input to Video Input ProcessorCVBS_Y_IN_C Composite Video/Luminance Input to Video Input ProcessorCVBSFIN Composite video Front Input signal.D_ADDR (10:0) Address busD_CVBS Composite Video coming from the Digital Board
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D_DATA (29:0) Data busD_EMPRESS (15:0) SDRAM Data Input/Output of EMPRESSD_PAR_D (7:0) Front-end parallel interface Data (record)D_PAR_DVALID Front-end parallel interface Data validD_PAR_REQ Front-end parallel interface requestD_PAR_STR Front-end parallel interface strobeD_PAR_SYNC Front-end parallel interface SyncDAC Digital to Analog ConverterDAIO Digital Audio Input/OutputDAOUT Digital Audio OutDATA Data from config ROMDeinterlacer Converts interlaced video to progressive scan. Line DoublerDENC Digital EncoderDFU Direction For Use: description for the end userDNR Dynamic Noise ReductionDONE Indication of the completion of the configuration processDOUT Serial configuration Data OutputDRAM Dynamic RAMDROPPI DVD Rewriteable OPU Pre-Processor ICDSD Direct Stream DigitalDSP Digital Signal ProcessorDV_ASN DVCODEC Address StrobeDV_DRQN DVCODEC Data Request InterruptDV_DSLN DVCODEC Data Strobe Lower 8 bitsDV_DSUN DVCODEC Data Strobe Upper 8 BitsDV_DTACKN Data Transfer AcknowledgeDV_ERRN DVCODEC Error InterruptDV_HS_IN DVCODEC Horizontal synchronization InDV_HS_OUT DVCODEC Horizontal synchronization OutDV_IN_CLK Digital Video IN Clock from DVIO BoardDV_IN_DATA (7:0) Digital Video IN Data bus from DVIO BoardDV_IN_HS Digital Video IN Horizontal Synchronization from DVIO BoardDV_IN_VS Digital Video IN Vertical Synchronization from DVIO BoardDV_LCN DVCODEC Last Code InterruptDV_PDN DVCODEC Power DownDV_RSTN DVCODEC System Reset for NW701DV_RWN DVCODEC Read/Write control signalDV_VS DVCODEC Vertical synchronizationDVCODEC Digital Video enCODing and DECoding protocol.EFM Eight to Fourteen bit ModulationEMI_A (21:1) External Memory Interface Address Bus (Host Decoder)EMI_BE0N External Memory Interface Lower byte Enable (Host Decoder)EMI_BE1N External Memory Interface Upper byte Enable (Host Decoder)EMI_CAS0N External Memory Interface SDRAM column Address strobe EMI_CE1N External Memory Interface VSM Lower bank EnableEMI_CE2N External Memory Interface VSM Higher bank EnableEMI_CE3N External Memory Interface flash IC’s EnableEMI_D (15:0) External Memory Interface Data Bus (Host Decoder)EMI_PROCCLK External Memory Interface Processor Clock (Host Decoder)EMI_RAS1n External Memory Interface Row Addres Strobe bank 1
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EMI_RWN External Memory Interface Read/Write control signal (Host Decoder)
EMI_WAIT External Memory Interface Wait state request (Host Decoder)EMPRESS_BOOT EMPRESS BOOT select InputEMPRESS_IRQN EMPRESS Interrupt request OutputEPG Electronic Program GuideFBIN Fast Blanking IN. Used by units having a SCART connector.FDS Full Diagnostic SoftwareFIFO First In First Out memoryFIFOA_A (0:15) FIFO buffer A Address busFIFOA_OEN FIFO buffer A Output EnableFIFOA_WEN FIFO buffer A Write EnableFIL1 Filiment supplyFIL2 Filiment supplyFLASH_OEN FLASH Output Enable control signalFOME FOllow ME. Used in units having a SCART connector. FPGA Field Programmable Gate ArrayFTC Fast Track CountG_IN_VIP Video green Input to Video Input ProcessorG_OUT Video green Output from Host DecoderG_OUT_B Buffered Green Video Output from Host DecoderGNDD Digital signal GroundHD_M_AD (13:0) Host Decoder SDRAM Address busHD_M_CASN Host Decoder SDRAM column Address strobeHD_M_CLK Host Decoder SDRAM ClockHD_M_CS0N Host Decoder SDRAM chip selectHD_M_DQ (15:0) Host Decoder SDRAM Data busHD_M_DQML Host Decoder SDRAM Data mask Enable (Lower)HD_M_DQMU Host Decoder SDRAM Data mask Enable (Upper)HD_M_RASN Host Decoder SDRAM row Address strobeHD_M_WEN Host Decoder SDRAM write EnableHF High Frequency/signal from the discHSOUT Horizontal synchronization OUTI2C Serial communication protocolI2S Integrated IC Sound Buss (3.3V High)INITN Initiate ConfigurationINT Interupt - Front Panel Microcomputer signifying to System Control
Microcomputer keyboard input data receivedIO (0:30) Data bus of IC7404IOE Input Output Extention only used in certain modelsION Inverted ON: Enable the power Supply for the Digital Board when LOWIPFAIL Interupted Power Failure response signalIPOR Inverted Power On ResetIRESET_DIG Initialization of the Digital Board, HIGH when power ONISPN In System Program Line (used for programming IC7203)JTAG3_TCK JTAG Test ClockJTAG3_TD_VIP_TO_VE JTAG Transmitted Data Video Input Processor to Video EncoderJTAG3_TD_VSM_TO_VIP JTAG Transmitted Data Versatile Stream Manager to Video Input
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ProcessorJTAG3_TMS JTAG Test Mode SelectJTAG3_TRSTN JTAG Test part ResetNLADIC LAser Drive ICLCASN Lower Column Address strobe for IC7404 DRAMSLDON Laser Drive OnLEVELSW Control Voltage used in units having a SCART connector. Line Doubler Converts Interlace Scan, NTSC, to Progressive ScanLINK_AVCLKLINK IC Audio/Video Interface ClockLINK_AVFSYNC LINK IC Audio/Video frame SyncLINK_AVREADY LINK IC Audio/Video Data ready to sendLINK_AVSYNC LINK IC Audio/Video packet SyncLINK_AVVALID LINK IC Audio/Video Data validLINK_CSN LINK IC chip selectLINK_INTN LINK IC interruptLINKFIFO_DQ (0:7) Audio Video Data interfaceLLD Loss Less DecoderLLP Laser Low PowerLOAD_DVN LOAD Digital Video (LOW active)LPCM Linear Pulse Code ModulationLRCLK Left/Right ClockMACE Mini All CD EngineMpeg Motion Picture Experts Group (compression scheme)MUTEN Mute Enable MUTEN_LV Mute Enable Low VoltageNVM Non Volatile MemoryOPC Optimum Power CailibrationORD Radial Drive disableOPU Optical Pickup UnitP_SCAN_YUV (7:0) Progressive Scan Digital Video busP50 Control Voltage used in units having a SCART connector.PA (0:15) SRAM processor AddressPCS Position Control SledPCM Pulse Code ModulationPOR_DC Power On ResetPPN Wobble Pre-Processor signalPPNO Wobble Pre-Processor signal Output signalPWRN Processor writeSYSCLK_VSM_5508 System Clock VSM and Host decoderPAD (0:7) SRAM processor DataPALE Processor Address Latch EnablePHY_CAN PHY 1394 cable not activePHY_LPS LINK IC power statusPINT0N Processor interrupt 0PINT1N Processor interrupt 1PRDN Processor readPROGRAMN Low active Input to initiate a configuration cyclePRSTN Processor resetR_IN_VIP Video Red Input to Video Input ProcessorR_OUT Video Red Output from Host Decoder
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R_OUT_B Buffered Red Video Output from Host DecoderRAS Row Address StrobeRASN Row Address strobe EnableRefsin Reference voltage for Hall sensor ampRefcos Reference voltage for Hall sensor ampRESETN Reset Host Decoder, VSM, and DENCRESETN_BE System reset basic engine (buffered)RESETN_DVIO System reset Digital Video Input Output (buffered)RESETN_VE System reset Video EncoderROMH_CEN Flash 2 chip EnableROML_CEN Flash 1 chip EnableRSA1 Control voltage for Audio input selectionRSA2 Control voltage for Audio input selectionRSTN_BE Reset control of basic engineRSTN_DVIO Reset control of DVIORSTAT Status ReadRTS1P Ready To Send Data to service serial interfaceRTSN System ResetRXD Receive DataRX1P Receive Data from service serial interfaceS2B Serial to Basic Engine CommunicationSCL I2C bus ClockSCLSW I2C bus Clock with its dc level switchedSD_CASN SDRAM Column Address strobe Output (active LOW)SD_CLK SDRAM Clock OutputSD_CLKE SDRAM Clock Enable OutputSD_CSN SDRAM Chip Select SD_DQM (1:0) SDRAM Data mask Enable OutputSD_RASN SDRAM Row Address strobe OutputSD_WEN SDRAM Write Enable OutputSDA I2C bus DataSDASW I2C bus Data with its dc level switchedSEL_ACLK1 Select Audio Clock (playback)SDRAM Synchronous DRAMSinphi Sine Positionof Hall infoSM_CS3N SRAM chip selectSM_LBN SRAM lower bank strobeSM_OEN SRAM Output EnableSM_UBN SRAM upper bankSM_WEN SRAM write EnableSMA (17:0) SRAM Address OutputSMD (15:0) SRAM Data Input/OutputSPDIF Sony Philips Digital Interface for AudioSPIDRE Signal Processing IC for DVD REwritableSRAM Static Random Access MemorySRAMCE0N SRAM processor chip Enable 0SRAMRDN SRAM processor Output EnableSTBY Control voltage Turns On the 5SW and 8SW supplies
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SVCD Super Video CDSubcode Tacking information/Track number/and disc location informationSYSCLK_EMPRESS System Clock EMPRESSSYSCLK_PROGSCAN System Clock Progressive ScanSYSCLK_VSM_5588 System Clock for the VSM and the Host DecoderTCK Boundary scan Test ClockTemp Sensor Temperature sensor’s output signalTDI Boundary scan Test Data InputTDO Boundary scan Test Data OutputTDO_CONF Boundary scan Test Data Output from IC 7309TLL Track Loss signalTMS Boundary scan Test Mode SelectTPI Track Position IndicatorTX1P Transmit Data to service serial interfaceTXD Transmitted DataU_IN Video U InputU_IN_VIP Video U Input to Video Input ProcessorUCASN Upper column Address V_IN Chrominance V InputV_IN_VIP Chrominance V Input to Video Input ProcessorVBR Variable Bit Rate recordingVCC3_CLK_BUF Power Supply 3V3 Clock bufferVCC3_VSM Power Supply 3V3 Versatile Stream ManagerVCC3_VSM_MEM Power Supply 3V3 Versatile Stream Manager MemoryVCC5_4046 Power Supply 5V to PLL ICVDD_125 Power Supply 5V to buffer 7202VDD_CORE Sti5508 Core Supply voltage 2.5VVDD_EMP Empress Supply voltage 3.3VVDD_EMP_CORE Empress Core Supply voltage 2.5VVDD_FLASH_H Flash 7301 Supply voltageVDD_FLASH_L Flash 7302 Supply voltageVDD_LVC32 Power Supply LVC32VDD_PCM Power Supply Audio decoder of Sti5508VDD_PLL Power Supply PLL Audio decoder of Sti5508VDD_RGB Power Supply Video encoder of Sti5508VDD_STI Power Supply of Sti5508 and SDRAMVDD_YCC Power Supply Video encoder of Sti5508VDD5_MK2703 Power Supply MK2703VDD5_OSC Power Supply OscillatorVDDA1A_7118 Power Supply for Analog Input of VIPVDDA2A_7118 Power Supply for Analog Input of VIPVDDA3A_7118 Power Supply for Analog Input of VIPVDDA4A_7118 Power Supply for Analog Input of VIPVDDE_7118 Power Supply Digital for peripheral cells of VIPVDDI_7118 Power Supply Digital for core of VIPVDDX_7118 Power Supply for crystal oscillator of VIPVE_DATA (7:0) Video Encoder Data BusVE_DSn Video Encoder Data StrobeVE_DTACKn Video Encoder Data Transfer acknowledgeVGNSTBY Negative Supply for the Grids of the Flouresent display
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Written by Dan Crum Mar. 2004Version 2
