1Colour television Chassis

5

4822 727 21613Published by TG9866 Television Service DepartmentPrinted in The Netherlands 5 4822 727 21613

Copyright reserved 1998 Philips Consumer Electronics B.V. Eindhoven, TheNetherlands. All rights reserved. No part of this publication may be reproduced,stored in a retrieval system or transmitted, in any form or by any means, electron-ic, mechanical, photocopying, or otherwise without the prior permission of PhilipsTraining Manual

A8.0A

ContentsIntroduction 2Mechanical 3Control 9Power supply 24Video processing 34Synchronization 52Audio processing 54Horizontal deflection 60Vertical deflection 80Teletext + On-Screen Display 83Widescreen view modes 89

Published by TG9866 Television Service Department

Printed in The Netherlands

Copyright reserved 1998 Philips Consumer Electronics B.V. Eindhoven, The Netherlands. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted, in any form or by any means, electronic, mechanical, photocopying, or otherwise

without the prior permission of Philips

2 INTRODUCTION A8.0ABlock diagramINTRODUCTION Block diagram

The power is supplied by an SMPS (Switch Mode PowerSupply) creating the deflection power supply voltage (+140V), the sound power supply voltage (+15V) and anumber of low voltages (+14V, +8v, +5v and+5vSTANDBY).

The controls located on the mono carrier are activated bythe keyboard and RC5 signals from the remote control re-ceiver. The internal control is via I2C.

The TUNER transmits an IF video signal on 38.9 MHz to theTDA884x (IC7150). In this IC the video processing(PAL,NTSC and SECAM) and synchronization along withthe geometrical alignments are implemented.

Sound decoding is performed in the sound processing partwhich can be BTSC dedicated (TDA9855) or multi standard(MSP3410) (mono, stereo, nicam).

In some stereo sets (mainly NICAM and FM DK) the QSSpanel (Quasi Split Sound) will be applied to improve the SIFsignal

The CRT-panel contains integrated RGB amplifiers andSCAVEM circuitry. The RGB signals are then transmitted tothe picture tube via the RGB amplifiers.

The horizontal and vertical deflection signals (line andframe) are amplified in the driver stages, which drive the de-flection coils.

In all sets except 21" E/W correction is needed which is ac-commodated on a separate panel. For 16:9 sets the pano-rama circuitry is also accommodated on this panel

1125TUNER

7150-AIF

IOPANEL

SOUNDPROCES-

SING

LINEDRIVE

EW+PANORAMA

PANEL

FRAMEAMPLIFIER

YC PIPPANEL

COMBFILTERPANEL

7150-0VIDEO

PROCESSING

7150-CRGB

PROCESSINGRGB AMPSCAVEM

DW PANEL

RGBSWITCH

OSD/TXT

CONTROLS

YUVPANEL

TOPCONTROL

PANELAUDIO

AMPLIFIER

LOT

QSSPANEL

7150-DSYNC

SUPPLYSMPS

I2C

+140+33+14+8+15+5+5 - STBY

SIF

AM

Y C Y C

Y/CVBS Y Y

C CUV

Y U V VY U

RGB

220V

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Personal notes

A8.0A Mechanical 3Chassis Set-upMechanical Chassis Set-up

(The A8 has a mono carrier and panels for East West, I/OSCART/Cinch, Side AV, QSS, Teletext, Mains filter and TopControl.

The mono carrier is a double sided panel with SMDs at thesolder side. It accommodates: the control part video signal processing source select(front/rear) IF sound processing audio amplifier horizontal and vertical deflection power supply front control(IR, LED) teletext in the micro-processor.

Different panels can be placed on the mono carrier: QSS panel YUV panel COMB. Filter panel E/W Panel OSD panel incredible sound panel

Loose panels are Top Control panel Side AV panel Mains filter panel

I/O panel. PIP panel/ DW panel The CRT panel (contains the RGB amplifier circuit and

SCAVEM)

G

R

SIDE AV PANEL

COMB. FILTER PANEL

CRT PANEL

TOP CONTROL PANELN

B

J QSS-DK PANEL

QSS (BGLI NICAM)

T PIP PANEL

EAST WEST PANEL

YUV PANEL

INCREDIBLE SOUND PANEL

H

S OSD

I

MAINS FILTER PANEL

A15FRONT CONTROL

C

E I/O CINCH PANELA14FRONT AV

A13IO SWITCHING

A12AUDIO OUTPUT

A11AUDIO PROCESSING NICAM/2CS/FM/AM

A10AUDIO PROCESSING BTSC

A8CONTROLS

A7RGB PROCESSING

A6SYNC

A5VIDEO PROCESSING

A4TUNER + VIF

A3VERTICAL DEFLECTION

A2HOR. DEFLECTION + LINE OUTPUT

A1POWER SUPPLY

Q

M

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4 Mechanical A8.0ARemoving the separate mains filterRemoving the separate mains filter

In order to remove the rear cover from the A8, all screws at theside, the bottom and the top of the rear cover have to be re-moved. The screws near the I/O cinch connectors should NOTbe removed.

CAUTION!

Remember to disconnect the subwoofer connector !!

Unplug the mains cord before working on the separate mainsfilter; the separate mains filter carries permanent mains voltage(even when the mains knob is switched OFF).

Disconnect the separate mains filter panel

To disconnect the separate mains filter bracket from the chas-sis tray:

firmly depress the click (with a screwdriver) in the chassistray (1)

push the mains filter bracket in the direction of the CRT

Remove the separate mains filter panel

To remove the separate mains filter panel from its bracket:

push the 2 clips at the right hand side of the mains filterbracket outside (2)

lift the panel from its bracket

2

1

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A8.0A Mechanical 5Removing the chassisRemoving the chassis

Service position without the need for a large table or workbench

To remove the chassis tray from the cabinet:

disconnect the degaussing coil (connector M16 on themono carrier)

pull the clips (1) backwards and pull the chassis tray as in-dicated (2)

The chassis tray should be turned 90 degrees counter clockwise and flipped over to access the copper side of the monocarrier.

1

1

2

M16

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Personal notes

6 Mechanical A8.0AEnvironment independent positionEnvironment independent position

For home repair the chassis tray with mono carrier can be fixedin the cabinet.

turn the chassis tray 90 degrees counter clock wise (1) flip the tray with the I/O panel towards the CRT (2) press (the hook of) the chassis tray firmly into the designat-

ed hole in the cabinet bottom (3) and pull the chassis trayforward (the speaker cables may have to be disconnected)

3

2

1

BA

IO PANEL

BRACKET

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Personal notes

A8.0A Mechanical 7Accessing the I/O panelAccessing the I/O panel

To access the copper side of the IO panel:

push the clips (1) in the direction of the CRT (If the clips arebroken, the I/O panel can also be screwed to chassis tray)

slide the I/O panel bracket (2) to its horizontal position

To remove the I/O panel from its bracket:

remove the 2 screws on the connector side of the panel (3)and (4).

44

2

1

3

(4X)

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Personal notes

8 Mechanical A8.0ARepairing the mono carrierRepairing the mono carrier

For full access to the component and copper side of the monocarrier, it can be removed from the chassis tray.

push the clicks of the chassis tray outwards (1) lift the mono carrier from the tray (2).

1

2

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Personal notes

A8.0A CONTROLS 9User MenuCONTROLS User Menu

The complete control of TV sets with a A8 chassis is performedvia menus. Selections within the menus are made by the arrowkeys on the remote control (cursor control).

On the remote control the "smart controls" for picture andsound are present. Pressing one of these buttons will give apre-programmed change of various audio or picture settings atthe same time.

1

3

4

5

7

8

9

10

11

2

6

MENU SURF

SMARTSMART

CH

5

2

4

7 8

0

1

6

3

9

AV

A/CHGAMEINCREDIBLEINC. SURR.

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Personal notes

10 CONTROLS A8.0AInstallationInstallation

Installation of the A8 can be done via the installation menu orvia the Dealer Service Tool (DST);

1. With the Installation-menu the installation of the TV can beperformed in two ways: Automatic: The complete TV band is searched and all

transmitters are installed. Manually: The frequencies have to be given for all pro-

gram numbers.

2. With the RC7150 Dealer Service Tool (DST) The RC7150 can install a complete TV program table in

a single operation.

Installation

AutomaticManuallyDST (RC7150)

Personal notes

A8.0A CONTROLS 11Dealer Service Tool (DST)Dealer Service Tool (DST)

The dealer service tool (DST, RC7150) is a remote control, es-pecially developed for the dealer and service engineer.

Dealer functions With the DST complete program tables can be transmit-

ted to the TV. 10 different tables can be stored in theDST, e.g. for 10 different areas.

Programming tables into the DST can be performed in twoways:

From the TV (GFL only). If a GFL TV is installed with a com-plete table of program information the complete table canbe transmitted to the DST. As use is being made of the deal-er link, the DST must be held at a short distance(within 10cm) from the IR transmitter LED (next to the stand-by led).

With a DST interface (22AV1376). This is a computer inter-face that can be used with the accompanying computer pro-gram to input tables in the computer and transmit thesetables to the DST.

Service features of the DST for the A8 Activating the Service Alignment Mode. By pressing the

"ALIGN" key on the DST the Service Alignment ModeSAM) is activated.

Activating Service Default Mode. By pressing the "DE-FAULT" key on the DST the Service Default Mode(SDM) is activated.

Downloading program tables from DST into the TV.

RC7150Service Features

-

-

Entering the Service Alignment Mode

Entering the Service Default Mode

Defined settings for tuning and control

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Personal notes

12 CONTROLS A8.0AService Default Mode (SDM)Service Default Mode (SDM)

Entering the Service Default Mode (SDM): By transmitting the "DEFAULT" command with the RC7150

Dealer Service Tool. By shorting the jumpers 9040 & 9041 while switching on the

set with mains switch.

Exiting the Service Default Mode (SDM):

Switch the set to stand-by (the error buffer is also cleared)

Specification of the Service Default Mode (SDM)Default values of the following must be set according;

Tune to 475.25MHz. PAL/Secam sets Tune to channel 3 (61.25 MHz) for NTSC sets All linear setting at 50%, except volume at 25% Disable service unfriendly modes;

Timer Off Sleeptimer Off Hospitality disabled No-ident timer disabled Parental lock disabled

The default system (for multi system sets) will be set ac-cording to the signal source input at the antenna.

SERVICE DEFAULT MODE

Tuner tuned to 475.25 MHz

-

-

Shortcircuit 9040 & 9041 on the SSP

Press the "default" key on the RC7150

All linear settings in "mid" position

Volume set to "low"

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Personal notes

A8.0A CONTROLS 13Service Default Mode (SDM)Service Default Mode (SDM)

Others features of SDM

Error codes OSD can be switched on and off with OSD but-ton

Switch to user menu by pressing MENU button LED blinks with info of the error in error buffer Start channel search by pressing "P+" button on the remote

control

P I C T U R E B R I G H T N E S SS O U N D C O L O U RF E A T U R E S C O N T R A S TI N S T A L L S H A R P N E S S

C O L O U R T E M P

S A M

S D M

S D M

E R R n n n n n n n n n n n n

SDM Menu

MENU+

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Personal notes

14 CONTROLS A8.0AService Alignment Mode (SAM)Service Alignment Mode (SAM)

Entering the Service Alignment Mode (SAM During normal operation and SDM by transmitting the

"ALIGN" command with the RC7150 Dealer Service Tool. By pressing and holding VOL+ & VOL- keys on the local

keyboard for 2 sec. while in SDM

Specification of the Service Alignment Mode(SAM)1. Operating hour counter ( in Hexadecimal)2. Software version3. Software of separate teletext controller; NOT implemented

for A/P.4. Error code buffer (maximum the last 6 error codes5. Option bytes (7 bytes possible6. Sub menus

Erase buffer Option codes Alignments and geometry information Reload default values

Error code Description of possible defective components 0 Noerror detected - 1 EW and/or Vert protection active EW/Ver-tical circuit is defective 2 High beam protection active CRTamplifier circuit or picture tube 3 Reserved 4 5V protectionactive +5V supply line is low or short cuicuit 5 BiMOS s/w pro-tection active or BiMOS register is corrupted IC7150 6 BiMOS

IIC error IC7150 7 General IIC bus error IIC bus s/c or o/c 8Main uP Internal RAM error IC7000 9 OSD generator IIC errorIC7101 on OSD panel 10 NVM addressing error IC7088 11NVM IIC error IC7088 12 Histogram IIC error IC7770 on YUVinterface panel 13 Reserved 14 Sound processor IIC errorIC7430 (ITT) or IC7437 (BTSC) 15 Reserved 16 Main tunerIIC error U1125 17 PIP processor IIC error IC7350 on PIPpanel 18 2nd tuner PIP IIC error U1126 or U1127 on PIP pan-el 19 EPG uProcessor/Guide Plus uProcessor IIC errorIC7007 on EPG panel

IC6 on guide plus panel 20 NV-clock IIC error IC7110 21 Re-serve 22 EPG processor IIC internal RAM error IC7007 onEPG error

Exiting the Service Alignment Mode (SAM) The SAM will be left by the stand-by command. In case the

set is switched "off" and "on" again with the mains switch,the set will start up in the SDM again.

Specification of the Service Alignment Mode(SAM)1. Operating hour counter (in hexadecimal)2. Software version3. Software of separate teletext controller4. Error code buffer (maximum the last 6 error codes)

SERVICE ALIGNMENT MODE

Service Menu

- From SDM via "Vol +" & "Vol -"

S A Mn n n n A 8 0 E U 1 - 1 . 0 5 2 6 3 - 2 - 2 3

E R R n n n n n n n n n n n nO P n n n n n n n n n n n n n n n n n n n n n

R E L O A D D E F A U L TE R A S E B U F F E RO P T I O N SA L I G N M E N T S

1

6

2 3 4 5

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A8.0A CONTROLS 15Service Alignment Mode (SAM)5. Option bytes (7 bytes possible)6. Sub menus

Erase buffer Option codes Alignments and geometry information Reload default values

Error code buffer

The error code buffer is written from left to right and contains allerrors detected since the last time the buffer is erased.

An example can be:

ERROR:0 0 0 0 0 0:No error code detected

ERROR:6 0 0 0 0 0:Error code 6 is last and only detected

ERROR:5 6 0 0 0 0:Error code 6 is first detected, error code 5last detected

The last error detected (actual) is the error at the left side By leaving the SAM with the "standby" function or ERASE

BUFFER function the error buffer is reset.

Error code Error description Possible defective com-ponents

0 No error detected -

1 E/W and/or Vert. protec-tion active/X-ray protec-tion.

E/W Vertical circuit de-fective,line o/p stage.

2 High beam protectionactive

CRT amplifier circuit orpicture tube

3 Reserved -

4 5V protection active +5V supply line is low orshort circuit

5 BiMOS s/w protectionactive or BiMOS registeris corrupted

IC7150, + 8V supply.

6 BiMOS IIC error IC7150

7 General IIC error IIC bus s/c or o/c

8 Main uP internal RAMerror

IC7000

9 OSD generator IIC error IC7101 on OSD panel

10 NVM addressing error IC7088

11 NVM IIC error IC7088

12 Histogram IICerror IC7770 or YUV interfacepanel

13 Reserved -

14 Sound processor IIC er-ror

IC7430 or IC7437 (BT-SC)

15 Reserved -

16 Main tuner IIC error U1125

17 PIP processor IIC error IC7350 on PIP panel

18 2nd tuner PIP IIC error U1126 or U1127 on PIPpanel

19 EPG uP/Guide Plus uPIIC error

IC7007 on EPG panel/IC6 on Guide Plus panel

20 NV-clock IIC error IC7110

21 Reserved

22 EPG processor IIC inter-nal RAM error

IC7007 on EPG panel

Personal notes

16 CONTROLS A8.0AService Alignment Mode (SAM)Service Alignment Mode (SAM)

Alignments

Selection of the desired alignment by the up/down cursor Change of the selected alignment by the left/right cursor The following alignments are possible (alignments for ge-

ometry are for the 4:3 picture format) A value between 0 and 63 can be given for all software

alignments Important! Any changed values will only be stored if the ge-

ometry menu is exit by pressing the MENU button.

Easy way to adjust vertical geometry (4 X 3)

1. Set vert. S-correction value to 132. Set vert. zoom value to 253. Set vert. blanking to ON4. Adjust vert. slope till test pattern centre line touches the

centre edge5. Adjust vert. shift and vert. height till best fix the screen.

Service Alignment Mode

HORSHIFT: Horizontal shiftHORWIDTH: Horizontal widthSERV.BLANK: Service blankingVERSHIFT: Vertical shiftVERHEIGHT: Vertical amplitudeVERSLOPE: Vertical linearityEW PARABO: E-W parabolaEW TRAPEZ: E-W trapeziumEW CORNER: E-W cornerVER S-COR: Vertical S-correctionVERZOOM: Vertical zoom

Personal notes

A8.0A CONTROLS 17Service Alignment Mode (SAM)Service Alignment Mode (SAM)

Options

Setting of individual options. Selection of the desired "option to be changed" by the

up/down cursor. Change of the selected option (ON/OFF) by the left/right

cursor or

By keying the decimal values in the option bytes 1~7 item The options are activated immediately after they are

stored and powered up.

Reload Default

By selecting LOAD NOW, the current values stored in the nonvolatile memory will be over written. Caution: It is used onlywhen the non volatile memory data is corrupted and no otherway to recover. Default values are activated when the set is re-started

H O R S H I F TH O R W I D T HS E R V . B L A N K I N GV E R S H I F TV E R W I D T H

C O L D R n n n G n n n B n n n

P I C T U R E B R I G H T N E S SS O U N D C O L O U RF E A T U R E S C O N T R A S TI N S T A L L S H A R P N E S S

C O L O U R T E M P

S A M

S A M

L O A D N O WD O N ' T L O A D

n n n n A 8 0 E U 1 - 1 . 0 5 2 6 3 - 2 - 2 3

E R R n n n n n n n n n n n nO P n n n n n n n n n n n n n n n n n n n n n

R E L O A D D E F A U L TE R A S E B U F F E RO P T I O N SA L I G N M E N T S

O B 6O B 7S T O R EA LA K

G E O M E T R YG E O M E T R Y S WW H I T E T O N ET U N E RB T S C S O U N D

I F P L LI F P L LA G CA F AA F B

T D A 9 8 5 5

L AS AW AA A

SAM Menu

MENU

MENU

MENU

MENU

MENU

MENU

MENU

MENU

Only when HW option is present

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n n n

n n n

O NO F F

n n n

n n n

n n n

n n n

n n n

n n n

n n n

n

n

n n

n n

n n

n n n

1

6

2 3 4 5

Personal notes

18 CONTROLS A8.0AMicroprocessorMicroprocessorIntroduction

Hardware and software diversity.

Europe sets:

Master micro processor 83C770 (64k ROM). Slave micro processor on TEXT/EPG panel, dedicated for

EPG (Electronic Programming Guide) and Teletext decod-ing.

Latam and USA standard sets:

Single micro processor 83C770 (64k ROM). Complete con-trols including Closed Caption decoding.

Low end USA sets:

Single micro processor 83C570 (48k ROM).

Asia/Pacific TXT sets:

Single micro processor SAA5297(masked) or SAA5499(OTP).Complete controls TXT decoding.

Asia/Pacific NON-TXT sets:

Single micro processor 83C770 (64K ROM)

Software diversity:

Version Region

EUROPE

A8EU1.1: Western Europe without EPG

A8EU1.2 : Eastern Europe

A8EU1.3 : Western Europe with EPG

USA

A8US1.1 : USA (all)

LATAM

A8LA1.1 : LATAM (all)

Software identification of the main micro controller (A80BBC-X.Y)

A80 is the chassis name for A8.0A BBC is 2 letter and 1 digit combination to indicate the soft-

ware type and the supported languages: PN1:Pal/Multi; NO teletext; English, Malay and Chinese PN2:Pal/Multi; NO teletext; English and Hindi

PN3:Pal/Multi; NO teletext; English and Arabic PT1:Pal/Multi WITH teletext; English, Malay and Chi-

nese NG1:NTSC; 2CS sound; English and Korean NB1:NTSC; BTSC sound; English and Taiwanese

X = (main version number) Y = (subversion number)

Software identification of a separate Teletext micro controller(DDDD E FF) (not applicable for A8.0A)

NVM

The NVM used for storing the default settings is ST24W16 is 16KB and is interfaced with the main micro using the S/W I2C bus.This is to avoid any data corruption in the NVM data by control-ling the Write CLock of the NVM by the main micro.

Personal notes

A8.0A CONTROLS 19MicroprocessorMicroprocessorSoftware control lines

SOFTWARE CONTROL LINES DESCRIPTION for the mainmicro processor

Logic 0 is : 0 V

Logic 1 is : +5V

Pin 1: PAN_SWITCH/+5V_CNTRL

OUTPUT

Activates 16:9 feature (EUROPE only)

Activates+5V supply for the PIP board (USA only)

Pin 2 & 3: SYS2 and SYS1

OUTPUT

Selects the XTALS and Combfilters.

Pin 4 & 9: SEL_PIP_FRNT_RR & SEL_PIP_R1R2

(valid for PIP sets)

OUTPUTS

Selects the PIP video source from rear I/O, main or front.

Pin 5: SEL_IF_TRAP_MAIN or L/L'

OUTPUT

Select the MAIN IF TRAP and Sound Traps also.

Pin 6: POSNEG_QSS or SEL_INCRED

OUTPUT

Selects the positive and negative demodulation mode for theQSS IC during SECAM L reception (Europe only).

Selects the Incredible Stereo feature (USA only)

Pin 7: SDM

INPUT

Service Default Mode is activated by shorting this pin to GND.

Pin 8 & 14: SEL_MAIN_R1R2 &SEL_MAIN_FRNT_RR

OUTPUTS

Selects the MAIN video source from INTERNAL, FRONT orREAR.

Pin 1: PAN_SWITCH Status

0 Default

1 Super Wide Selected in 16:9 sets

Pin 1: +5V CNTRL Status

1 +5V OFF

0 +5V ON

Pin 2: SYS2 Pin 3: SYS1 System

0 0 PAL M

1 0 PAL B,G,H,I,D,K

0 1 NTSC M

1 1 PAL N

Pin 4: SEL_PIP_FRNT_RR

Pin 9:SEL_PIP_R1R2

PIP Source Selec-tion

0 0 REAR1

0 1 REAR2

1 0 FRONT

1 1 INTERNAL

Pin 5:SEL_IF_TRAP_MAIN

A/P Europe

0 ON - for NTSC M ON - for othrs

1 OFF - for others OFF - SECAM L'

Pin 6: Status - POSNEG_QSS Status - INCRED

0 POSITIVE (SECAM L/L')

Incredible stereo is on

1 NEGATIVE (Others) Incredible stereo is off

20 CONTROLS A8.0AMicroprocessorNote: For Multimedia and Institutional TV Interface pin 8 will beconfigured as TV CLK.

Pin 9: STAT2 or SEL_PIP_R1R2

(valid for non PIP sets)

ADC input.

Detects the presence of SCART2 Video source (CVBS) andalso whether it is 4:3 or 16:9 video source.

Pin 10: STAT_EXT 1/ AFC_TUNER2/SYS_ECO_DW

ADC input

Comparator to sense different DC levels from I/O to indicate thepresence of an EXTERNAL SCART video sources (CVBS), 4:3or 16:9 SCART video.

ADC input (Valid for NTSC-M)

Indicates for the 2nd tuner PIP application for Y/C PIP andnamed AFC_TUNER2.

Input

Controls the Eco Double Window.

Note: For Multimedia and Institutional TV Interface this pin willbe configured as DATA IN.

Pin 11: FRNT_CNTRL

INPUT ADC

Connected to the keyboard and protection line PROT_E_W.The keys are read by applying a unique voltage.

Pin 12: POR2 OUTPUT

Pin 14:SEL_MAIN_FRNT_RR

Pin 8:SEL_MAIN_R1R2

MAIN Source Se-lection

0 0 REAR1 (AV2/SVHS)

0 1 REAR2 (AV1)1 0 FRONT (AV3/

SVHS)1 1 INTERNAL

Pin 9: STAT2 ADC VALUES Status - SCART2 Video

0 - 4 Internal Video

5 - 10 External 16:9

11 - 15 External 4:3

Pin 10: STAT1 ADC VALUES Status - SCART1 Video

0 - 4 Internal Video

5 - 10 External 16:9

11 - 15 External 4:3

Pin 10: Function AFC_TUNER2

ADC

Output of Analog tp Digital Con-verter

Input DC voltage

0 0 - 0.5

1 - 2 1

3 - 4 1.5

5 - 6 2

7 - 8 2.5

9 - 10 3

11 - 12 3.5

13 - 14 4

15 4.5

Pin 10: SYS_ECO_DW System Status

0 50 Hz

1 60 Hz

Input DC Voltage Function ketboard read

0 Protection

1V5 Program Up

2V1 Program Down

2V7 Menu (not forLatam)3V4 Volume Up

4V Volume Down

5V No Key Pressed

A8.0A CONTROLS 21MicroprocessorProvides Power On Reset pulse during start-up for 2nd micro-p (both EPG and non-EPG boards used in Europe sets) andGEMSTAR decoder boards used for USA sets.

For 2nd micro-p board the POR2 is high for at least 2 machinecycles when the oscillator is running and then go back to LOW.

For Gemstar the POR2 must go from LOW to HIGH and remainHIGH during start-up

Note: For Multimedia and Institutional TV Interface this pin willbe configured as DATA IN.

Pin 14: SEL_MAIN_FRNT_RR

See pin 8

Pin 15: SVHS_MODE

OUTPUT

Select/deselect the external SVHS or the CVBS inputs

Pin 16: DEGAUS

OUTPUT

Controls the DEGAUS circuit in the Power Supply block. Duringpower ON this pin gives low going pulse for 2 seconds.

Pin 17: AMP_MUTE1

OUTPUT

Mutes the Audio Output Amplifier

Pin 18 : STAT_HP

INPUT.

To sense the presence of a Head Phone jack.

Pin 19: STBY

OUTPUT

To switch between standby and normal operation.

Pin 20: LED

OUTPUT

Pin 21 SAA5297/P83C770: SEL_GAIN_SPLIT/SEL_TUNER1_2

OUTPUT

Selects the gain of the antenna splitter of the 2nd tuner for PIP(A/P and LATAM sets only).

OUTPUT

Pin 15: SVHS_MODE Select

0 SVHS

1 CVBS

Pin 16: DEGAUS

'0' for 2 seconds and then goes to '1'

Pin 17: AMP_MUTE1 Status

0 MUTE OFF

1 MUTE ON

Pin 18: STAT_HP Status

0 Headphone NOT connected

1 Headphone connected

Pin 19: STBY TVStatus

1 In Stand-by Mode

0 in Normal Operation

Pin 20 Europe AP/Latam USA

0 LED brighter= Standby

LED lighted =Standby

LED lighted =normal

1 LED dimmer= normal op-eration

LED OFF =normal opera-tion

LED OFF =Standby

Pin 21: SEL_GAIN_SPLIT Attenuation

0 OFF

1 ON

22 CONTROLS A8.0AMicroprocessorSelects between the MAIN tuner 1 and MAIN tuner 2. (USAand 2 Tuner PIP sets only).

Pin 30 P83C770: RMT_LOC_DATA

OUTPUT

Signal: DATA to the REMOTE LOCATOR circuit (USA only),others this pin is pulled to high via 3063.

Pin 46 for SAA5297 and P83C770 :WRITE_CTRL

OUTPUT

Selects the global write protection control of the EEPROM(IC7088).

Pin 47 SAA5297/P83C770 : SCL_EEPROM

Clock output EEPROM I2C bus.

Pin 48 SAA5297/P83C770 : SDA_EEPROM

Data in - output EEPROM I2C bus.

Pin 49 SAA5297/P83C770 : SCL

Clock output of master I2C bus.

For a survey of all connected ICs to this bus see the diagram"I2C overview" in the service manual.

Pin 50 SAA5297/P83C770 : SDA

Data in - output of master I2C bus.

Pin 51: RGB_KILL

(Valid for SCART sets !)

Output

Pin 52 of P83C770 : FFBL_EXT/4_NORMA_SEL

For LATAM sets this pin is used to select the respective crystals4 or 2/3 Norma sets. This is configured by hardware as LOW orHIGH depending on the crystals connected to the BiMOS.

OTHER PIN DETAILS

Pin 13: Ground

Ground line for digital circuits for SAA5297 and P83C770

Pin 22: VSSA (For SAA5297 and P83C770 )

Ground line for analog circuits

Pin 23: Ground

Input

CVBS from which closed caption for USA/LATAM or TEXTdata for EUROPE/AP is to be extracted. A positive going 1V(peak-to-peak) input is required.

Pin 24: STN For P83C770 and CVBS1 for SAA5297

For SAA5297 this data slicer decoupling capacitor input, con-nect to VSSA via a 100 nF capacitor (C2054).

Pin 25: BLACK & BLK (For SAA5297 and P83C770 )

CVBS signal black level reference, connected to VSSA via 100nF capacitor (C2055).

Pin 26: IREF (For SAA5297 and P83C770 )

CVBS signal reference current input, connect to VSSA via a27K resistor (R3058)

Pin 27: TEST (For SAA5297 and P83C770 )

This pin is connected to +5V via 10 K Ohms resistor (R3060)

Pin 28: TEST (For SAA5297 and P83C770 )

Pin 21:SEL_TUNER1-2

Tuner 1 Tuner 2

0 Not selected Selected

1 Selected Not selected

Pin 51: RGB_KILL Status

0 Default

1 Kill External RGB

Pin 52: FFBL-EXT Status

0 RGB present on the SCART

1 No RGB on the SCART

Pin 52: 4 NORMA_SEL Status

0 Selects 4 Norma

1 Selects 2 or 3 Norma

A8.0A CONTROLS 23MicroprocessorThis pin is connected to Digital gnd for SAA5297. For P83C770this pin is pulled to high via 3061.

Pin 29: TEST (For SAA5297 and P83C770 )

This pin is connected to +5V via 10 K Ohms resistor (R3062).

Pin 31: RGBREF & REFH (For SAA5297 and P83C770 )

For SAA5297 this is the DC input voltage to define the outputHIGH level on the RGB pins,

For P83C770 this is the data slicer reference high capacitor in-putconnectedtoVSSAvia100nFcapacitor (C2070).

Pin 32 to 35 (For SAA5297 and P83C770 ): FBL, R, G and B

Outputs 'RED', 'GREEN' and 'BLUE' deliver the colour compo-nents for the OSD, while output 'Blanking' is used as a fastblanking signal to insert R, G and B signals in the television pic-ture. The output polarity of all four pins is active high.

Pin 36: HSYNC for OSD /TXT (For SAA5297 and P83C770 )

This signals is derived from the deflection part to get a stableOSD picture on the television screen. The 'HSYNC' pins issupplied with active low horizontal sync pulses (polarity is soft-ware programmable).

Pin 37: VSYNC for OSD/TXT (For SAA5297 and P83C770)

This signal is derived from the deflection part to get a stableOSD picture on the television screen. The 'VSYNC' pin is sup-plied with active low vertical sync pulses (polarity is softwareprogrammable).

Pin 38 for P83C770 & SAA5297 : VDDA

This pin is connected to +5VA

Pin 39: VDDT for SAA5297 & VDD_P P83C770

For SAA5297 this pin is connected to +5V Teletext power sup-ply.

For P83C770 this pin is the Digital periphery power supply.

Pin 40: OSCGND for SAA5297 & VSS_D for P83C770

For SAA5297 this pin is connected to crystal oscillator gnd.

For P83C770 this pin is the Digital Ground.

Pin 41 for SAA5297 and P83C770 : XTALIN

This is XTAL oscillator INPUT pin

Pin 42 for SAA5297 and P83C769 : XTALOUT

This is XTAL oscillator OUTPUT pin. All internal timing of themicro-controller is derived from this oscillator The oscillator fre-quency has to be 12MHz.

Pin 43 for SAA5297 and P83C769 : POR

'POR' is used to reset the micro-controller after a power-on re-set. This reset signal has to be HIGH until a stable 5V supplyvoltage is available and then it goes LOW. Also when the sup-ply voltage drops below the minimum required voltage the mi-cro-controller has immediately to be reset via pin 'POR'.

Pin 44 for SAA5297 and P83C770: VDDM

For SAA5297 and P83C770 this pin is +5V micro-controllerpower supply.

Pin 45 for SAA5297 and P83C770 : RC-5

This input pin is connected to an RC5 remote control receiv-er(TFMS5360). The input should be high when no remote con-trol signal is received.

Pin 52 for SAA5297 and P83C770: N.C

For SAA5297 and P83C770 this pin can be used as an I/O portand is not connected. Pulled to high.

Some hints on problem solving

No LED or IIC activity - Check for the +5V_STBY and the PORpulse

Set always on standby - Check +8V of BiMOS

LED Blinking - The set may be on protection. Check pin 11

No LED blinking to RC5 - Check NVROM

No OSD/TXT - Check H sync on pin 36

No TXT- Check CVBS_TXT on pin 23 and +5V at pin 39.

24 POWER SUPPLY A8.0ADegaussingPOWER SUPPLY Degaussing

The degaussing circuit is activated whenever the TV set isturned on. So from normal off to on and from stand-by to on thedegaussing circuit is activated. During start-up the signal de-gaus (A8-05) is high which blocks TS7900. After start-up of theuP the signal degaus (A8-05) becomes low for 3 seconds whichforces TS7900 in conduction. Now the +13V is put on the coilof the relay and switch G5P-1 is closed. The degaussing cur-rent passes through the degaussing coil. After three seconds,DEGAUS goes high, 7900 turns off , 1901 is de-energised andno current passes through the degaussing coil at normal oper-ation due to the fact that switch G5P-1 is opened. PTC 3906 ispresent in 220V sets and PTC 3908 is present in 110V sets.

+t

13V4

*

*

RELAYSWITCHER

COIL

*

}

13V4 0V

*

DEGAUS

OF MAINS{FILTER

PTC

TO F15

TO DEGAUSSING

G5P

-1

PTC

BZX79-C3V3

6920

3908

ZPB

2M2

3950

9950

1901

23

14

22n

2908

3

39061

2

9999

BC557B7900

BZX79-C9V1

699201321 2

3 4 4K7

3911

6935

1N4148

1

2

M16

6904

1N41

48M15

1

2 10K

3910

+13V

A8-05

CL 86532033_011.AI160698

Personal notes

A8.0A POWER SUPPLY 25General informationGeneral information

CL 86532033_049.AI160698

26 POWER SUPPLY A8.0AGeneral informationThe A8 power supply is a Switch Mode Power Supply(SMPS)with minimum voltage switch. The topology is a flyback convert-er with primary current sensing, secondary voltage sensing andmains input Voltage measuring. The power supply is built withIC 7902 which has a built-in MOSFET and control circuit. Thefrequency ranges for normal operation are 25kHz to 130kHz(full range) and 40kHz to 130kHz (single range and 120V).

The SMPS works in discontinuous mode, so with a T-on, T-offand a Tdead. The FET is switched on during T-dead when thevoltage at the drain of the built-in FET (IC7902 pin 3) is minimaldue to oscillation of C2913 and the primary inductance ofT5912. This is reducing the switching losses.

Output voltages

+14V (For Line Circuit and input voltage for stabilizer 7908): +13.5V. If +14V and +8V are not present check 1905.

+33V (For Tuner) : +33V. Created via R3994 and zenerdi-ode 6955

Vbat (Battery Voltage for Line Output Stage) : +140V (9917present) or +130V (9918 present).

+8V (Bimos Supply ) : +8.3V. Output voltage from stabilizer7908. This voltage is decreased in standby to 2V3. In stand-by TS7909 is conducting and switching R3933 parallel toR3932. This will decrease the output voltage of 7908.

+5Vstby (P Supply) : +5.1V. This voltage is also presentduring standby. If this voltage and +5V are missing check1906. If the voltage at pin 1 and 2 of IC7907 are present re-place 7907.

+5V (For Tuner, QSS, BTSC or ITT etc) : +5.1V. This volt-age is disabled when the +13V is not present at pin 3 ofIC7907. +13V is generated by the line-output circuit. Sowhen the line-output circuit is working correctly the +5V isenabled and the POR signal is generated to start the set.

+15V ( Audio Supply) : +18V or +14V

Personal notes

A8.0A POWER SUPPLY 27Control circuitryControl circuitry

Mains input circuit

The mains voltage is rectified by bridge rectifier D6903 orD6930 ,D6931 ,D6932, D6933 and filtered by C2906 . The DCvoltage across C2906 is the DC input voltage for the SMPS atpin 6 of transformer T5912.

Start-up circuit

IC7902 is started when the voltage present at pin 4 is highenough. When the set is switched on, C2912 is chargedthrough start-up resistor R3917. When the voltage acrossC2912 reaches 16V (Typical), the control circuit of IC 7902starts to operate.

After the control circuit starts its operation, power is supplied bysmoothing and rectifying the voltage of the supply winding ( 8-9 ) of T5912. The supply winding reaches the operation voltagebefore the voltage of C2912 drops below the shutdown voltage.Consequently, the control circuit can continue its operation.

Control circuit and oscillation phase

IC 7902 has two internal comparators . The thresholds of thesetwo comparators are 0.73V and 1.37V. During T-on , the MOS-FET inside IC7902 is conducting . The voltage across R3924

increases due to the increase of the drain current. When thevoltage of pin 1 of IC7902 reaches the threshold voltage Vth(1)=0.73V, the MOSFET turns off. The voltage of pin 8 of T5912becomes now positive . Power supply flybacks at this moment(so energy is released at the secondary side). Voltage appliedat pin1 of 7902 is determined by the turn ratio of the transform-er T5912 and R3962, R3991 ( Typical voltage is 3.5V) . Thisvoltage is higher than threshold voltage Vth(2) (1.37V). Untilthe transformer is demagnetized, this voltage remains high.Once the energy stored in the transformer is fully transferred tothe secondary side, the voltage at pin1 of IC7902 drops belowthe threshold voltage Vth1 after a certain delay time and a newcycle starts.

DEMAGNITIZING DETECTION CIRCUIT

100P

1V6

*

* *

*

**

*1N5062

1N5062

1N50

62

NTC-t

1N50

62

0V 1n5

0R1

**

*

*

*

*

*

(15V6) (301V)

(0V)(0V7)

**

**

***

*

*

*

(301V)TRANSFORMER

290V

290V17V6

1R5

*

**

100m

Hz

*

2906

470u

3R3

3959

2K7

3962

6933

3924

5911

P1

P2

P3

P4

P5

1K5

3991

2920

10n

6931

680R

3922

2912

47u

3K3

3920

5

6

7

8

9

1

10

11

12

13

14

15

16

17

18

2

3

4

5912

9952

470p

2915

6908

BYD33J

3902

9956

2966

3n3

BYD3

3J

6910

2905

2n2

3905

1n5

2914

2n2

6932

2904

6930

BYD33J

6911

GND

1 OCFB 2S

4VIN

STR-F66267902

3D

5

2971

2913

22n

2911

5906

2M2

3941

100K

3917

100K

3995

9954 GBU4J

69034 1

2

3

6906

BYD3

3M

CL 86532033_005.AI030898

28 POWER SUPPLY A8.0AControl circuitryControl circuitry

1V6

*

0V

1n5

0R1

**

*

*

*

*

*

(15V6) (301V)

(0V)(0V7)

(7V7)

11V5

12V5

2V9

17V6

(11V)

(10V)

(15V6)

TRANSFORMER

REGULATOROPTO-COUPLE

290V17V6

*

*

100m

Hz

3R3

3959

2K7

3962

TCDT1101G7950

15

4 2

3924

P2

P3

P4

P5

1K5

3991

2920

10n

680R

3922

2912

47u

3K3

3920

5

6

7

8

9

1

10

11

12

PIN 2 OF IC 7904(MEASURINGOUTPUTVOLTAGE)

SECONDARY VOLTAGE MEASUREMENT 2

13V

13

14

15

16

17

18

2

3

4

5912

470p

2915

6908

BYD33J

2966

3n3

BYD

33J

6910

1n5

2914

BYD33J

6911

GND

1 OCFB 2S

4VIN

STR-F66267902

3D

5

2913

5906

CL 86532033_003.AI030898

A8.0A POWER SUPPLY 29Control circuitryControl circuitryRegulation

Secondary voltage sensingIC7902 (SMPS IC) and 7950 (Opto-Coupler ) form the second-ary voltage regulation circuit. The error amplifier feedback is fedto the control circuit (7902, pin 1) by the opto-coupler. The feed-back is realized as follows:

When the output voltage Vbat increases (decrease of the load), the voltage at the base of the internal transistor of IC7904 in-creases. As a result, the collector current of the internal transis-tor of IC7904 and the current through the diode in the opto-coupler 7950 increases. At the same time, Vce of the transistorpart of 7950 decreases. Therefore, the voltage across C2915increases. This will shorten the T-on time of the MOSFET ofIC7902

The opposite story is valid for an increasing load (decrease ofthe output voltage Vbat). In case of a short-circuit between pin3 and 2 of IC7902 check snubber circuit 2911, 6906,2971 andR3995.

Personal notes

30 POWER SUPPLY A8.0AControl circuitryControl circuitry

Control due to the mains voltageA part of the rectified mainsvoltage is coupled to pin1 of IC7902by dividing the voltage by R3924, R3922 and R3941. The high-er the input voltage, the more the transformer current is limited.In this way the maximum power of the power-supply is limited.

PRIMARY - CURRENT MEASUREMENT

100P

1V6

*

* *

*

**

*1N5062

1N5062

1N50

62

NTC-t

1N50

62

0V 1n5

0R1

**

*

*

*

*

*

(15V6) (301V)

(0V)(0V7)

**

**

***

*

*

*

(301V)TRANSFORMER

290V

290V17V6

1R5

*

**

100m

Hz

*

2906

470u

3R3

3959

2K7

3962

6933

3924

5911

P1

P2

P3

P4

P5

1K5

3991

2920

10n

6931

680R

3922

2912

47u

3K3

3920

5

6

7

8

9

1

10

11

12

13

14

15

16

17

18

2

3

4

5912

9952

470p

2915

6908

BYD33J

3902

9956

2966

3n3

BYD3

3J

6910

2905

2n2

3905

1n5

2914

2n2

6932

2904

6930

BYD33J

6911

GND

1 OCFB 2S

4VIN

STR-F66267902

3D

5

2971

2913

22n

2911

5906

2M2

3941

100K

3917

100K

3995

9954 GBU4J

69034 1

2

3

6906

BYD3

3M

CL 86532033_006.AI160698

Personal notes

A8.0A POWER SUPPLY 31Control circuitryControl circuitry

Primary current measurementThe current through the MOSFET of IC7902 is also goingthrough R3924 which increases the voltage on C2915 and sothe voltage on pin1 of IC7902. This will shorten the on-time ofthe MOSFET.

MEASURING MAINS - VOLTAGE

100P

1V6

*

* *

*

**

*1N5062

1N5062

1N50

62

NTC-t

1N50

62

0V 1n5

0R1

**

*

*

*

*

*

(15V6) (301V)

(0V)(0V7)

**

**

***

*

*

*

(301V)TRANSFORMER

290V

290V17V6

1R5

*

**

100m

Hz

*

2906

470u

3R3

3959

2K7

3962

6933

3924

5911

P1

P2

P3

P4

P5

1K5

3991

2920

10n

6931

680R

3922

2912

47u

3K3

3920

5

6

7

8

9

1

10

11

12

13

14

15

16

17

18

2

3

4

5912

9952

470p

2915

6908

BYD33J

3902

9956

2966

3n3

BYD3

3J

6910

2905

2n2

3905

1n5

2914

2n2

6932

2904

6930

BYD33J

6911

GND

1 OCFB 2S

4VIN

STR-F66267902

3D

5

2971

2913

22n

2911

5906

2M2

3941

100K

3917

100K

3995

9954 GBU4J

69034 1

2

3

6906

BYD3

3M

CL 86532033_004.AI030898

Personal notes

32 POWER SUPPLY A8.0AControl circuitryControl circuitry

Protection

IC7902 has a latch circuit which latches when the thermal shut-down circuit or the over voltage shutdown protection circuit be-comes active. The Latch circuit continues to stop the operationof the power supply when overvoltage protection or thermalshutdown circuit are or were in operation. As long as the sus-taining current of the latch circuit is supplied via R3917 (start-up resistor) the power supply circuit sustains OFF. A restartcan be arranged by switching off the mains voltage and subse-quently switching on again.

If IC7902 is in protection the oscilloscope wave form P3 can bemeasured at pin 4 of IC7902.

Thermal protection

The thermal shutdown circuit triggers the latch circuit when theframe temperature of IC7902 exceeds 140C (typ).

Over-voltage protection

The over-voltage protection circuit, triggers the internal latchcircuit of IC7902 when the voltage across C2912 exceeds22.0V (typ). Since the voltage across C2912 is supplied fromthe drive winding (8-9) of the transformer and this voltage isproportional to the output voltage, it prevents overvoltage at the

secondary output which is caused when the control circuit isopen . Check in this case IC7904, IC7950 and the +142V.

Under-voltage behavior of the power supply

In case a secondary voltage is short-circuited or loaded tomuch, the voltage on winding 8-9 of T5912 is decreasing andso is the voltage of pin 4 of IC7902. When this voltage drops be-low the shutdown voltage, IC7902 stops operating. This will en-able an increase of the voltage on pin4 via R3917.

Undervoltage can be recognized by an intermittently starting ofthe supply.

100P

1V6

*

* *

*

**

*1N5062

1N5062

1N50

62

NTC-t

1N50

62

0V 1n5

0R1

**

*

*

*

*

*

(15V6) (301V)

(0V)(0V7)

**

**

***

*

*

*

(301V)TRANSFORMER

290V

290V17V6

1R5

*

**

100m

Hz

*

2906

470u

3R3

3959

2K7

3962

6933

3924

5911

P1

P2

P6

P3

P4

P5

1K5

3991

2920

10n

6931

680R

3922

2912

47u

3K3

3920

5

6

7

8

9

1

10

11

12

13

14

15

16

17

18

2

3

4

5912

9952

470p

2915

6908

BYD33J

3902

9956

2966

3n3

BYD3

3J

6910

2905

2n2

3905

1n5

2914

2n2

6932

2904

6930

BYD33J

6911

GND

1 OCFB 2S

4VIN

STR-F66267902

3D

5

2971

2913

22n

2911

5906

2M2

3941

100K

3917

100K

3995

9954 GBU4J

69034 1

2

3

6906

BYD3

3M

P6 POWER

5V / div AC0.2ms / div

CL 86532033_007.AI180698

A8.0A POWER SUPPLY 33Low power stand-byLow power stand-by

To create a very low power consumption during standby, theSMPS is forced in burst mode. An oscillator formed by TS7961,TS7962, C2945, C2946, R3945 and D6940. During normal op-eration this oscillator is blocked by TS7910 via TS7963. Duringstandby the oscillator is activated. The output of the oscillator ispresent at the collector of TS7960.

When TS7960 is conducting, current is flowing through the di-ode of opto-coupler 7950 and the transistor part of IC7950 be-comes saturated, which causes the voltage across C2915 toraise above 3V. This will prevent the oscillator of IC7902 fromoscillation. Without any switching of the FET of IC7902 noswitching losses will occur which will decrease the power con-sumption in standby. When TS7960 turns off, the SMPS willstart working again. So in standby the power consumption willbe low but the ripple on the output voltage will be higher. Thisis no problem due to the fact that the set is not operating.

CL 86532033_010.AI080698

= L

= H

*

(0V3)

(0V6) (0V)

0V

11V5

0V0V 0V6

0V6

0V

13V5

(7V7)

(-1V5)(7V2)

(0V7)(0V6)

(0V6)

11V5

12V5

2V9

17V6

(11V)

(10V)

(15V6)

*

*

**

*

*

*

REGULATOROPTO-COUPLE

1n

STBY

LOW POWERSTANDBYCONTROL

ON-OFF SWITCHOSCILLATOR

OSCILLATOR

*

*

**

*

***

*

TCDT1101G7950

15

4 2

P6

33n

2945

2947

22K

3965

820R

3926

3947

82K

BC847B7962

5K6

3948

BC847B7960

1m2919

7961BC847B

3946

5K6

3945

10K

100n

2946

7963BC847B

3976

1K8

22K

3943

4K7

3944

3949

10K

6940

BZX7

9-C1

0

BC847B7910

+5V_STBY

A8-01

CL 86532033_010.AI160698

Personal notes

34 VIDEO PROCESSING A8.0ATunerVIDEO PROCESSING Tuner

The A8 chassis uses a PLL controlled tuner. The tuners are fullband, but dependent on the system (PAL/SECAM/NTSC) thetuning range is as follows

Systems B,G,H,I,L,L',D, K,M and N can be received with the A8chassis. Be aware that for most pattern generators the maxi-mum tuning frequency is 860.00 MHz. At pin 9 of the tuner 33V(+VT =Voltage Tuning) has to be present for tuning a channel.This 33V is derived (via R3994 68k and D6955 33V zener di-ode) from Vbat (+140V) from main power supply (diagram A1).

Tuners

The TELE9-087A for PAL MULTI.The TELE9-108A for PAL MULTI China.The TELH9-205A for NTSC-M only sets

Pal frequency range

Band frequency range

low 44.75-150.25 MHz (E2-S7)mid 150.25-426.50 MHz (S8-S36)high 426.50-890.00 MHz (S37-E69)

NTSC frequency range

Band off-air/cable channels

low 55.25-127.25 MHz

mid 133.25-361.25 MHz

high 367.25-801.25 MHz

Positive modulation

system frequency range

SECAM L' 44.75-110.25 MHz

SECAM L 110.25-890.00 MHz

System picture colour sound1 sound2

B,G,H 38.9 34.47 33.4 33.16

L 38.9 34.47 32.4

I 38.9 34.47 32.9 32.35

L' (band I) 33.9 38.33 40.4D,K China 38. 0 33.57 31.5 32.15

M 45.75 42.17 41.25

A8.0A VIDEO PROCESSING 35Block diagram video path without PIPBlock diagram video path without PIP

The processing is largely handle by a single-chip video-proces-sor IC7150 TDA8844 with built in IF-detector, CVBS and SVHSsource select, luminance and chrominance separator, PAL/NTSC/SECAM chrominance decoder, video controller and hor-izontal & vertical sync/geometry-processor.

The difference with previous TV-processors is that the SECAM-decoder is integrated and also the delay-line.

Three video-signal flow diagrams are possible in the A8 chas-sis:

video path without PIP video path with YUV PIP (for Latam/AP) video path with YC PIP (for Taiwan/Korea)

The IF signal is fed to pin 54 of IC7150 (TDA8844). The demod-ulated CVBS is available on pin 6 and fed back to pin 13 for I/O-switching. The selected video-signal on pin 38 is fed to I/OSCART/Cinch and optional a comb-filter. Without comb-filter isthe video-signal internally processed, but the front-end signalcan always be measured on pin 38 IC7150 to check correct tun-ing.

YUV (pins 28,29,30) is fed via TDA9178 to the RGB matrix(pins 27,31,32). After the matrix it is possible to switch to an ex-ternal RGB-source (or OSD/TXT).

SOUNDBPF

TUNER

SOUNDTRAP

COMB(opt.)

TDA9178(opt.)

CHROMAPROCESSING

SWITCH

CVBS_INT

CVBS+SIF

SIF(to sound proc..) CVBS_EXT

Y Y

FBL ROSD/TXT/SCART etc

G B

R

G

B

TO CRT

U

V

CYC/CVBS_EXTYC/CVBS_EXTYC/CVBS_EXT

CVBS_MON

CVBS_MON

IFTDA884X

IF

MATRIX

RGBPROCESSING

+SWITCH

CL 86532063_002.eps040898

Personal notes

36 VIDEO PROCESSING A8.0ABlock diagram video path with YUV PIP (for Latam/AP)Block diagram video path with YUV PIP (for Latam/AP)

In this block diagram is a splitter added for the PIP-tuner and ofcourse the PIP/DW circuitry (PAL/NTSC). Personal notes

A8.0A VIDEO PROCESSING 37Block diagram video path with YC PIP (for Taiwan/Korea)Block diagram video path with YC PIP (for Taiwan/Korea)

In this diagram use is made of MC44462B for PIP processing.This IC is NTSC-only.

For Pal Multi Asia Pacific sets an additional M-trap (L5145) willbe required for filtering the sound carrier of an NTSC-M trans-mission to avoid interference in the picture. (see diagram A4 inthe service manual)

Personal notes

38 VIDEO PROCESSING A8.0AIF Demodulation (IC7150-A)IF Demodulation (IC7150-A)

The video-signal is demodulated by means of a PLL carrier re-generator (no external LC-circuit anymore only a RC-networkon pin 5 which determines the IF-loop filter). Internal there is afrequency detector and a phase detector. During acquisitionthe frequency detector will tune the VCO to the right frequency.The initial adjustment of the oscillator is realized via the IIC-bus.

In the service menu IF-PLL is indicated, but this alignment hasno effect anymore.

Automatic Gain Control (AGC)AGC control is used to maintain a constant signal at the tuner-amplifiers when the incoming signal on pin 49 and 48 ofTDA8844 becomes too high (above the take-over level). Thetake-over level (limiting point) of the AGC-control can be adjust-ed via I2C in the service menu.

For negative modulation (BGIDKM systems have all negativemodulation) the AGC circuit detects the top-sync level.

The AGC DC signal from pin 54 TDA8844 is fed to pin 1 of thetuner. In normal situations (not at program switching) the AGCDC signal is smoothed by C2126 and R3126.

To enable a fast AGC control at program switching, D6130 orD6131 shorten R3131 at high AGC peaks (a program switchgives a fast change from low to high or from high to low HF lev-

el). As R3131 is shortened, the AGC time-constant is shortly re-duced giving a faster response.

Automatic Frequency Control (AFC)The TDA8844 IC implement the alignment free IF-PLL conceptwhich enables automatic frequency control via IIC. There is noAFC voltage anymore only control via software.

For search tuning two input signals (internally in the TDA8844)are used: video IDENT and AFC. If a transmitter is tuned theIDENT is valid and a digital AFC level is followed (as long asthe IDENT is valid).

Automatic Channel Installation (ACI) is possible with the A8chassis. All channels will be stored according to the ACI-data.This data is a hidden (not selectable for the customer) txt-page(s).

If ACI is not used by the cable network then the auto-store pro-cedure is used. For Europe the channels found will be storedbeginning from max. program number downwards.

For Asian Pacific the channels found will be stored beginningfrom program 1 upwards.

For Germany, Austria, UK and Switzerland, the stored chan-nels will be stored according to a table in the software (ATS).

A8.0A VIDEO PROCESSING 39IF Demodulation (IC7150-A)Sound trap

The baseband CVBS signal (pin 6 of TDA8844), with a nominalvalue of 2Vpp, also contains the sound signals (FM demodulat-ed mono sound for intercarrier sound processing; see AudioProcessing) at a subcarrier of 4.5 / 5.5 / 6.0 / 6.5 MHz. Thesesound signal are filtered out by the sound trap crystals1167,1168 and (selectable) 1165. Crystal 1167 is a 5.5 /5.75MHz or triple trap 5.5/5.75/6.5 MHz ceramic filter, and crystal1165 is a 4.5 MHz (for NTSC-M) ceramic filter (crystal 1168 isreserved and can be used as a 6.0 MHz sound trap for PAL/NICAM I, or NTSC-M sound trap of 4.5MHz).

For audio various concepts are possible:

BASICFM mono/ AM mono

NICAMFM stereo / NICAM BG/I/L'/M

2CS onlyFM mono/stereo

BTSCmono/stereo and SAP (Second Audio Program)

BASICFor the BASIC set, the FM-sound is demodulated by IC7150(TDA8844). The baseband video-signal is fed via bandpass fil-ter 1158 to pin 1 of IC7150. The mono output is pin 15. For AM-sound comes from Quasi Split Sound pin 10 IC7401 (TDA9810on QSS-panel). The demodulated AM-signal is directly fed tothe amplifier.

NICAM, AM SoundThe IF-output from the tuner is also fed to the QSS-panel (Dia-gram I). On the QSS-panel are two SAW filters used dependingon system L/L'. Also the IC is internally switched via pin 7 be-cause of different IF-sound frequencies. The demodulated AM-sound is available at pin 6 and fed to IC7430 (MSP3410D) forfurther sound selection.

The IF-sound output pin10 IC7401 is fed to the MSP3410D.This IC can demodulate NICAM, 2CS and MONO signals.

2CSThe baseband output from IC7150 pin 6 is fed to theMSP3400C (without NICAM) for further demodulation.

BTSC/AV stereoThe baseband signal from IC7150 pin6 is fed to IC7437(TDA9855) for decoding and sound processing. One of the rearcinch inputs, and the signal from the front cinch connectors isselected by IC7436 (HEF4052). The selected signal is fed tothe TDA9855 (pin 12 and 41).

Personal notes

40 VIDEO PROCESSING A8.0AI/O switching with SCART REAR I/O panelI/O switching with SCART REAR I/O panel

In chassis A8 are two versions I/O-panels: I/O with SCART andthe other with CINCH connectors.

The block diagram below shows the I/O switching from the ex-ternal inputs for sets with a SCART REAR I/O panel ( see Dia-gram E).

The input of SCART1 is CVBS + RGB + LR and the output isalways the video (+ sound) signal from the tuner (CVBS_INT).The input of SCART2 is YC + CVBS + LR. The output signal onSCART2 is CVBS_MON (+ sound), except when SCART2 isselected as the source for the main picture. Then the output onSCART2 is CVBS_INT (+ sound).

SEL-MAIN-R1R2 is the selection between SCART1 (R1) andSCART2 (R2) via IC7100-A. With SEL-FRNT-RR selection ismade between front and rear (IC7250 chassis).

Personal notes

A8.0A VIDEO PROCESSING 41I/O switching with CINCH REAR I/O panelI/O switching with CINCH REAR I/O panel

CINCH in/out (see Diagram F or L)

Y/C and CVBS signal of REAR2 are connected together, TheCINCH I/O panel has maximum 2 inputs and one output. Theoutput is always the same source as the main picture(CVBS_MON). The selection for CVBS_MON is done in the BI-MOS.

Since the PIP panels can only handle external CVBS signals,the Y and C signals are added in order to create a CVBS_PIPsignal in case of a YC input signal.

Personal notes

42 VIDEO PROCESSING A8.0ALuminance processingLuminance processing

The switching between external video (CVBS_EXT) and inter-nal video (CVBS_INT) and the switching between YC andCVBS signals is done in the TDA8844. Two different comb fil-ters are used: SAA4961 (PAL/NTSC) or SAA4963 (NTSC on-ly). Since only the SAA4963 has a separate Y input and theSAA4961 has a combined Y/CVBS input, the switching be-tween YC and CVBS is a little different for both comb filters.Switching on and off the comb filter is done via pen 33 IC7150(TDA8844). The switching is done with the 4.43 MHz (or 3.58MHz) oscillator signal imposed on a DC-level:

If the video switching of the TDA8844 in combination withSAA4961. For CVBS_EXT and CVBS_INT sources the outputsignal of the TDA8844 (Y/CVBS_MON) is used forCVBS_MON out. For external YC signals the CVBS_MON iscreated by adding Y/CVBS_MON and C_EXT. This is control-led by the SVHS_MODE control signal from the uP.

If the combfilter is not present then the jumpers (9200 and 4201diagram A5) are present and the external Y/C signals are di-rectly fed to the pins 10/11 IC7150.

There is an Y/C adder realized with TS7243/TS7242(diagramA13) , this is necessary for PIP. IC7250-C selects between thevideo signal from front and rear and then via TS7270 fed to thePIP-panel.

Y/C via rear or front: chrominance is fed via the combfilter to pin10 TDA8844 (diagram A5) and luminance is fed to pin 11. Inthe TDA8844 source select takes place and then CVBS_MONis available on pin 38 .

A second Y/C adder is realized around TS7261 (diagram A13).The transistor is driven by the SVHS-mode signal. In SVHS thebase is low; chrominance is added via R3262/R3263 to the lu-minance via R3264. The video-signal is via the buffer-stage fedto I/O panel for Video out.

The figure above shows the block diagram of the video switch-ing of the TDA8844 in combination with SAA4963. In this casethe CVBS_MON is the same as Y/CVBS_MON.

pin 33 comb filter

low off

high on

A8.0A VIDEO PROCESSING 43RGB - switchingRGB - switching

In A8 there 4 possible RGB sources:

TXT and/or OSD from uP OSD from PCF8515 OSD generator EPG External RGB from SCART or Guide Plus (GEMSTAR)

In previous chassis there was also RGB from PIP possible. Inthe A8 chassis the PIP/DW panel is in the YUV or Y/C signalpath (see also the block diagram of the video path). TheTDA8844 has only one RGB input, so switching between thedifferent RGB sources is needed. The figure below shows theRGB switching.

All sets have RGB_TXT and/or RGB_OSD from uP. Only AP sets have the PCF8515 (separate OSD-IC) If the set has TXT from uP and OSD from PCF8515, these

RGB sources are connected together via diodes and thenconnected to the input of TDA8844 directly. The softwareshould make sure that there is no OSD during TXT. Jump-ers A are in.

For EPG sets a separate TXT/EPG processor (IC7007 dia-gram S) is used. The RGB of the EPG and OSD from (P areconnected together via diodes and then connected to the in-put of TDA8844 directly. Jumpers A are in.

For sets with external RGB (SCART), the selection betweenRGB_TXT/OSD and RGB_EXT is done with a IC7275(TDA8601) RGB-switch.

The RGB_KILL signal is used to overrule an external RGBsource from SCART.

Status signals

There are 3 status signals which come from SCART REAR I/Opanel. With the information which comes from these status sig-nals the set is set to the correct mode.

STATUSSIGNAL

DESCRIPTION Remark

STAT1 CVBS status from 0 - 2V: internal CVBS

pin 8 of SCART1. . 4.5 - 7.0V: 16:9 aspect ratio

This is fed to uP pin 10 9.0 - 12V: 4:3 aspect ratio

STAT2 CVBS status from 0 - 2V: internal CVBS

pin 8 of SCART2. 4.5 - 7.0V: 16:9 aspect ra-tion

This is fed to uP pin 9. 9.0 - 12V: 4:3 aspect ratio

FBL RGB status from pin16 of SCART1

>0.9V is RGB mode

44 VIDEO PROCESSING A8.0AChrominance ProcessingChrominance Processing

Chrominance

The chrominance signal is internally applied to the PAL/NTSC/SECAM chrominance decoder inside IC7150-B. Also the 64 Sdelay line is integrated in the TDA8844. Chrominance can alsobe fed in on pin 10 from COMB-filter or SCART and luminanceon pin 11.

The chrominance demodulator determines whether a PAL,NTSC or SECAM signal is present and subsequently decodesits R-Y and B-Y signals.

For LATAM there are three BI-NORMA versions, one TRI-NORMA and one FOUR-NORMA.

Depending on the version a 3.6MHz x-tal or a 4.4MHz x-tal isconnected to pin 35 of the BI-MOS. During INITIALIZATION ofthe BIMOS the XA,XB control bits have to be set in order to geta correct calibration of the BIMOS.

If the XA,XB setting does not tally with the x-tal connected to pin35, the line output transistor can be killed. So, this can not bedone via a software option!! A option jumper between pin 52 ofthe uP and ground is used to distinguish between the x-talsconnected to the BIMOS.

CL 86532063_006.eps040898

3197

100K

33K

3193

8V3

1V7

2V3 1V2 3V4 0V4

3V4

3V7

11

COMB_ON

Y_CVBS_EXT

1

1

00

C_EXT

TO/FROMCOMB-FILTER

*

**

*

* * **

* * *

*

*

**

*

*

*

*

*

2V3

0

Y_CVBS_MON

PAL BG

SYS2

2V3

SYS2

FOR WITHOUTCOMB FILTER

NTSC MPAL N

SYS1

PAL M

*

*

*

0SYS1

2V3

EXT. CVBS BUFFER

6V6 2V32V5 2V5 4V7

2V6

33K

3191

2190

15p

BFS207191

33K

3189

2197

100n

22n

2186

15p

2189

9200

4201

2187

2u2

3435

2176

470n29

1038

17

13

11

SY9 36

28

SAND

CAST

LE

33

30

16

7150-BTDA8844

15p

2191

100n

2180

V8c

V8a

V8b

4195

1191 11

90

1192

1189

7193BC847B

V4

V6

V7

CVBS_INT

C_CO

MB

Y_CO

MB

4198

7190BFS20

BC847B7189

3190

33K21

81

100n

470n

2177

3176

560R

2192

15p

V5

220n

2188

1n2196

3192

33K

3194

33K

BC847B7176

7192BFS20

3175

100R

V2

4192

4190

R_Y_OUT

B_Y_OUT

Y_OUT

+8V

+8V

PAL/INTSCY

Personal notes

A8.0A VIDEO PROCESSING 45Chrominance ProcessingChrominance Processing

The crystals are also used as a reference for the line frequen-cy (sync diagram A6). This means in case of colour problems(only black/white) the crystal could cause the symptom. Re-place the crystal only by an original one! In case of only black-white the problem can also be the loop filter on pin 36 IC7150.So not always the IC causes the problem but mostly compo-nents around the IC.

A defective crystal: no synchronisation! The DC-level of theCVBS-signal (pin13 front-end signal and pin17 from SCART) isalso very important. In case this level is not correct than thesymptom could be no picture.

SET VERSION possible systems x-tal on pin 34 x-tal pin 35 pin 52BI-NORMA-M PAL-M/NTSC-M 1x 3.6MHz 1x 3.6MHz highBI-NORMA-B PAL-BG/NTSC-M 1x 3.6MHz 1x 4.4MHz lowBI-NORMA-N PAL-N/NTSC-M 1x 3.6MHz 1x 3.6MHz highTRI-NORMA PAL-M/PAL-N/NTSC-M 1x 3.6MHz 2x 3.6MHz highFOUR-NORMA PAL-M/PAL-N/PAL-

BG/NTSC-M3x 3.6MHz 1x 4.4MHz low

BI- TRI and FOUR NORMA configuration

Personal notes

46 VIDEO PROCESSING A8.0AChrominance ProcessingYUV

The demodulated video-signal can be checked on pins28,29,30 IC7150 and is fed to pins 27,31,32. In this path theYUV panel can be inserted. Without this panel, the jumpers4225/4226/4227 are in.

On the YUV-panel TDA9178 is used, which can control variouspicture improvements: histogram processing, colour transientimprovement and luminance transient improvement.

The TDA8844 can also do some picture improvements:

Sets without TDA9178; for sets without TDA9178 the Dy-namic Skin Control and the Blue Stretch is controlled intheTDA8844. There is no Green Enhancement.

Sets with TDA9178: for sets with TDA9178 the DynamicSkin Control and Green Enhancement are controlled in theTDA9178. The Blue Stretch is controlled in the TDA8844and the Blue Stretch of the TDA9178 is switched off.

Green Enhancement. Is intended to shift low saturatedgreen colours towards more saturated green colours. Thisshift is effective for only that part of the picture that matcheswith low saturated green.

Blue stretch. For parts of the picture that are white, the col-our temperature is changed a little bluish coloured white togive a brighter impression.

Dynamic Skin Control. Skin tones are very sensitive for hueerrors, because the human eye has an absolute feeling forskin tones. To make a picture look free of hue error, the goalis to make sure that skin tones are put at a correct colour.

When the TDA9178 is used then the noise reduction is alsoavailable. The action of the noise reduction has also influenceon the sharpness control.

IF a noisy signal is received then the noise reduction should behigh and sharpness low and also vice versa:

Good picture: DNR=low; sharpness= high; Bad(noisy) picture:DNR=high; sharpness=low

CL 86532063_004.eps040898

5V9

3V

11

B

Y_IN

3V5

2V3

2V3

2V6

AVE. BEAM - CURRENT LIMITER

LOT SATURATION LIMITER

180k1V7

B_Y_IN

R_Y_IN

10

13

2V2

2V2

2V2

RGB_SW_OFF

100R

3V4

1V9

1V8

1V9

5V2

3V70V2

3V53V5

180k

****

0V2

12

****

***

TO C

30 O

F CR

T PA

NEL

3V6

1V9

1V8

1V9

EHT_INFO

2322

4u7

1K3293

2323 1u

6301

BAS2

16

47R

3327

22R

3309

47R

3308

3292

32 RYI

7

SCL

8

SDA

TDA8844

22BCLIN

25BI

18BLKIN

19BO31 BYI

24GI

20GO27 LUMIN

26RGBIN

23RI

RO 21

7150-C

2292

47n

BAS2

16

6300

2301

47p

3304

2K2

6325

BAS216

V9b

V9c

V9a

47p

2302

3325

BAS2

16

6302

4

5

M13A

M301

2

3

M12A

V10c

47p

2300

10K

3312

3324

3307

47R

2321

100n

BC857B

3326

150K

47K

3331

7325

V12c

3323

22K

BCI

V12b

2K2

3330

9222

47R

3306

3336

100R

2K2

3303

100R

3335

V12a

47n

2293

47R

3310

3311

47R

BAS216

6328V10a

V10b

2K2

3305

2294

47n

FBL_OUT

+8V

G_OUT

B_OUT

+8VB

R_OUT

FROM SEPARATETXT-ICWHEN

PRESENT

R_IN

G_IN

B_IN

SDASCL

CONTROLS A8 WHENOSD PANEL IS PRESENT

OR

TO M12B & M13B OFTRANSPARENT OSD A9

TO M12C & M13C OF

G-YMATRIX

RGB

A8.0A VIDEO PROCESSING 47Chrominance ProcessingOSD-IC7101

See also chapter "Teletext and On-Screen Display.

253 fonts are possible with 4 different sizes, foreground/back-ground colours, shadow.

This IC is put on a separate panel. On the connector O06 H-and V-sync are fed in for stable OSD and for OSD-positioning.What has to displayed is transmitted via I2C. The RGB-outputsand fast-blanking are fed to IC7275 via connector O05.

TXT/EPG (diagram P) uses a separate microprocessor for Eu-rope, because in these countries features like ACI/FLOF/TOPare used. These features need also some memory and thatwas not enough available in the main microprocessor IC7000.

In the circuit diagram P two versions are indicated: theSAA5262 and SAA5263:

Both support also ACI and the SAA5263 can do the 'simple'Electronic Program Guide (EPG) feature.

The commercial name for EPG is NextView: (this part is alsodescribed in the MG98/MD2.2 TM)

NexTView is a feature with which it is possible to retrieve a pro-gram listing with one press of the button.

NexTView (Simple Program Guide): For each program, duringinstallation the user should indicate on which teletext page theprogram guide can be found. This teletext page is then dis-played when the nexTView command is given. This featureonly requires a software modification and no hardware modifi-cation in the set. For each program the page number in whichthis information is contained has to be given.

CONTROLREGISTER

DISPLAYROM

I/OPORT

BUFFERS

INTERNALSYNCHRONOUS

CIRCUIT

PLLOSC

CSYNCSEPAR

CRYSTALOSCILLATOR

CONTROLSIGNALS

R G BTO RGB SWITCH

7275

FROMUC

7000

FB

TESTINGCIRCUITRY

DISPLAY CONTROLAND OUTPUT STAGE

ACM-VOB2

5

EXT/INTDATA SWITCHING

BUFFER

I 2 C SLAVERECEIVER OR

HIGH-SPEED I/OBUFFER

CHAR SIZEREGISTER/CONTROL

HORIZONTALPOSITIONREGISTER/COUNTER

INSTRUCTIONDECODER

VERTICALPOSITIONREGISTER/COUNTER

WRITEADDRESSCOUNTER

ADDRESSBUFFER

SELECTOR

DISPLAYCHARRAM

IVOW

3

17P00

19P01

2P04|ACM

13 RESET_

16

RVOW

0

9SLC SCL|SCLK8

SDASDA|SIN

4

TST1

3

TST2

21 VDD

12 VSS

6 VSYNC

10XT

A1I

11

XTA2

O

PCA8515P7101

24AVDD

23AVSS

20

BVOW

2

5 C

14 E

22

FBVO

B

18

GVOW

1

15 HIO_|I2C

7 HSYNC

1

CL 86532033_017.AI1606989.4

48 VIDEO PROCESSING A8.0AChrominance ProcessingRGB-dematrixing

RGB dematrixing dematrixes the -(R-Y), -(B-Y) and the Y sig-nals into RGB signals.

Contrast, saturation and brightness control are realized via I2C(for an external RGB-source brightness and contrast is alsocontrolled).

FBL-INVia the FBL-IN fast blanking signals on pin 26 of IC7150-C,both the fast blanking and the RGB source select is realized:

When FBL-IN at pin 26 is higher than 4V DC, IC7119-4C isin the OSD mode (only the FBL-IN coming from the OSDgenerator of the P gives 8V DC). If pin 26 is higher than 4VDC, the RGB output pins 19-20-21 of the video controllerare made high-ohmic, so RGB OSD info from the P can beinserted. This mode is not used in A8.

When FBL-IN at pin 26 is between 0V9 and 4V DC, IC7150-C is in the external RGB mode.

RGB from TXT or SCART can be inserted at pins 23,24,25. When FBL-IN at pin 26 is lower than 0V9 DC, IC7119-4C is

in the internal RGB mode.

Peak white limit (PWL)See diagram A7

If the beam current becomes too high, the picture tube could bedamaged. If the voltage on pin 22 is reduced then also the con-trast is decreased. The EHT-info is fed to R3331/3324. ViaTS7325 a fast PWL is realized and via D6328 the average PWLbecause of RC-time C2322/3331.

The voltage on pin 22 is also dependent of the contrast settingin the picture menu.

Transparent OSD only EuropeSee diagram A7/A9

Can be realized by controlling the peak white limit. To realizethis the circuitry of diagram A9 is added. The fast blanking(FBL1) is fed to the collector of TS7361 to make a box with re-duced contrast.

To the base of the TS7361 is FBL2 fed. This makes the OSD-blanking and the OSD is inserted via the RGB-lines from the Pto the RGB-inputs (23-26).

In the circuit diagram A7 there is an option for soft clipper withTS7316/TS7318/TS7320. This has also effect on the PWL pin22. If one of the voltages of the RGB-drive is too high thenTS7320 conducts to reduce contrast. In this case the peakwhite limit via the EHT-info has less function, because thepeaks are now limited by the soft clipper.

CL 86532063_005.eps040898

LUMA

NC

TRAL

DOWWIN-

ADC

PROC

SPEC-

CONTROL

PROCESSINGCHROMA

PROCESSING

RES

Y - INY - IN

B - Y - IN

R - Y - IN

FBL_TXT_OSDR_TXT_OSD

G_TXT_OSDB_TXT_OSD

RGB_SW_OFF

U - IN

V - IN

SDA

SDA SCL

SCL

+8V

100n

2227

SAND

CAST

LE

+8V

3338

4R7

3336

100n

2226

3337 0R

1

SCL

11

SDA

14

SOUT 21

UIN8 UOUT 17

VCC20

VIN9 VOUT 16

YIN627

7150-C

31

32

21

20

19

18

1M30 R

G

B

BCI

2M30

3M30

5M30

1C30

2C30

3C30 TO CRTPANEL

5C30

2625

2423

8 7

YOUT 19

7770TDA9178

AD1

3

AD2

4

AD3

5

ADR

7

CF22

DEC

15

GND1813 12 2 10 23 24

SC

10u

2225

3339

G-YMATRIX RGB

V12c V12b V12a

A8.0A VIDEO PROCESSING 49Chrominance ProcessingVia diodes D6300/6301/6302 the RGB-outputs are very fastswitched off. At switch-off these diodes will conduct so theRGB-drive is made high. To prevent a very bright picture thevertical deflection is put on top of screen so the switch-off spotis not visible.

Cut-off control/white driveThe picture tube is continuously adjusted to prevent visible age-ing of the picture tube. In this way the customer has always aperfect picture.

This is so-called 'Continuous Cathode Calibration'. The func-tion is realized by means of two-point black level stabilization.By inserting two levels for each gun and comparing the resultwith 2 different reference circuits the drive is controlled. Withtwo different reference currents the influence of picture tube pa-rameters like the spread in cut-off voltage can be eliminated.

The measurement of the "high" and the "low" current of the 2-point stabilization circuit is carried out in 2 consecutive fields.The leakage current is measured in each field, The maximumallowable leakage current is 100uA. The current is measuredvia Beam Current Information (BCI) that is fed back to pin 18 ofIC7150-C.

When the TV is switched-on the RGB output signals areblanked and the black current loop will try to set the right picturetube bias levels and then there is RGB-drive.

Personal notes

50 VIDEO PROCESSING A8.0ACRT panelCRT panel

RGB amplifier

The RGB amplifier on position 7830 is located at the CRT-pan-el. This integrated RGB video amplifier has three amplifierchannels inside and is intended to drive the three cathodes ofthe colour CRT.

The main features of IC TDA6107 are :

This amplifier is connected to 200V only because 13V ref-erence is generated internally.

Black current stabilization output is also generated internal-ly and this signal goes directly to the BiMOS feedback input(see diagram A7).

Thermal protection.

The amplifiers are basically negative feedback op-amps locat-ed inside the IC TDA6107. Pins 1, 2 and 3 are inverting inputsfor green, red and blue ; pins 7, 8 and 9 are cathode outputsfor blue, red and green. Pin 5 is the black current stabilizationoutput.

Cut-off stabilization

Cut-off stabilization is an auto tuning loop (active during a fourline period prior to the end of a field blanking pulse) which sta-bilizes the black current of each RGB-channel sequentially andindependently. This is a new concept known as 'Continuous

Cathode Calibration', provided by the BiMoS. In this conceptthe cathode drive is adjusted at two points and hence providesbetter accuracy of black level.

Picture tube flash over protection

TDA needs external protection consisting of D6831, D6833,and D6835 combined with 100 Ohm resistors R3831, R3833and R3835 to protect the video amplifier against picture tubeflash-over discharge. These diodes clamps the cathode outputvoltage to VDD + diode. To limit the diode current , external re-sistors of 1K R3832, R3833 and R 3835 are connected in serieswith the cathode output of each gun, in conjunction with the2KV sparksgaps in the CRT socket.

MIRROR 1

MIRROR 4

MIRROR 5

CASCODE 1

CASCODE 2

MIRROR 2

DIFFERENTIALSTAGE

VIPREFERENCE

THERMALPROTECTION

CIRCUIT

CURRENTSOURCE

MIRROR 3

1x

4

Rl

1x

3x

VDD

6

9, 8, 7

6

Voc(3),Voc(2),Voc(1)

Io(m)

RaRl

3x

1, 2, 3Vl(1),Vl(2),Vl(3)

TDA6107Q

CL 86532033_028.AI160698

A8.0A VIDEO PROCESSING 51CRT panelCRT panel

SCAVEM

Scavem means SCAn VElocity Modulation; the Scavem-circuit-ry is implemented in the layout of the picture tube panel so it isnot an extra module.

This means that the horizontal deflection is influenced by thepicture content. In an ideal square wave, the sides are limitedin slope by a limited bandwidth. (5 MHz).

Scavem will improve the slope as follows:

At a positive slope, a scavem-current is generated which sup-ports the deflection current. The first half of the slope the spotis accelerated and the picture is darker, while at the second halfof the slope, the spot is delayed and the slope becomes steep-er.

At the end of the slope, the scavem-current decays to zero andthe spot is at the original position. An overshoot occurs whichimproves the impression of sharpness.

At the negative slope, the scavem-current counteracts the de-flection and during the first half of the slope, the spot is delayed,the slope becomes steeper. During the second half the spot ac-celerates and the scavem-current is zero at the end of theslope.

OperationVia the three resistors R3861, R3862, R3863, red, green andblue are added together and offered to the emitter of 7860. Onthe collector of this transistor, configured in a common base,the sum of these three signals is obtained.

Via the emitter follower 7861 this signal is conveyed to the dif-ferentiator C2867, R3868 and R3869. Only the high frequen-cies are differentiated (small RC). The positive and negativepulses of this signal drive 7863 and 7862 respectively into con-ductivity. The DC setting of the output stage is set by R3870,R3871, R3872 and R3783. The working voltage of the transis-tors is at half the supply voltage. At the positive section of thepulse, the current flows through R3869, C2869, the scavem-coil and TS7863.

At the negative section of the pulse, the current flows throughR3869, C2869, the scavem-coil and TS7862.

Both currents flow through R3869 and the voltage across thisresistor is a measure for the scavem-current.

This voltage is fed back via R3868,.D6867 and D6868.

In this way the feedback operates with an approx. 0.6V thresh-old.

Because of this, the scavem-current is limited to 50mA.

# = 34"

##

#

820R FOR34"

#

R

G

8k2

SCAVEM

0V7

5V6

1V4

5V6

RGB ADDER

DRIVERSCAVEM

SCAVEM PRE-DRIVER

72V

13V5

4V7

B

TOSCAVEM COIL

72V6

3K3

15p

2K7

18p

2K2

10R

22p

0V

0V6

37V

36V

## = 28"/29"/37"

##

#

## #

10u

FOR

34"

##

3876

33R

22n

2870

9876

5861

3874

7863BD829

470n

2866

2876

10u

3865

18K

1

2

3

47p

2872

C80

3869

15R

56K

3872

1N4148

6867

6868

1N4148

3870 1K

+200V

3864

470R

270p

BAS216

6862

2867

2865

100n

2869

4p7

2873

2874

56p

22n

3877

100R

100u

2860

5862

5u6

BF1997860

3868

150R

2K2

3866

3871

56K

6861

BAS216

5863

5u6

2863

2862

3863

2861

3862

3861

3875

4K7

3880

10R

7861BF370

3881

2868

22u

2871

7862BD830

100p

1K3873

2864

470n38

67

220R

10R

3860

5860

3882

220R7

6

5

CL 86532033_025.AI160698

52 Synchronization A8.0AHorizontal and Vertical SynchronizationSynchronization Horizontal and Vertical Synchronization

Horizontal synchronization

Start upBefore the Video processor IC7150 can generate horizontaldrive pulses the supply voltages on both pin 12 and 37 must bepresent. Pin 12 supplies the IC circuits and pin 37 supplies thehorizontal drive circuits in the IC. After the start up command ofthe uP via the IIC the BIMOS starts giving horizontal pulses.First with a double line-frequency in order to obtain a smoothswitching-on behavior of the horizontal output stage.

Horizontal sync. SeparatorThe horizontal sync. Separator separates horizontal pulses outof the CVBS signal and so synchronizes the free-running hori-zontal sawtooth generator. Both the horizontal and vertical os-cillator frequencies are internally locked to the 4.43 / 3.58 MHzchrominance oscillator on pin 34 / 35 IC7150-B and so "knows"whether the frame frequency is 50 or 60 Hz and the line fre-quency is 15625 or15750 Hz (also for black and white picturesthis 4.43 / 3.58 MHz oscillator can be used for locking of thehorizontal and vertical oscillator).

Horizontal sawtooth oscillatorThe horizontal sawtooth oscillator signal is converted into asquare wave voltage. This square wave HDRIVE signal at pin40 is fed to the line output stage. The time constant of the sync.circuit (different for VCR and weak terrestrial signals) is auto-matically internally determined by IC7150-B.

Sand-castle output (pin 41)On pin 41 the sand-castle (SAND) is present. The burst-keyand vertical blanking pulse are always available (made byIC7150-D). Pin 41 also act as input pin for the horizontal fly-back pulse (HFB). This pulse is used for the horizontal phasecorrection. The sand-castle pulse is a 2 state pulse with the fol-lowing values:

5V3 level for the burst-key timing ; 2V for line and frame blank-ing timing

Horizontal Phase correction (pin 42)The phase-correction signal at pin 42 give horizontal shift cor-rection during beam currents changes. If the beam current in-creases (more white), the EHT voltage decreases so thepicture will become off centre. The Phase correction signaltakes care that the picture remains in the middle of the screenby adapting the timing of the horizontal drive pulse (H_DRIVE).

Vertical synchronization

Vertical sync. SeparatorThe vertical sync. separator separates frame sync. pulses fromthe CVBS signal and synchronizes the frame oscillator.

VDRIVE_POS (pin 46) and VDRIVE_NEG (pin 47)The VDRIVE_POS and VDRIVE_NEG signals are the bal-anced output currents (sawtooth shaped) of the frame oscillator

1K

3802

100n

2810

RES

FOR E/W SET

BUFFER

0V8

3V8

1V2

SYNC PROCESSING SECTION

2V2

2V9 7V8

0V4

4V9

3V2

A2-17

VDRIVE_NEG

SANDCASTLEA7-64

HFB

PHASE_CORRECTION

A2-20PROT_IBEAM_EHT_INFO

A2-10

1V3

0V6

8V33V9

E_W_DRIVE3V8

2815

2n2

A2-08

A3-25

A3-24

VDRIVE_POS

H_DRIVE

3814

100R

4K7

3805

C14

3813

2819 1u

4K7

L8

L1

33K

3800

F138

01

4M7

3806

L5V_

P2

1n2812

TDA8844

39DECDIG

50EHTO

45EWD

41 FBISO

44GND2

40HOUT

52I_REF

43 PH1LF42

PH2L

F

46VDRA

47VDRB

51 VSC

37

15p

2813

C12

7150-D

27K

3811

2820 1n

3809

39K

1n2821

1K

3808

3807

1K

7800BC847B 2814

220n

100p

2818

15K

3804

2811

4K7