OTIS ( O uter Tracker T ime I nformation S ystem) A TDC for LHCb

1Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich Uwer

Physikalisches Institut Universität Heidelberg

OTIS (Outer Tracker Time Information System)

A TDC for LHCb

8th Workshop on Electronics for LHC Experiments

September 9 – 13, 2002 Colmar, France

OTIS Group, University Heidelberg:Harald DeppeUwe StangeUlrich TrunkUlrich Uwer



Contents

OverviewOuter Tracker, Front End Electronics & OTIS

OTIS Chip Concept Components of the OTIS Chip

OTIS1.0 PrototypeMeasurements

Summary



TDC +

ReadoutBuffer

DerandomizerBuffer

Pipeline MemoryTrigger

Hit

DriftTime

DLL

DAC

Fine TimeControlCircuit

I2C Interface

BX

SDA SCL notResetTTCrx

GbitLink

8

OTIS

Straw Tube(w. particle track)

32 ch

GOL

TTC

ASD(8 ch)

Outer Tracker / FE

Drift time measurement Mounting on detector Approx. 50,000 channels Data of 4 TDC (32 chan-

nels each) gets serialised and transmitted optically (1.28GBit/s)

Chip Requirements:

1ns resolution (6 bit) drift times of up to 50ns

40MHz, clock driven design 1.1MHz L0 trigger rate

up to 10% occupancy 4µs trigger latency

radiation hard design (pipeline length: 160)

9.6GBit/s

4 x 320MBit/s



OTIS: Concept

Components: 32 maskable channels DLL, HitRegister, PrePipeline:

6 bit drift time generation,playback data feed in

Pipeline, Derandomizing Buffer:Intermediate data storage, compensation of trigger rate fluctuations

Control Algorithm:Memory and trigger management,data output

Slow Control Interface:Programming the chips behaviour

DAC: ASD-Chip bias



OTIS: DLL, HitReg, Decoder

Clock

Delay Chain

Phase

detector

Charge

pump

Hit SignalD Q

64 Time bins

( 390ps nom. resolution)

64 Hit registers

QDQD

Decoder 64:6

6 bit drift time

Vctrl



OTIS: DLL, HitReg, Decoder

Clock

Delay Chain

Phase

detector

Charge

pump

Hit SignalD Q

64 Time bins

( 390ps nom. resolution)

64 Hit registers storing

a picture of the Hit Signal:

QDQD

Decoder 64:6

6 bit drift time

Vctrl

Time

0..01110 .. 0



OTIS: DLL Prototype

Dy

na

mic

Ra

ng

e

Vct

rl /m

V

ResultsDynamic range:

Vctrl: 1V

Lock range:

flock: 29-56MHz @ 300K

Tlock: 10-90°C @ 40MHz

Lock time:

tlock < 1µs

Differential nonlinearity:

DNL = 0,51 ± 0,03 LSB

(190ps)



OTIS: Pipeline, DBuffer

Realised as dual ported SRAM

(164 + 48) x 240Bit x 40MHz 1.1GByte/s low power design

Test chip OTISMem1.0 fully functional expected behaviour confirmed (operational up to 100MHz)



OTIS: Control Algorithm

Management of memory, trigger and data output.

Verification of critical parts on FPGA. Data format:

First hit out of 1, 2 or 3 BX

Single Hit TDC

8bit drift times

Independant from occupancy

Fixed read out length

Data format guarantees synchronous operation of all TDC

Hit Position Data

1. BX 00XXXXXX

2. BX 01XXXXXX

3. BX 10XXXXXX

No Hit 11000000

Bit 0 .. 31 32 .. 39 ... 280 .. 287

Data Header Drift Time 0 ... Drift Time 31



OTIS: Data format (planned)

Bit 0..31 32..127 128..133 ... 122+(6n)...127+(6n)

Data Header 3 * Hit-Info Drift Time 1 ... Drift Time n

Bit 0..31 32..95 96..101 ... 90+(6n)...95+(6n)


Bit 0..31 32..63 64..69 ... 58+(6n)..63+(6n)


Data format for 1, 2 or 3 BX per trigger (programmable, truncatable to 900ns)

1 BX per trigger (100% mean strip occupancy w/o truncation)





Contents

OverviewOuter Tracker, Front End Electronics & OTIS

OTIS Chip Concept Components of the OTIS Chip

OTIS1.0 PrototypeMeasurements

Summary



OTIS1.0 Prototype

First prototype with basic

functionality ~700.000 transistors 5100µm x 6000µm Tape out: 15/04/2002

Delivery: 29/07/2002 Small test PCB with

possibility to connect

ASD and GOL chips



OTIS Under Test (1)

DLL Lock Time

Ch1: Clock

Ch2: notReset

Ch3: Vctrl

Power Consumption 185mA or 465mW after PowerUp reset 220mA or 550mW operation @ 40MHz

Vctrl 1.1V

Tlock 1µs



OTIS Under Test (2)

Read Out Sequence

Debug SignalsSequence Start

Sequence Stop

Data (8bit)

Correct memory and trigger management Correct frame length Correct timing and behaviour of Correct data encoding for

debug signals - header

- drift times

Header Drift time pattern



OTIS Under Test (3)

Drift Time Measurement: Unexpected behaviour

of the encoded drift time:

under study

Workaround to procede

with test: double hit pre-

charges the decoder

preliminary

preliminary



Preliminary Status OTIS1.0

PowerUp Reset as expected

Power Consumption 550mW

DLL: Lock Time 1µs

Lock Lost not observed

DAC as expected

Slow Control as expected

Fast Control: Memory and

Trigger Management, Data

Output, Debug Features

no errors found

Memory Selftest problems

Drift Time Encoding not yet understood



Outlook

Further investigations concerning drift time encoding

Study more chips, performance tests,

random trigger tests, ...Operation with detector prototypeCommissioning of the read out chain

including TTCrx



Summary

OTIS TDC Chip: 32 channel TDC, 6 Bit drift time resolution 40MHz, clock driven architecture 160 events deep pipeline 1.1MHz trigger rate radiation hard

Prototype OTIS1.0 at hand since

6 weeks: almost fully functional

Documents

OTIS ( O uter Tracker T ime I nformation S ystem) A TDC for LHCb