© 2013 ANSYS, Inc. ANSYS-Apache Confidential 1 Apache Design, A subsidiary of ANSYS Apache Design, A subsidiary of ANSYS

SemiCon Europa 2014 Jérôme Toublanc

Optimize Power Consumption & Delivery from RTL to GDS

© 2013 ANSYS, Inc. ANSYS-Apache Confidential 2 Apache Design, A subsidiary of ANSYS

Curr

ent

Time

Metrics

It is all about Power!

#µA/MHz? #nA?

FUNCTIONAL STANDBY

Power control is mandatory!

Cost Applications

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• Power Gates • Back Biasing • …

• Gated Clocks • Frequency Scaling • …

• Gated Control • Sleep modes • …

• Gated DataPath • Gated Registers • …

How do we control the Power?

Leakage Clock Trees Memories Datapath

Power Control Efficiency is a must!

© 2013 ANSYS, Inc. ANSYS-Apache Confidential 4 Apache Design, A subsidiary of ANSYS

clk _

Use case: Gated Clock

enable_

gated_clk _

data _

Inefficient controls waste power

en_blk

clk

gclk_blk

Block Clock Gate

en_reg

Register Clock Gate gclk_reg

Block level enables control significant power Wasted Power!

Synthesis will optimize cell level clock gates, but Block level clock gates are even more critical!

© 2013 ANSYS, Inc. ANSYS-Apache Confidential 5 Apache Design, A subsidiary of ANSYS

B

A

MUX_EN

M_OUT

Wasted Power!

Final Gate Netlist Power Performances rely on RTL Code Efficiency

Use case: Data Path

MUX_EN

1

0

A

B

M_OUT

Redundant Activity wastes Power Exclusive Cone of Logic driving Mux Input

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PowerArtist: RTL Power Metrics

module PA (

... always @ (posedge clk) begin dout

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PACE: RTL Power Predictability

module PA (

... always @ (posedge clk) begin dout

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Millions of Cycles can be Analyzed at RTL Level time

Pow

er Activity Analysis coverage

Worst Power

Frame: CYCLE_POWER Start time: 0.0806005 Finish time: 0.0806007 Average leakage for supply VDD: 0.002569 Average power for supply VDD: 0.250168 Peak power for supply VDD: 0.266678

Worst di/dt

Frame: DIDT Start time: 0.0817704 Finish time: 0.0817706 Average leakage for supply VDD: 0.00257393 Average power for supply VDD: 0.185336 Peak power for supply VDD: 0.219776

PowerArtist Cycles Selection

Standard signal waveforms Judging activity is difficult!

PowerArtist Activity Viewer Easy to identify unexpected activity

Constant Activity?!

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DEF

RTL-to-GDS Power Integrity module PA ( ... always @ (posedge clk) begin dout

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Power Gates’ Efficiency Integrity concerns with Power Gated Designs

How long to reach nominal supply? How big is the rush current? Is the Ramp-Up homogeneous? What about the coupling noise with top level? What is real “OFF State” leakage?

Header

Footer

Block

Vdd External

CTL

CTL

Block Vdd_int Vss_int

Vss External

Power Gates Physical Implementation

Ileak

time

V

time

I Rush Current

Vdd Internal

ON

ON

VON?

∆time?

Peak? LeakOFF? LeakON?

RedHawk-Explorer Low Power Analysis Checks

1

2 4

3

5

Coupling Noise at Top Level Instance Voltage over time

time

V

1 2 3 4 5

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Power-Thermal Efficiency

TEMPERATURE POWER

Leakage

Leakage Dependency on Temperature Sub-threshold voltage is temperature dependent

Self Heating

Chip-Package Power-Thermal Convergence Analysis

SoC Heat Flux, per layer

Package Layout

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Flagship Technology

ANSYS Fluent™ • Aerodynamics • Engine Combustion • Thermal Management

ANSYS Mechanical™ • Static Structural • Vibration and Stress • Component Design

ANSYS HFSS™ • EMI/EMC Certification • Wireless Connectivity • Electric Motors, Battery

ANSYS RedHawk™ • RTL2GDS Power Noise • Foundry Certified Reliability • C-P-S Power, Signal, Thermal

© 2013 ANSYS, Inc. ANSYS-Apache Confidential 13 Apache Design, A subsidiary of ANSYS

Thank you

Merci

Optimize Power Consumption & Delivery �from RTL to GDSIt is all about Power!How do we control the Power?Use case: Gated ClockUse case: Data PathPowerArtist: RTL Power MetricsPACE: RTL Power PredictabilityActivity Analysis coverageRTL-to-GDS Power Integrity Power Gates’ EfficiencyPower-Thermal Efficiency Flagship TechnologySlide Number 13