38 February 2011

Ali Hajimiri

Digital Object Identifier 10.1109/MMM.2010.939321

Date of publication: 14 January 2011

Ali Hajimiri (hajimiri@caltech.edu) is the Thomas G. Myers professor of electrical engineering at the California Institute of Technology (Caltech) and director of the Microelectronics Laboratory.

Next-Generation CMOS RF Power Amplifiers

Ten years ago, it was widely accepted conventional wisdom that watt-

level fully integrated power amplifi ers (PAs) were not feasible in

standard complimentary metal-oxide-semiconductor (CMOS) tech-

nology. Today, millions of such devices are commercially produced

and shipped every month and are used in hundreds of millions of

cellular phones across the world. Such dramatic transition from being considered

an impossibility even by most optimistic academics to the obvious future direc-

tion to be followed by everyone happened through a series of demonstrations

based on new architectures radically different from the known PA topologies

applied over more than half a century.

1527-3342/11/$26.00©2011 IEEE

FOCUSED

ISSUE FEATU

RE

© PHOTODISC

February 2011 39

CMOS technology presents several challenges to

the implementation of a fully integrated high-power

radio-frequency (RF) PA, in particular, low transis-

tor breakdown voltage and lossy on-chip passive

elements [1]. However, these challenges could be

completely trumped by CMOS’s most potent weapon

of all: a practically unlimited number of transistors

to design with. This unlimited number of transis-

tors integrated on a single silicon chip is similar to

an army of ants that, when harnessed in unison, can

overwhelm the elephant of compound semiconduc-

tors and module technology. In fact, the main reason

so many inaccurate predictions about the impossi-

bility of fully integrated watt-level CMOS PAs were

made in the past was that they were based on the

assumption of using the same or similar topologies

as those used in the compound semiconductor PAs.

This assumption, however, completely discounts the

power of parallelism offered by the practically infinite

number of transistors available in today’s CMOS pro-

cess technologies. The (practically) unlimited num-

ber of transistors available in CMOS not only can be

used to generate a large amount of RF power when

used in conjunction with innovative combining tech-

niques but also can be further exploited to make high-

efficiency transmitter architectures for nonconstant

envelope modulation schemes. In this article, we will

discuss the thought process behind the development

of some of the techniques that resulted in the emer-

gence of CMOS as a viable technology for fully inte-

grated watt-level PAs and fully integrated radios.

Metal-oxide-semiconductor (MOS) transistors were

not considered true RF transistors until the early

1990s, and, even then, the notion of CMOS RF was per-

ceived by many as an academic exercise with no com-

mercial value. However, the continued scaling of the

CMOS minimum feature sizes led to faster MOS tran-

sistors to the point that it became possible to use them

in lower-frequency commercial RF applications at the

turn of the century. Unfortunately, this increase in

speed (higher fT and fmax) came at the price of lowered

breakdown voltages due to the smaller dimensions of

the transistors. This was not a major challenge for the

small-signal blocks except for some loss of dynamic

range, which is often easily justified considering the

benefits of integration. Even for most large-signal

blocks, such as oscillators and mixer, the loss of volt-

age swing can be countered with topological modifica-

tions and device-size adjustments. However, the

limitations imposed by the low-voltage han-

dling capability of the modern MOS

transistors is much more severe

in PAs and cannot be dealt

with as easily, as shown

in the following simple

example.

The ac power PL, delivered to

the load RL, is related to the peak volt-

age amplitude Vamp of a sinusoidal source

through

PL5Vamp

2

2RL.

Assume that we would like to deliver 1 W of RF power

into a 50 V load at 2 GHz. This is a representative

Dra

in V

oltage,

Dra

in C

urr

ent

Dra

in V

oltage,

Dra

in C

urr

ent

Dra

in V

oltage,

Dra

in C

urr

ent

Current Current CurrentVoltage Voltage Voltage

Time Time Time

Dra

in V

oltage,

Dra

in C

urr

ent

Current Voltage

Vbk

Time

Dra

in V

oltage,

Dra

in C

urr

ent

Current Voltage

Vbk

Time

More Voltage

More Current

Figure 1. Constant power scaling: how the same output RF power can be achieved with different levels of voltage and current.

40 February 2011

example of the power levels needed in cellular com-

munication standards Global System for Mobile Com-

munications (GSM) and General Packet Radio Service

(GPRS). Using the above expression, we can easily

determine the peak-to-peak voltage swing across the

load to be 20 V. This is too high a voltage to directly

appear across the drain-source of a transistor with

small enough feature size to provide the necessary

power gain at the frequency of interest. The maximum

voltage handling capability of a single 130 nm CMOS

transistor is in the range of a few volts, not tens of volts.

For example, if reliability issues in the transistor dic-

tated a maximum voltage swing of 2 V, only a power of

10 mW could be deliver to a 50 V load if it were driven

directly by the transistor. Something must be placed

between the transistor and the load if higher power

levels are needed.

The classical solution to this problem is trading cur-

rent for voltage, as shown in Figure 1. This is achieved

through impedance transformation. The concept is

quite simple, the instantaneous power is the product of

the voltage and current, so the large voltage swing nec-

essary at the load can be obtained using a network of

passive elements that transfer it to a lower impedance

at the driving transistor. This allows the transistor to

have a larger current and a smaller voltage swing. This

is advantageous as the voltage handling capability

of a single transistor is essentially determined by its

physics while its current handling can be adjusted by

changing its effective width or the number of parallel

transistors. Although this solution can work in theory,

the classical impedance transformation approaches

are not very effective when the ratio of the power

needed at the load 1PL 2 and the power the transistor

can directly generate 1Pdir 2 is large. This ratio is called

power enhancement ratio (PER) [2] and is easily deter-

mined to be given by

E ;PL

Pdir

5 r.hp,

where r is the impedance transformation ratio and hp is

the power efficiency of the passive matching network.

(In the earlier numerical example, the power enhance-

ment ratio is 100.) For a multistage inductance-capaci-

tance (LC) matching network [Figure 2(a)] with a fixed

inductor quality factor (Q) it is possible to calculate

the highest possible passive efficiency as a function of

PER for the optimum number of LC matching sections

[2]. The result of this calculation is plotted in Figure 3,

where the maximum achievable passive efficiency is

plotted versus PER for the optimum number of stages

designated as n. It is easy to see from Figure 3 that,

for a PER of 100, even with an inductor quality factor

of 10, the passive efficiency of the output matching

network alone is around 50% (achieved with three LC

stages). This efficiency will be multiplied by those of

the active device and the previous stages, leading to

unacceptably low power efficiency for the completed

PA. Therefore, it is clear that an integrated LC match-

ing network cannot be used effectively to implement a

watt-level CMOS PA due to the strong dependence of

the efficiency on the power enhancement ratio.

Unlike an LC matching network, a transformer-

based matching network’s efficiency does not have a

strong dependence on the PER, assuming a given Q and

Resonant LC Match(a)

Rload/r1r2r3 Rload/r2r3 Rload/r3

Rload

First Stage Second Stage Third Stage

Magnetic Transformer

(b)

50/N2 Ω50 ΩLoad

1:NImpedance

Transformer

Figure 2. (a) An LC resonant match. (b) A magnetic transformer match.

0 10025 50 75

100

0

20

40

60

80

Power Enhancement Ratio (E )

Effic

iency,

η (%

)

n = 2 n = 3

QL = 50

QL = 15

QL = 10

QL = 5

n =

4

QL = 8

Figure 3. Passive efficiency versus power enhancement ratio for the optimum number of LC matching sections as a function of Q [1].

Ten years ago, it was widely accepted conventional wisdom that watt-level fully integrated PAs were not feasible in standard CMOS technology.

February 2011 41

a high coupling factor k [2]. Therefore, a transformer-

based matching architecture [Figure 2(b)], where a

high k can be maintained, offers a more realistic way

of achieving the impedance transformation necessary

from a large number of transistors (necessary to carry

a lot of current) to a large resistor (needed to deliver a

large voltage swing). Several CMOS PAs using trans-

formers with multiple primaries and single secondary

performing power combining and impedance match-

ing at the same time have been reported [1]–[7].

An intuitive way to see why transformers are supe-

rior to LC-matching networks when a large transfor-

mation ratio is needed is to note that there is more

energy stored in an LC-matching network than a trans-

former. Consider the example illustrated in Figure 4,

where a single stage LC match and a transformer per-

form an impedance transformation to convert a 1 V,

7 A swing at the drain of the transistor to a 7 V, 1 A one

at the load. The reactive energy stored in the LC match

[Figure 4(a)] is 49 J, while the reactive energy stored in

the transformer [Figure 4(b)] is roughly 7 J. Consider-

ing that quality factor is the ratio of the energy stored

to the energy dissipated per cycle, we can see that, for a

given Q, there is more power loss in the LC match than

the transformer simply because there is more energy

stored in the LC match.

There are some practical limitations to the basic

transformer matching. Large transformation ratios

result in impractically small inductance on the pri-

mary. This, in turn, leads to a larger fractional ohmic

loss in the transformer, diminishing some of the

intended benefits of such matching scheme. This

problem can be dealt with by taking advantage of the

isolation between the primary (or primaries) and the

secondary windings of transformers to use multiple

primary windings to couple to a single secondary. This

is highly conducive to the parallelism necessary for

providing a large current by the transistor and leads to

a very natural way of performing an impedance trans-

formation and power combining, at the same time not-

ing that multiple primaries can be used to couple to the

same secondary. The most straightforward approach is

to have multiple primaries each driven by an indepen-

dent amplifier couple to the secondary. This way, mul-

tiple amplifiers can be power combined to produce the

large voltage swing on the secondary, where no active

element exists. While this is a major step forward, it

still poses other practical limitations due to the layout

geometrical constraints of on-chip inductors.

To obtain a reasonable operation at higher power

levels, different primary windings of the transformer

should be well isolated. This limits the practical lay-

out options, as most classical approaches to such lay-

out result in significant overlap and/or proximity of

different primaries and is, hence, suboptimal. One

approach that does not suffer from such limitation is

using slab inductors (Figure 5) on the primary and

the secondary, where the secondary slab inductors are

placed in series in the form of a polygon, as shown in

Figure 6. This arrangement minimizes the coupling

between the various primaries while allowing the use

of slab inductors, which offer a higher Q for a given

inductance.

Note that the individual differential amplifiers can-

not be directly connected across the two terminals of

the slab primary. This is because the two terminals of

a slab inductor are not in the same physical location,

making it impossible to attach a small circuit element

Resonant Match

Lp

Input

Cs

Rin

Rload

7 V7 V1 V

7 A 7 A1 A

Inductor Stored Energy = 49 J

Rload

Input

7 A 1:7

M

1 A

1 A7 A

1 V 7 V

7 V

Transformer Match

Inductor Stored Energy ≈ 7 J

(a)

(b)

Figure 4. The energy stored in (a) LC match and (b) transformer.

? ?

? ?

Figure 5. The connection challenge of a slab inductor.

The instantaneous power is the product of the voltage and current, so the large voltage swing necessary at the load can be obtained using a network of passive elements.

42 February 2011

to both terminals without long interconnecting wires,

which produce additional loss and inductance, as illus-

trated in Figure 5. This is not a problem in the second-

ary, as the secondary slabs are all in series and form

one closed loop in the secondary. However, connect-

ing a capacitor or differential drive transistors across

the primary inductors poses a practical problem. For-

tunately, this problem can be solved by noting that,

when each primary operates in a differential mode,

the voltage on the opposite side of a primary would

be essentially the same as the voltage on the near end

of the adjacent primary inductor. This key observation

allows the differential driver and the resonant capaci-

tor to be connected between the neighboring ends of

adjacent slab inductors, as shown in Figure 6, resulting

in the same circuit behavior as if they were connected

across the primary inductors. This structure is known

as distributed active transformer (DAT).The first watt-level fully integrated CMOS PA was

implemented using the DAT architecture in 2000 and

reported in 2001 [1]. It was a 1.9 W, 2.4 GHz CMOS

PA implemented using 350 nm CMOS transistors. It

achieved a peak power-added efficiency (PAE) of 41%,

running off of a 2-V power supply with a die area of

2.6 mm2. Although it was implemented at the 2.4-GHz

industrial, scientific, and medical (ISM), the power lev-

els were clearly suitable for cellular applications such as

GSM/GPRS, which were solely addressed by compound

semiconductors and exotic module technologies at the

time. Its die micrograph is shown in Figure 7. Many dif-

ferent DATs have been successfully demonstrated by

several teams [1]–[5] over the last decade.

While demonstration of a fully integrated watt-level

CMOS PA was a major achievement at the time, there

still existed several challenges before DAT-based PAs

could be deployed as commercial products. Perhaps

the most pressing was the need for the PA to run off of

a Li-ion battery with a cell voltage of 3.6 V, which would

be even higher when the battery is being charged. This

posed another breakdown voltage challenge to the

PA, which is more of a dc nature as opposed to the ac

excess voltage swing problem the original DAT was

designed to solve. In the standard DAT (or other clas-

sical PA topologies), this intrinsically larger supply

voltage directly appears on the drain of the transistors

serving as the average value of the ac signal swing on

the drain, resulting in larger peak voltages.

While it is conceivable to solve this problem with a

step-down dc-to-dc converter, it is neither cost-effective

nor practical to do so due to the required extra elements

(at least one external inductor), the added efficiency hit,

and switching noise issues. Therefore, the ideal solution

should allow application of the large supply voltage to

the PA directly, where it is used in the PA to generate the

necessary voltage swing at the output.

In a standard single-concentric DAT like the one

shown in Figure 6, the dc supply voltage is directly

seen by the transistors in the amplifier cores. A first

step in solving this problem is using cascode architec-

ture in the cores to divide the voltage swing between

the two transistors, where each transistor experiences

roughly half of the voltage swing. While this alleviates

the problem to some extent, it is not enough to imple-

ment a reliable watt-level CMOS PA in a 130-nm CMOS

process that may have to withstand supply voltages as

high as 6 V while experiencing a load mismatch condi-

tion in a worst-case scenario.

Gnd Gnd

Output

vdd

Gnd Gndvdd

vddvdd

tput

vdd

G dG G dGGGGGGvdd

vdvdd

Figure 6. The basic distributed active transformer [1]–[3].

Input

Outp

ut

Transistors

Primary Winding

Secondary

Winding

Figure 7. The die micrograph of the first distributed active transformer [1].

Gnd GndGndGnd

Output

vdd

vdd

vddvdd

Gnd GndGndnGnd

tput

vdvdd

Figure 8. A double concentric distributed active transformer with cascode cores [4].

February 2011 43

This challenge can be overcome by noting that the

standard single-concentric DAT of Figure 6 consists of

slab inductors that are driven by the differential cores

in the corner, effectively creating a virtual ground in the

middle of the slab. This is where the supply voltage is

applied to the PA. The key insight is that the same vir-

tual ground point can, in principle, serve as the ground

connection of the core of another PA. The two PAs can be

combined in a concentric fashion where they both cou-

ple magnetically to the same secondary loop, as shown

in the double-concentric quad-core DAT of Figure 8 [4].

This way, the two sets of DAT primaries are stacked

from the dc perspective, while they operate in parallel

from an ac point of view. The inner and the outer cores

share the same dc current, while they divide the supply

voltage almost equally between them. This reduces the

voltage experienced by each PA by a factor of two, while

they each contribute half of the RF power at the output

by magnetically coupling to the secondary. This concen-

tric stacking can be repeated multiple times if necessary.

These techniques were used to implement a fully

integrated quad-band CMOS PA in a standard 130-nm

CMOS process, operating off of a 3.6-V battery to sup-

port GSM/GPRS at 850 MHz, 900 MHz, 1.8 GHz, and

1.9 GHz [4]. The PA has an overall PAE of 51% while

producing 135 dBm (3.2 W) of output power in the

extended-GSM (E-GSM) band. The PAE includes the

losses of the PA, on-chip closed loop power control,

and the packaging. The high-band PA in the PCS band

achieves a PAE of 45% while generating up to 33 dBm

(2 W) of power at 1.85 GHz. The PA works with power

supplies in the range of 2.9–5.5 V and can withstand a

6-V power supply under voltage standing wave ratio

(VSWR) of greater than 15:1 under all phase angles,

showing no oscillation, breakdown, or long-term deg-

radation over extended periods of testing. The die

micrograph of this chip is shown in Figure 9.

Figure 9. Die micrograph of the quad-band GSM/GPRS power amplifier of [4].

Digital

Controller

LBB+

CM

LO

+

LO

–

On-Chip

Iout–

Iout+

PAD

RLoadEnvelope (BB)

6

6

t

t

Phase (LO)

Bypass

6 6

PM0

PM13

PM15

PM14

VDD

C1

C2

RF Output

–+

LBB+

LBB–

LBB–

Analog

BB

Distributor

Analog

BB

Replica

Linearizer

Array

BBin+ BBin–

t

Digital LO Distributor

1:2

6 6

CM

6

Digital Control

Figure 10. The block diagram of an RF transmitter based on a power mixer array [11].

For a given Q, there is more power loss in the LC match than the transformer simply because there is more energy stored in the LC match.

44 February 2011

These demonstrations show the path the fully

integrated CMOS PA took from being an oxymo-

ron to a reality, where hundreds of millions of units

have been shipped and the prospects for the future

shipments are growing. While integration of a PA in

CMOS has produced significant cost and area reduc-

tions, its real power lies in the ability to integrate the

PA and the transceiver on the same die. In addition

to the classical benefits of such integration, namely

interface elimination and cost/size reduction, such

integration provides an opportunity to utilize new

architectures not practical with the PA and the trans-

ceiver on two separate chips. Such architectures are

of particular interest in the case of nonconstant mod-

ulation schemes. As an example, the following briefly

discusses the power mixer array concept that makes

it possible to implement a CMOS full transmitter for

nonconstant envelope modulation schemes.

The spectral efficiency of nonconstant envelope

modulation schemes has turned them into an attrac-

tive option for wireless communications where there

is constantly growing demand for scarce spectral

resources. Traditionally, in these modulation schemes,

the data is modulated at the baseband, upconverted

by transmitter to the desired frequency, and, finally,

amplified using a linear PA. The DAT-based PAs of

[1]–[4] were designed for quasi-constant-envelope

modulation schemes such as GSM/GPRS and must be

modified for use in nonconstant modulation schemes.

Although several linearization techniques have been

devised over the last half-century (e.g., [8]–[10]),

many of them are not conducive to a fully integrated

implementation because they either require long,

low-loss transmission lines, or dc-to-dc converters

that need an external inductor and large switching

currents. A linear PA is used to maintain the integ-

rity of the modulated signal and avoid detrimental

out-of-band emission due to

spectral regrowth. Although

it has been possible to make

linear PAs capable of faithful

amplification of such signal,

they are usually less efficient

than their nonlinear, switch-

ing counterparts.

The ability to fully inte-

grate a PA in a CMOS process

enables attractive alterna-

tives to generate noncon-

stant envelop modulations

without resorting to strictly

linear PAs. Many solutions

RFout+ RFout–

M7

M1 M2

M8

M6M5M4M3BB+ BB–

BB–

LO–LO+

Figure 11. The power mixer core used in the power mixer array [11].

–60

–50

–40

–30

–20

–10

0

10

–10 –7.5 –5 –2.5 0 2.5 5 7.5 10Frequency Offset (MHz)

(dB

m/1

0 k

Hz)

POut = +25.0 dBm

BA Mode, Frequency = 1.75 GHz, BW = 5 MHz, 99.9% PAPR = 8.5 dB

EVM = 4.9%

Figure 12. The measured spectrum and constellation of WiMax signal [11] operating in baseline analog (BA) mode.

1.6 mm

1.6

mm

Power Mixer

Array

Digital LO

Distributor

Output

Network

Analo

g B

B R

eplic

aLin

eari

zer

Arr

ay

Analo

g B

BD

istr

ibuto

r

Digital

Controller

Figure 13. The die micrograph of the power mixer array of [11].

The spectral efficiency of nonconstant envelope modulation schemes has turned them into an attractive option for wireless communications.

February 2011 45

have been proposed to deal with this problem, such

as amplitude elimination and restoration techniques,

which could operate based on polar modulation. One

such solution is the power mixer array (Figure 10),

which selectively applies the local oscillator (LO) sig-

nal to a sufficient number of individually linearized

power up-conversion mixers, to generate the neces-

sary output power while maintaining linearity and

high back-off efficiency [11]. The outputs of the mix-

ers are current combined at their drains, where the

nonconstant envelope modulated signal is restored.

The modulated signal is impedance transformed into

the external load impedance by an on-chip trans-

former, which does not degrade the spectral purity of

the transmitted signal due to its linear nature. High-

power efficiency can be expected from a current-com-

muting mixer since its lower-tree common-source

transistors operate in the switching mode between the

triode and the cut-off regions [11]. To obtain higher-

voltage-handling capability and improved reliability,

a double cascade is used, where the top transistor is

a thick gate oxide for better voltage handling capa-

bility, as shown in Figure 11. The phase information

is carried through the phase-modulated LO, which is

selectively applied to the desired number of power

mixer cores by the digital LO distributor. The choice

of how many and which power mixers receive the

digital LO is controlled by an on-chip digital control-

ler. The baseband amplitude signal is applied to the

middle-tree differential pair, thereby eliminating the

need for a supply voltage modulator commonly used

in standard envelope elimination and restoration

techniques. Analog baseband replica linearizers are

used to linearize the differential baseband envelope

signal, which is applied to the power mixer cores via

an analog distributor.

A prototype was fabricated in a standard 130-nm

CMOS process [11] with PAE greater than 40% between

1.6 GHz and 2 GHz with a peak of 42% and the output

power greater than 1 W over an octave from 1.2 GHz

to 2.4 GHz with a maximum output power of 131.3

dBm. The linearized analog (LA) mode [11] operation

achieves an output 1 dB compression point of 131.3

dBm, providing a very large linear range. In the LA-

mode, a 16 quadrature amplitude modulation (QAM)

modulated signal with a symbol rate of 50 ksym/s at

1.8 GHz, an error vector magnitude (EVM) of 5% is

measured with an average output power of 127.6 dBm

and an overall PAE of 18%. In the efficient segmented

(ES) mode, cores are dynamically activated in units

of 4, and the measured PAE improves to 26% with an

average output power of 126.5 dBm and an EVM of

4.5% despite the 16-QAM’s nonconstant envelope with

a peak-to-average power ratio of 6.7 dB. Additionally,

wideband code-division multiple access (WCDMA)

and worldwide interoperability for microwave access

(WiMax) modulated output signals are successfully

measured with a linear output power of 128 dBm, a

PAE of 30%, and an EVM of 2.9% for WCDMA and

maximum linear output power of 125 dB, a PAE of

20%, and an EVM of 4.9% for WiMax. The measured

spectrum and constellation of a WiMax signal with 5

Msymb/s in the baseline analog (BA) mode is shown

in Figure 12. The die micrograph of the power mixer

array is shown in Figure 13.

It can be seen through these demonstrations that it

is indeed possible and beneficial to implement a fully

integrated watt-level CMOS PA by using novel archi-

tectures that leverage the large number of transistors

available in CMOS process technologies. Such inte-

gration enables innovative transmitter architectures,

leading to power and area efficient radio transmit-

ters in CMOS, enabling the next generation of radio

transceivers.

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