JEE2600 – INTRODUCTION TO DIGITAL LOGIC AND COMPUTER DESIGN

ModelSim Tutorial

Prepared by: Phil Beck

9/8/2008

This document provides a general tutorial on how to use ModelSim to create, debug, and verify a design writing in VHDL. This tutorial uses ModelSim version 6.2 and was prepared using the resources available from the CEC lab. Behavorial modeling is used to describe the operation performed by the voter function. The design is contained in file 3inputVoterBehCase.vhd. The testbench used to verify this module is 3InputVoterTestBenchforCase.vhd.

Voter

Function

Pass is only a 1 when two or

more of the Vote inputs are a 1.

Vote 1

Vote 2

Vote 3

Pass

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ModelSim is available on Windows machines available in the CEC lab and perhaps also on the Linux

machines. For this tutorial, Remote Desktop was used to access the CEC resources remotely. In order to

access the CEC machines locally or remotely, you must get a login. Using Remote Desktop, type in the

computer name given below and click Connect. You will then get the login screen for your user name

and password as shown.

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After a short period of time, you should get a standard Windows Desktop. From there, select the

ModelSim 6.2 program as shown below.

For this tutorial, we’ll start off by creating a new Project file. This is done by selecting File, New, and

Project… as shown below. This will generate the Create Project dialog box also shown below. By

default, ModelSim will open the Project file that was in use when you last closed ModelSim. In the first

Window below, the VHDL code shown is from the project that was last used when ModelSim was

previously exited.

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It is recommended that you create a new directory for your project. This is down by defining the

directory in the Project Location textbox and it will be created when you click OK. In this example, the

directory called Tutorial was added. Then the title of the project was added in the Project Name text

box.

After clicking OK, the Add items to the Project dialog box will appear as shown below.

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At this point, you would most likely click the Create New File icon so you can begin entering VHDL code.

The Create Project Dialog box will then appear allowing you to enter the file name for your VHDL

module as shown here.

For this tutorial, I had previously created the VHDL modules using a text editor so I have no need to

create a new file from scratch here. Also, I copied the VHDL modules I want to use here to the Tutorial

directory so they could easily be added to the project by clicking Add Existing File icon. Clicking this icon,

the Add file to Project dialog box appears as shown below.

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Clicking the Browse… button above results in the following dialog box.

The 3inputVoterBehCase file was added to the project by clicking the Open button. Note that the file

name now appears in the Workspace window as shown below.

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We can add additional files or create new ones later. Let’s compile the program we just added but first,

open it by double-clicking on the file name in the Workspace window so that the actual code can be

viewed as shown below.

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Next, let’s compile it. Use either the Compile Selected or Compile All selection as shown below.

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Note that as the program is compiled, the status of the compile appears in the Transcript window. The

Transcript window records that actions you have taken and the results of these actions.

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Note that the compile was successful as noted in the transcript window. If there were errors, they

would be noted there. You can view the errors and get a better idea of what is wrong by double-clicking

on the error message in the Transcript window.

Now let’s add our simple testbench vhdl program that will test our voter module. To add in an existing

file (or to create a new file), click on the Project tab. Note, if the Project tab doesn’t appear, click

somewhere within the Workspace window. Then select add an existing file. For this example, the

3InputVoterTestBenchfor Case.vhd file will be added which is the testbench for the 3 input voter

function.

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Now, we need to compile the test bench module just like we did before. Please note, since the test

bench references the entity in the 3inputVoterBehCase file, the 3inputVoterBehCase file must be

compiled first. Since it was previously compiled, we can proceed with compiling

3inputVoterTestBenchforCase file. Under the Compile tab, the order of the compiles can be set if more

than one compile is being performed.

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Both files were compiled since the compile all option was selected. Both compiles were successful but

the test bench had a few warnings. (The warnings are due to the way I designed the test bench in that it

is effectively an infinite loop. I am using the run-time setup of the simulator to get around this potential

infinite loop problem.) We can now use the simulator to verify our voter module does what we want it

to do.

Before we invoke the simulator, we will set up the runtime options for the simulator (it runs for a finite

period of time). Based on the way the test bench is designed, it will take 800 nsec to cycle through all

input conditions. Therefore, we’ll set the runtime option for the simulator to run just for just 800 nsec.

Click the Simulate tab, then click the Run-time tab. Select the Default Run to be 800 nsec as show

below. Click okay.

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Click the Simulate tab again, then select Start Simulation menu will appear as follows.

Click on the + in front of the work library (contains the design). Then select the test bench to be

simulated as shown below. Also, disable optimization as shown. Click okay.

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The Transcript window should indicate a successful loading of all of the necessary libraries to support

the simulation and the Workspace will provide the architecture and process references to the test bench

as shown below.

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We will validate this design by using the wave window available in Model Sim. The wave window will be

set up to display the test signals generated by the Test Bench and applied to the inputs 3-input voter

module. Then the output of the 3-input voter will also be displayed so it can be verified that the output

of the 3-input voter is a 1 when two or more of the voter inputs are a 1. To activate the wave window to

display the voter inputs and output, right click on the DUT (the 3-input voter is the DUT) as shown here

by Add to Wave.

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The wave window will appear like below. With some small adjustments, the windows can be size so a

full 800 nsec of time appears in the wave window along with the inputs and output for the voter.

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The next step is to actually run the simulation. This is done by clicking on the Simulate tab and clicking

Run as shown below.

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The simulator should run for 800 nsec and the waveforms should be created as shown below. Note

that the output is only a 1 when two or more of the inputs are a 1.

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The wave window can be saved off as an image file so it can be included as part of an assignment. To do

this, make sure the wave window is active (click somewhere on it), then click the File tab – then Export,

and then Image.