Methods for Manufacturing Improvement IEOR 130 Prof

Semiconductor Manufacturing

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Methods forManufacturing Improvement

IEOR 130

Prof. Robert C. LeachmanUniversity of California

at Berkeley

August, 2020


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IEOR 130• Purpose of course: instill cross-disciplinary,

industrial engineering perspective and skills in future engineers, managers or researchers for technology-intensive manufacturing

• Course prerequisites: calculus, linear algebra, statistics and probability. Physics recommended.

• Course assignments: ~ 9 homework exercises, midterm exam, final exam

• Course grade: Max { F, 0.67F + 0.33M}


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Instructors and readings• Prof. Rob Leachman, 4127 Etcheverry Hall

– Office hours MWF 11-12 (class days only) or by appt, [email protected]

• GSI Ahmad Masad– Office hours TuTh 1230-2 or by appt., [email protected]

• Course web site: http://ieor.berkeley.edu/~ieor130

• Course outline, presentation slides, required readings, HW and HW solutions are all posted on the course web site

mailto:[email protected]

mailto:[email protected]

http://ieor.berkeley.edu/%7Eieor130


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TopicsWhat matters in high-tech manufacturing:• Process control – We need a stable manufacturing process. We

need to consistently make good product.

• Yield analysis – We need to identify root causes of quality losses and eliminate them.

• Equipment efficiency – We need to achieve good return on very expensive equipment assets. We need to understand capacity and plan investments wisely.

• On-time delivery – We need to promise delivery dates we can achieve, and we need to achieve them.

• Speed (AKA cycle time) – For competitive reasons and economic reasons, we need manufacturing to be fast.


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Technical Topics and Relationshipto Other IEOR Courses

• Statistical Process Control (IEOR 165), Process Controllability and Six Sigma Analysis

• Statistical Yield Analysis• Maintenance Scheduling Under Uncertainty (renewal

models, IEOR 172)• Equipment Efficiency Measurement • Production Planning (IEOR 150 & 162) and Delivery

Quotation• Factory Floor Scheduling (IEOR 150) and Management of

Work-in-Process• Economics of Speed (Continuous-time discounting of

cash flows, E120)• Cycle Time Analysis (Queuing analysis, IEOR 173 & 151)• Capacity Planning


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Course Outline• Introduction to Semiconductor technology and

manufacturing (today, Friday and next Monday)

• Statistical process control (9/2 – 9/11)

• Yield analysis (9/14 – 9/18)

• Equip maintenance & efficiency analysis (9/21 – 9/25)

• Production Planning, On-time delivery (next)

• Cycle time analysis (after midterm)

• Line Scheduling (after midterm)

• Benchmarking best manufacturing performance and practices (course wrap-up)


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Introduction to Semiconductor Technology

• Semi-conducting materials (Germanium, Silicon, Gallium Arsenide) - insulator if pure, conductor if “doped” with particular impurities

• Crystalline structure allows relatively large gains in current and generates current from applied voltage

• Transistors were made out of Germanium beginning in the 1950s


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Semiconductor Technology (cont.)• Integrated circuits were made out of Silicon

beginning in the 1960s, a much more suitable material (wider semiconductor band gap, higher melting point)

• 1958-59 - Jack Kilby of Texas Instruments proposed complete circuits (resistors, capacitors, diodes, transistors) made out of silicon; prototype was fabricated out of Germanium, with connecting wires attached to “mesas”


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Semiconductor Technology (cont.)• 1959-60 - Robert Noyce and others at Fairchild invent

the planar fabrication process:Photolithography – isolate patterned areas of silicon wafer

Diffusion – using a furnace, “dopants” are diffused into the silicon to define the circuit elements

Apply film of SiO2 (an insulator as well as a protective coating) –also done with diffusion furnaces

Etch holes or “vias” through the SiO2 to expose the circuit elements

Evaporate aluminum into the vias to connect up circuit elements


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Microelectronics: Scale ofIntegration

Scale Number of Logic First UseElements Per Chip

Small (SSI) 1-10 1960Medium (MSI) 1-100 1965Large (LSI) 100 -10,000 1970Very Large (VLSI) 10K - 1M 1975Ultra Large (ULSI) > 1M 1985

> 100M 1998> 1B 2005> 1G 2010


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Process Technologies• BiPolar - Areas of silicon are doped to be either poor or

rich in electrons. Both polarities are used (“p-type” and “n-type”) to define individual circuit elements.

• MOS (Metal Oxide Semiconductor) - Doping to define each circuit element is entirely of one polarity, simplifying the manufacturing process. NMOS is faster than PMOS, because electrons are more mobile than “holes”.

• CMOS (Complementary MOS) - Both p-type and n-type transistors are fabricated; the same signal that turns on one turns off the other, thereby affording substantial power savings and more dense circuitry.


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Device TechnologiesTechnology Primary Period of

Applications UseSiliconBiPolar Computers, consumer products 1960-PMOS Early microprocessors 1965-75NMOS Memory, microprocessors 1970-90CMOS Battery-powered equipment 1970-CMOS (high-speed) Most new designs 1980-

Gallium Arsenide Microwave radio, radar 1975-(GaAs) Optoelectronics 1980-

Power controllers 1990-


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Product Categories• Standard products - many customers

– “commodity” memory

– microprocessors and microcontrollers

• Programmable devices - many customers– user programs the device

• Application-specific integrated circuit (“ASIC”) - one customer, one supplier

– Gate Array (metalize customer-selected options on generic semi-finished wafer)

– Standard Cell (custom product right from blank wafer start)

– Full custom


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Types of Companies

• Integrated Device Manufacturer (product design, process technology development, manufacturing, marketing)

– e.g., Intel, Samsung, Micron

• Fabless (product design and marketing only)– e.g., Qualcomm, Nvidia, SanDisk, Apple

• Foundry (development of process technology and contract manufacturing only)

– e.g., TSMC, UMC, GlobalFoundries


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Semiconductor Milestones• 1948 - transistor invented at Bell Labs

• 1954 - silicon transistor perfected at Texas Instruments

• 1959 - Bi-Polar fab process for integrated circuits perfected at Fairchild Semiconductor

• 1963 - Fairchild captures TV electronics market

• 1967-70 - mass exodus from Fairchild to start-up companies; Silicon Valley is born


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Milestones (cont.)• 1967 to 1971 - MOS process perfected by Gordon

Moore and Andrew Grove, Intel develops DRAM, Intel develops EPROM, Intel develops MPU

• Early 1980s - Japanese companies perfect CMOS, capture most of memory market over the decade

• Late 1980s - Americans catch up in CMOS, dominate logic markets

• Early 1990s - Koreans take the lead in memory

• Late 1990s - Taiwan firms dominate foundry business


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Global Semiconductor Sales

• 1985: $27.8 billion (48.9% US cos., 41.2% Japan cos.)

• 1995: $144.4 billion (40.9% US, 38.9% Japan)

• 2005: $227.4 billion (48.3% US, 22.6% Japan)

• 2014: $335.8 billion (memory $79.2 billion, µPUs and µCUs $62.1 billion, other logic $91.6 billion, analog $44.4 billion, discretes $20.2 billion, power $11.9 billion, all other $26.4 billion)

• 2018: $468.8 billion


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2013 Revenues by Company1. Intel $48.0 billion (15.2%)2. Samsung Electronics $29.6 billion (9.4%)3. Qualcomm $17.3 billion4. SK Hynix $12.8 billion5. Micron Technology $11.8 billion6. Toshiba $11.5 billion7. Texas Instruments $10.6 billion8. ST Microelectronics $8.1 billion9. Broadcom $8.0 billion10. Renesas $7.8 billionAll other $149.9 billionTotal $315.4 billion


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Semiconductor Manufacturing Process

• Grow ingots of pure Si and slice into wafers about 300 microns thick

• Many identical integrated circuits are fabricated on the wafer in the wafer fabrication process

• Each integrated circuit on the wafer is termed a die or a “chip”

• Dice up the completed wafer and package the chips in plastic or ceramic housings with electrical leads(the assembly process)


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Manufacturing Process (cont.)

• Fabrication Plant - carries out wafer fabrication process and wafer probe (“die sort”); fabrication plant sometimes called wafer fab for short

• Back End Plant - carries out assembly process (including wafer dicing) and device testing

• State-of-the-art 300mm 50 nm wafer fab (with capy of 30K wafer starts per month) ~ $5 B US

• State-of-the-art back end plant ~ $400 M US


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Device Feature Sizes

• Generations of the same device type are differentiated by the minimum feature size, measured in nanometers (billionths of a meter)

• Each new generation of a device type requires more sophisticated and expensive processing equipment

• The equipment set in a semiconductor fabrication plant has a capability as to the minimum feature size of the devices that can be produced


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Feature SizesMinimum Logic MemoryFeature Size Device Device1.2 micron 286 256K DRAM1.0 micron 386 1M DRAM0.7 micron 486 4M DRAM0.5 micron Pentium 16M DRAM0.35 micron Pentium Pro 64M DRAM0.25 micron P III 256M DRAM0.18 micron P IV 1G DRAM0.13 micron 4G DRAM90 nanometer 16G DRAM65 nanometer 64G DRAM


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Die Bank

Assem- bly

Wafer Fab

Probe

Die

Bin Inventory

Finished Goods

Wafer Bank

Wafer Fab

Base Wafer Wafer Packaged

Device Bins Finished

Goods

Process and Product StructureFabrication Plant Back End Plant


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Wafer Fabrication ProcessesPhotolithography - transferring an image of a pattern

onto the surface of the wafer

– Apply layer of light-sensitive plastic called photoresist, capable of withstanding etching

– Using a pattern mask, expose the resist to UV light

– Develop the image, leaving portions of the substrate exposed and the remainder protected by a coating of resist


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Photolithography Equipment• Resist coating and developing “tracks”

• Optical equipment (“photo machines”):

– Contact aligners (features down to 3 microns in size)

– Projection aligners (1.2 micron)

– 1X Step-and-repeat (“Steppers”) (1 micron)

– 5X Steppers (G Line - 0.7 micron, I Line - 0.35 micron)

– Scanners (latest down to 0.02 micron, i.e., 20 nm)

• In most cases, coat/develop track and photo machine are linked as one machine


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Fabrication Processes (cont.)Etching - cutting trenches into the exposed areas

of SiO2 corresponding to the mask pattern

• Wet Etch - HF or Phosphoric Acid is used; isotropic, so not precise

• Dry Etch - Gas energized with electric discharge, with reactive ions and radicals present; plasma etching is anisotropic and permits more precise etching


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Fabrication Processes (cont.)Oxidation - grow SiO2 film on the wafers by exposing

them to oxygen in a furnace

– SiO2 is put down as insulation and as a protective coating between layers of circuitry

Diffusion – diffuse impurity into exposed silicon by blowing gas containing desired dopant over the wafers

– Common impurities include boron, phosphorous, nitrogen, polysilicon


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Diffusion equipment

Diffusion furnace - expose batch of wafers to a gas flow. Low cost, but limited accuracy.

Same kind of equipment is used for oxidation or for diffusing an impurity – a vertical furnace accommodating up to 150 wafers (6 lots). Process time ranges from 2 to 18 hours.


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Fabrication Processes (cont.)Ion Implant – Vaporize impurity atoms, disassociate

the ions in an electric discharge, accelerate a beam of ions in a strong electric field and focus ions on the wafer. High cost, but much better accuracy than diffusion furnaces.

Implant dopants “species” – Boron, BF2, Phosphorous, Arsenic, Antominy

Implant Equipment Types - High Current, Medium Current and High Energy Ion Implanters


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Fabrication Processes (cont.)Metalization - coating wafer surface with metal or metal

compounds by various methods:

– Evaporation - by means of filament contact or electron beam bombardment of metal source, metal vapor is released which settles on to wafers

– Sputtering - a heavy atom such as Argon is excited by electric discharge and collides with metal target, releasing metal shower on exposed wafers

– CVD - thermal decomposition of an organometallic compound onto the heated wafer


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Fabrication Processes (cont.)

• Chemical Mechanical Polish (CMP) - dielectric insulation deposited between metal layers is ground to precise thickness. (Only used in fabs making logic devices with feature sizes of 0.35 microns or smaller or memory devices with feature sizes of 0.25 microns or smaller.)


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Fabrication Processes (cont.)

Stripping or ashing - resist removal by wet or dry means, respectively

- one wafer at a time

Cleaning – wafers are rinsed in ultrapure, de-ionized water, followed by a spin-dry

- usually 50 wafers at a time

Sorting – re-shuffle wafers in a given lot into a different order


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Fabrication Equipment• Equipment for metalization, etching, cleaning and ashing

may consist of single-chamber tools, or several chambers may be collected into a “cluster tool” with a shared robot for load/unload

– One wafer at a time in each chamber

• Wet operations (etch and clean) are collected into “wet benches” which comprise a series of tanks served by a robot arm

– Batch of 50 wafers proceeds through the tanks


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Overall Fab Process• A process flow (or process technology) is the

complete series of wafer fabrication steps needed to fabricate a particular family of products.

– Various products produced in the same process flow typically have identical equipment settings (“recipes”) at each step

– The only difference between products in the same flow is the masks used at the lithography steps.


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Fab Process Flows (cont.)

• A fab may have as few as one or as many as 90 different process flows

– Products in different process flows experience different machine recipes

• A process flow may have as few as one or as many as 200 different products (wafer types)


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Fab Process Characteristics• Typically, wafers move from step to step in a cassette

holding 25 identical wafers called a lot• Great variety of load sizes for equipment:

– Dry Etch, Ash, Strip, CVD, Metalization, CMP, Sort, Inspect process one wafer at a time. Process times per wafer range 0.25 – 3 minutes.

– Implant processes 13 wafers at a time (depends on wafer size). Process times per run range 5 – 75 minutes.

– Wet cleaning and etching steps process up to 2 lots at a time through a series of tanks. Process times per run range 10 – 40 mins.

– Diffusion furnaces process up to 4 or 5 lots at a time. Process times pre run range 2 – 16 hours.

– Photolithography processes one chip at a time. (!) Process times per wafer range 2 – 10 minutes.

• Because of the many layers, lots re-visit the same equipment for performance of different steps requiring different process times (“re-entrant flow”).


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Typical Wafer Fab Construction Today

• Three Floors– Top floor - airflow equipment– Middle floor - fabrication equipment, operators– Bottom floor - utilities, water and chemicals

distribution• Middle floor supported independently to minimize

vibration

• Air flow from ceiling through floor to minimize turbulence (a large fab circulates 7M cu. ft. of air per minute)


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Typical Fab Layout• Equipment arranged into bays of like equipment

(“farm layout”)– Etch Bay

– Lithography Bay

– Implant Bay, etc.

• Automated material handling system such as monorail with lot carriers powered by linear-induction motors connects “stockers” serving each bay; in most fabs, operators hand-carry wafer lots from stocker to processing machine


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Typical Fab Operation• Wafers move from step to step in a lot of 25

identical wafers.

• Entire processing sequence in a process flow may include 500 individual steps to define 25-30 layers of circuitry; average lot may take 40-60 days to pass through the whole flow.

• Bar codes on the lots are used for automatic downloading of proper recipe into processing equipment.

• Computers collect substantial amounts of data about process, wafer and equipment.


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Scale of Operation• 50,000 wafer starts per month

• 50 steppers/scanners plus coat/develop tracks

• 10 high current ion implanters, 8 medium current implanters

• 40 dry etch machines, 30 CVD machines, 20 metallization machines, 50 diffusion furnace tubes, 50 wafer probe test CPU’s

• 200 operators and technicians, 200 engineers

• 24 hours per day, 365 days per year


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Traditional Fab Organization

• Manufacturing Operators and Supervisors

• Equipment Technicians

• Equipment Engineers

• Process Engineers

• Device Engineers & Integration Engineers

• Managers

• Other engineering and MIS support


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Die Sort Process

• Special electrical structures fabricated on the wafer are tested to verify proper electrical characteristics (“sample probe” or “parametric test” or “acceptance test”)

• Next, each chip on each wafer (each “die”) is given a full functional test, and bad die are inked (“wafer probe” or “electrical die sort”)


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Back End Process• Wafer dicing, die attach, wire bond, package

molding and sealing (the “assembly process”)

• Full functional test of the packaged device at various temperatures (“device test”), branding device ID, high-temperature operation (“burn-in”) followed by re-test, packing for shipment

• Lot sizes in the back end are 500 - 10,000 units

• Testing machines are basically computers with one or more test stations connected


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Manufacturing Challenges• Develop new process flows and ramp up

production volume as quickly as possible

• Insure stable process and product quality

• Invest in capacity wisely

• Determine causes of lost yield and lost equipment productivity, and eliminate losses as quickly as possible

• Reduce total elapsed time (“cycle time”)

• Improve on-time delivery

• Load factories to maximum possible revenue


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Manufacturing Yield• Line Yield is the fraction of wafers surviving the

fab process flow. Typical line yields: 70-98%

• Die Yield is the fraction of chips on a completed wafer that function at wafer probe. Typical die yields: 20-95%

• Causes of line yield loss: – Wafer mis-handling

– Wafer mis-processing

• Causes of die yield loss:– Process out of control (over-etch, under-deposit, etc.)

– Contamination (particles causing short or open in the circuit)


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Equipment Productivity• Availability is the fraction of time machine is

production-worthy (i.e., not under maintenance and not waiting for maintenance)

• Utilization is the fraction of time machine is engaged in production activity

• Overall equipment efficiency (OEE) is the “should-take” time for the work actually completed divided by the total time

• Typical OEE of fab equipment: 20 - 80%


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On-Time Delivery

• On-time delivery (“LIPAS”) is the fraction of products whose output quantity in the given time period is at least as much as was scheduled.

• Typical LIPAS for a fab (based on weekly schedules): 60 - 95%

• Typical LIPAS to external customers (based on daily schedules): 85 - 98%


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Cycle Time

• “Cycle time” is what the semiconductor industry calls flow time, i.e., the time it takes manufacturing lots to pass through the entire production process.

• Typical average cycle times for wafer fabs range from 3 days per mask layer down to (world-class) 1 day per mask layer.


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Why Cycle Time is Important

• Facilitates yield improvement

• Reduces working capital

• Increases revenue (because of rapid erosion of selling prices for technology goods, especially commodity chips and consumer goods)

In short, TIME IS MONEY


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Summary: The Grand Challenges

How do we:

• Maintain tight control of the manufacturing process to successfully fabricate the circuits

• Achieve high yield and high productivity

• Provide excellent on-time delivery

• Wisely invest in expensive process equipment

• Rapidly develop, deploy and ramp up new manufacturing technology and new products

• Compress the time to manufacture


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IE Job Opportunities• Integrated Device Manufacturers

– In Bay Area: Analog Devices, Maxim, Western Digital, Seagate, Headway Technologies, various Solar companies

– In Portland: Intel, Analog Devices, Microchip, Maxim– In Phoenix: Intel, Microchip, TSMC (next)– In Dallas: Texas Instruments– In Korea: Samsung, Hynix– In Singapore: Micron, ST Microelectronics, many others

• Foundries– In Albany, NY: Global Foundries– In Portland: Wafer Tech (TSMC)– In Orange County: Tower Jazz– In Dresden, Germany: Global Foundries– In Taiwan: TSMC, UMC, other foundries– In Singapore: Global Foundries, TSMC, others– In China: many


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IE Job Opportunities (cont.)

• Fabless companies– In Bay Area: Western Digital, NVIDIA, Cypress, others– In Southern California: Qualcomm, Broadcomm, others– Many other locations

• Equipment companies– In Bay Area: Applied Materials, Lam Research, KLA Tencor, Form

Factor, others

Documents

Methods for Manufacturing Improvement IEOR 130 Prof