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South Dakota School of Mines and Technology EE 647 Spring 2005 Page 1 of 20 EE 647 HDL Design Lab #2 VHDL-Based Design in Xilinx ISE 6.X and ModelSim Due Thursday 3/24/2005 Dr. Nian Zhang South Dakota School of Mines and Technology  ________________________ __ LAB #2 REQUIREMENTS 1. Turn in the truth table on page 14. (2 points) 2. Turn in the functional simulation waveform before Synthesis. (2 points) 3. Turn in the timing simulation waveform after Place & Route. (2 points) 4. Turn in the CLB slice on page 18. (2 points) 5. Report the dif ference between the functional simulation waveform (i.e. before Synthesis) and the timing simulation waveform (i.e. after Place & Route). Explain it. (2 points)  _____________________________________________________________________ This tutorial is intended to provide you with an introduction to the tools that you will  be using throughout this semester. While this tutorial attempts to expose you to the most common buttons, icons, menu options, etc. in the software, it will not demonstrate all of the features. Once completing the tutorial you are encouraged to explore more capabilities of the tools. The more familiar you are with your design environment, the more productive you will be. Before we begin looking at VHDL and its FPGA implementation in the lab, we will introduce the design flow for VHDL entry. BACKGROUND - VHDL DESIGN FLOW STEP 1 – Design Entry The first step in the design process is to input your design into a machine-readable format. To do this you will use a Computer Aided Design tool. In this course, we will use Xilinx ISE software. A typical CAD tool supports many design entry methods, such as a schematic capture, HDL entry (VHDL/Verilog) or a component net list. In this course, all digital designs are captured using VHDL. STEP 2 – Functional Simulation Once a design has been captured in the CAD tools, the next step is to simulate the 1

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