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In the name of God Digital Logic – Shahid Beheshti University – Spring 2012

ModelSim 6.5 brief tutorial

Here are some short tips for you to get used to Verilog Language and ModelSim 6.5 environment. After Installing ModelSim go to crk folder and run MentorKG then If it’s your first time opening ModelSim or if you encounter problems with licenses, you can run the license wizard: Start > All Programs > ModelSim SE > Licensing Wizard. Choose install a new license and select the file LICENSE.TXT in crk Folder, you must see a congratulation message that you cracked successfully!

It’s time to see different parts of ModelSim, we’ll go through it step by step with an example of designing a full adder module, I’ll explain important parts to you when we reach them.

First you’ll see something like the picture below. start by choosing new Project and name it fullAdder:

Environment ModelSim 6.5 Language Verilog

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Ok, now choose new file, name it whatever you like, consider to choose Verilog, the default language is VHDL, now you’ll see your file and the status is “?”, it means it didn’t compile yet.

First things first, let’s sharpen our tools by choosing right component in ModelSim, so go to view tab and make sure the Library, Objects, Project, Transcript and Wave are selected.

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Library: A directory that contains compiled design units, such as modules.

Projects: A collection of various files for designs under test, such as Verilog source files, local working libraries, references to resource libraries, and simulation configuration (*.mpf files).

Objects: is where you can find your variables, input outputs, etc.

Wave: Here you can see the inputs/outputs of your module in waveform.

Transcript: this tool will allow you to execute your commands by typing. (Something like command prompt in windows)

E.g. instead of clicking a file to compile you can type

vlog –work [working library] [filename.v]

Example: vlog –work work fullAdder.

That’s enough for now, let’s start coding :D

Here you can see a full adder:

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Go to Project component and double click the Verilog file to change it

We want to create a fullAdder Module.

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I wrote code and named it “my fullAdder.v” and I explained different parts by comments. If you want to use my code instead of creating new file you can choose add existing file and choose my file, you must then compile that, but I strongly suggest you for first time write it on your own to get familiar with Verilog.

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Ok, go to project and compile the file, if your code doesn’t have compile error you’ll see a check mark in status.

Note: After each change in your code you must save it and then recompile it, it won’t save automatically (use ctrl+s shortcut key)

Consider that when you compile a module correctly it will be added to your Work library with Module name you defined in your code. Here is: fullAdder

Well then, time to simulate.

In simulate tab click start simulation:

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In work library find fullAdder Module

Here uncheck the “Enable Optimization”, otherwise sometimes signals won’t appear in Objects list.

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Click Ok, now in Objects Component you must see all of your inputs and outputs to and from module

We want to see the waveform of these signals so by right clicking and selecting

Add->To wave->Signal in Regions

You’ll add all signals (if you want to select some signals you can choose your signals and then choose selected signals, for example sometimes you’re just interested in outputs)

Now they are added in waveform.

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HiZ means high impedance, because we didn’t set any input yet. X in output means it doesn’t have any value yet

Next step we should set the inputs,

Force values:

Force follows this type: Force [variable] [value] [time] Value: is the constant you want to set. Time: shows after how much time change will occur. So here we can do something like this: force a 1 force b 0 force b 1 100 ns force Cin 1 Now it’s time to run, so from time 0 to time 100 the outputs should be: S = 0, Cout = 1

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From time 100 to 500 the outputs should be: S = 1, Cout = 1 (Times are in Nano second scale by using ns suffix) To run simply type: Run 500 ns

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NOTE: when you type run, it’ll not start from time 0, it’ll start from current time, so after previous run if I type run 120 wave form will show you from time 500 to 620. In general after run when you type anything it’ll affect the changes after that time For example here if we write: force a 0 50 ns force b 0 run 120 We’ll see:

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Note: if you want to restart all waves and back to time zero, simply type: restart –f

References: Stephen Brown’s Digital Logic Design http://en.wikipedia.org/wiki/Adder_(electronics) http://web.mit.edu/6.111/www/index.html

Instructor: Dr.M.Abbaspour TAs: Ashkan Entezari, Maryam Sekhavat, Aryan Yaghoubian https://sites.google.com/site/sbudigitallogic/