VHDL & ModelSim VHDL & ModelSim

CPU ArchitectureCPU Architecture

Serge KarabchevskySerge Karabchevsky

ObjectivesObjectives

Course Website, Software and HardwareCourse Website, Software and Hardware

Logic TimingLogic Timing

Introduction to VHDLIntroduction to VHDL

ModelSim SimulationModelSim Simulation

First Assignment DefinitionsFirst Assignment Definitions

Course WebsiteCourse Websitehttp://hl2.bgu.ac.ilhttp://hl2.bgu.ac.il AnnouncementsAnnouncements AssignmentsAssignments LecturesLectures Forums Forums

Anyone can askAnyone can askAnyone can answer (if he knows the answer)Anyone can answer (if he knows the answer)Check Google before asking at forum.Check Google before asking at forum.

Reception hoursReception hours At the forumsAt the forums Monday 16Monday 160000-17-1700 00 -- Scheduling by emailScheduling by email Email : Email : serge@ee.bgu.ac.ilserge@ee.bgu.ac.il

Course SoftwareCourse Software

Modelsim (Simulator)Modelsim (Simulator) http://model.com/content/modelsim-pe-http://model.com/content/modelsim-pe-

student-edition-hdl-simulationstudent-edition-hdl-simulation

Quartus (FPGA Compiler)Quartus (FPGA Compiler) http://www.altera.com/products/software/http://www.altera.com/products/software/

quartus-ii/web-edition/qts-we-index.htmlquartus-ii/web-edition/qts-we-index.html

MARS (MIPS compiler)MARS (MIPS compiler) http://courses.missouristate.edu/http://courses.missouristate.edu/

KenVollmar/MARS/KenVollmar/MARS/

Course Hardware Course Hardware Altera DE1 FPGA BoardAltera DE1 FPGA Board

Cyclone II EP2C20F484C6 FPGACyclone II EP2C20F484C6 FPGA

50MHz,27MHz and 24MHz oscillators50MHz,27MHz and 24MHz oscillators

4 pushbutton switches 4 pushbutton switches

10 toggle switches 10 toggle switches

10 red LEDS10 red LEDS

8 Green LEDs 8 Green LEDs

Logic TimingLogic Timing

Tpd : Time from state change at input to state Tpd : Time from state change at input to state change at outputchange at output

In

Out

t

t

pdt

DFF TimingDFF TimingTco : Time from clock rise to output state changeTco : Time from clock rise to output state change

Tsu : Time that input must be stable before clock riseTsu : Time that input must be stable before clock rise

Th : Time that input must be stable after clock riseTh : Time that input must be stable after clock rise

Clk

In

Out

t

t

t

setupt holdt

cot

Q

QSET

CLR

D

Calculating FrequencyCalculating Frequency

Long Path Rule (Setup):Long Path Rule (Setup):

1/F1/FMaxMax = Tco = Tco11+Tpd+TpdMaxMax+Tsu+Tsu22+t+tskewskew

Short Path Rule (Hold):Short Path Rule (Hold):

TcoTco11+Tpd+TpdMinMin > Th > Th22+t+tskewskew

FF(Tco1,Tsu1,Th1)

Logic(Tpd)

FF(Tco2,Tsu2,Th2)

CLKtskew

Introduction to VHDLIntroduction to VHDLVVery high speed integrated circuits ery high speed integrated circuits HHardwareardware

DDescription escription LLanguageanguageEntitiesEntitiesArchitecturesArchitectures StructuralStructural Dataflow Dataflow Behavioral (Process , examples)Behavioral (Process , examples)

Test BenchTest BenchGeneric VariablesGeneric VariablesGenerate LoopsGenerate LoopsPackages and Simulating DelaysPackages and Simulating Delays

VHDL DesignVHDL Design

Design must have a top level entity with :Design must have a top level entity with : At least one input (test-bench is an exception)At least one input (test-bench is an exception) At least one output (test-bench is an exception)At least one output (test-bench is an exception) Optional Parameter (generic variable)Optional Parameter (generic variable)

Each entity is located in separate fileEach entity is located in separate file

File is with .VHD extensionFile is with .VHD extension

VHD File StructureVHD File Structure-- Library Definition-- Library Definitionlibrary ieee;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_1164.all;use IEEE.std_logic_unsigned.all; use IEEE.std_logic_unsigned.all; -- Entity Definition-- Entity Definition entity counter is port (clk : in std_logic; q : buffer unsigned (7 downto 0)); entity counter is port (clk : in std_logic; q : buffer unsigned (7 downto 0)); end entity;end entity;-- Architecture Definition-- Architecture Definitionarchitecture rtl of counter isarchitecture rtl of counter is-- Component and signal declaration-- Component and signal declarationBeginBegin-- Design Body-- Design Body

process (clk) beginprocess (clk) beginif (rising_edge(clk)) thenif (rising_edge(clk)) then

q <= q + 1;q <= q + 1;end if;end if;

end process;end process;end rtl;end rtl;

An EntityAn Entity

c

a(0)

a(1)

a(2)

a(3)

entity entity entity_nameentity_name is isgeneric ( generic ( generic_declarationsgeneric_declarations ) ; ) ; port ( port ( port_declarationsport_declarations ) ; ) ;

end end entity_nameentity_name ; ;

In the Entity we define our design like a black-box In the Entity we define our design like a black-box with only inputs and outputs.with only inputs and outputs.

entity entity nand2nand2 is isport ( port ( a,b : in std_logic; c : out std_logica,b : in std_logic; c : out std_logic ) ; ) ;

end end nand2nand2 ; ;

entity entity xorxor is isgeneric ( generic ( N : integer := 4N : integer := 4 ) ; ) ; port ( port ( a : in std_logic_vector(N-1 downto 0); a : in std_logic_vector(N-1 downto 0);

b : out std_logicb : out std_logic ) ; ) ; end end xorxor ; ;

bc

a

ArchitectureArchitecture

architecture architecture architecture_namearchitecture_name of of entity_nameentity_name is is[ component declaration ][ component declaration ][ signal declaration ][ signal declaration ]

beginbegin[ design logic ][ design logic ]

end end architecture_namearchitecture_name ;;

The types of architecture are :The types of architecture are :•StructuralStructural•Dataflow Dataflow •BehavioralBehavioral

In the Architecture we define the logic of our Entity (contents) In the Architecture we define the logic of our Entity (contents) and it’s connection to inputs and outputsand it’s connection to inputs and outputs

architecture architecture rtlrtl of of nand2nand2 is isbeginbegin

c <= a NAND b;c <= a NAND b;end end rtlrtl ;;

bc

a

Entity and ArchitectureEntity and Architecture

EntityInputs OutputsInputs Outputs

Component Component

Signal

ProcessSignal

Data Flow

ArchitectureArchitecture

Structural ArchitectureStructural ArchitectureUsing existing components (entities) in order to Using existing components (entities) in order to build a new one, like connecting chips each to build a new one, like connecting chips each to otherother

All the components must be declared before the All the components must be declared before the architecture beginarchitecture begin

Then the components are instantiated and Then the components are instantiated and connected each to other using signalsconnected each to other using signals

Structural AND Gate from NAND Structural AND Gate from NAND and NOTand NOT

entity entity and2and2 is isport ( port ( a,b : in std_logic; c : out std_logica,b : in std_logic; c : out std_logic ) ; ) ;

end end and2and2 ; ;architecture architecture structstruct of of and2and2 is is

component component nand2nand2 is port ( is port ( a,b : in std_logic; c : out std_logica,b : in std_logic; c : out std_logic ) ; ) ; end component ;end component ;component component not_gatenot_gate is port ( is port ( a : in std_logic; b : out std_logica : in std_logic; b : out std_logic ) ; ) ; end component ;end component ;signal signal nand_out : std_logic;nand_out : std_logic;

beginbeginU1 : nand2 U1 : nand2 port map (a=> a ,b=>b, c=> nand_out);port map (a=> a ,b=>b, c=> nand_out);U2 : not_gate U2 : not_gate port map (a=> nand_out ,b=>c);port map (a=> nand_out ,b=>c);

end end structstruct ;;

b

ca

Data Flow ArchitectureData Flow Architecture

Circuits are described by indicating how the Circuits are described by indicating how the inputs and outputs of builtinputs and outputs of built--in primitive in primitive components components ((exex.. andand gate) are connected. gate) are connected.

In other words we describe how signals flow In other words we describe how signals flow through the circuit. through the circuit.

entity entity latchlatch is is port (port (s,r : in std_logic; q,nq : out std_logics,r : in std_logic; q,nq : out std_logic););end end latchlatch;;architecture architecture dataflowdataflow of of latchlatch is isbegin begin

qq <=r nor nq; <=r nor nq; nqnq <=s nor q;<=s nor q;

end end dataflowdataflow; ;

r

s

q

nq

Behavioral ArchitectureBehavioral ArchitectureDescribes the behavior of components in Describes the behavior of components in response to signals.response to signals.Behavioral descriptions of hardware utilize Behavioral descriptions of hardware utilize software engineering practices to achieve software engineering practices to achieve a functional model. a functional model. Timing information may be included for Timing information may be included for simulations.simulations.Requires PROCESS statementRequires PROCESS statement

What can be behavioralWhat can be behavioral

Combinational LogicCombinational Logic Simple combinational logicSimple combinational logic LatchesLatches

Sequential logicSequential logic Flip FlopFlip Flop Mix of Combinational logic with Flip-FlopsMix of Combinational logic with Flip-Flops Flip Flops with asynchronous Reset/PresetFlip Flops with asynchronous Reset/Preset

Test BenchTest Bench

It is Not a It is Not a SoftwareSoftware

Behavioral description describes a Behavioral description describes a LogicLogic , , not a software. Be careful of what you are not a software. Be careful of what you are writing.writing.

Timing commands can be used only in test Timing commands can be used only in test bench or for delays definition in simulation.bench or for delays definition in simulation.

Do not use timing commands to create logicDo not use timing commands to create logic

The design should work normally if you The design should work normally if you remove the timing commandsremove the timing commands

ProcessProcess

Used for all behavioral descriptionsUsed for all behavioral descriptions

Statements within a process are executed Statements within a process are executed sequentially sequentially

All processes in a VHDL description are All processes in a VHDL description are executed concurrently executed concurrently

Will be executed (in simulator) in case of Will be executed (in simulator) in case of state change of at least one signal in state change of at least one signal in sensitivity listsensitivity list PROCESS (PROCESS (sensitivity listsensitivity list))

declarationsdeclarationsBEGINBEGIN Process body (behavioral description)Process body (behavioral description)END PROCESS;END PROCESS;

SignalsSignals

Signals are local for specific architecture , they are Signals are local for specific architecture , they are used for interconnect between different processes used for interconnect between different processes and components and components

When assigning a signal in a process it will When assigning a signal in a process it will change only after process completion change only after process completion

Only the last assignment counts (including Only the last assignment counts (including assignments under IF or CASE)assignments under IF or CASE)

If there is no active assignment , signal holds it’s If there is no active assignment , signal holds it’s previous state (previous state (LatchLatch))

Assignment is done by ‘<=‘Assignment is done by ‘<=‘

SIGNAL a, b : std_logic;

VariablesVariables

Local to the process they are definedLocal to the process they are defined

A variable behaves like you would expect in A variable behaves like you would expect in a software programming languagea software programming language

Assignment takes time immediatelyAssignment takes time immediately

Assignment is done by ‘:=‘Assignment is done by ‘:=‘

VARIABLE tmp : integer range 0 TO 15;

Combinational DescriptionCombinational Description

All the process input signals must be in the All the process input signals must be in the sensitivity listsensitivity list

Signal must have an active assignment in Signal must have an active assignment in all the paths (if , case …). Otherwise latch all the paths (if , case …). Otherwise latch will be createdwill be created

A default assignment can be used at the A default assignment can be used at the beginning of the process to avoid latchesbeginning of the process to avoid latches

Combinational Description ExampleCombinational Description Example

A[1..0]

B[1..0]OUT

EQUAL

A[1..0]

B[1..0]OUT

EQUALSEL

DATAA

DATABOUT0

MUX21

SELDATAA

DATABOUT0

MUX21

I2[2..0]I1[2..0]I0[2..0]

S[1..0]

O[2..0]

O~[5..3]O~[2..0]

Equal1

2' h1 --

Equal0

2' h0 --

Common ErrorCommon Error

A[1..0]

B[1..0]OUT

EQUAL

A[1..0]

B[1..0]OUT

EQUAL

A[1..0]

B[1..0]OUT

EQUAL

D

ENA

PRE

CLR

Q

0

1

0

1

D

ENA

PRE

CLR

Q

0

10

1

D

ENA

PRE

CLR

Q

0

10

1

Equal0

2' h0 --

Equal1

2' h1 --

Equal2

2' h2 --

O[0]$latch

O[0]~1

O[1]$latch

O[1]~2O[1]~3

O[2]$latch

O[2]~4O[2]~6

O[2]~7

I2[2..0]I1[2..0]

I0[2..0]

S[1..0]

O[2..0]

O[0]~0

Sequential DescriptionSequential Description

D

ENA

QPRE

CLR

q~reg0q~0d1d2

clock

q

rising_edge statement must present in the rising_edge statement must present in the process bodyprocess body

Asynchronous reset pathsAsynchronous reset paths

Only one synchronous pathOnly one synchronous path

Only one Asynchronous pathOnly one Asynchronous path

A[7..0]

B[7..0]OUT[7..0]

ADDER

D QPRE

ENA

CLR

clockclear

Q[7..0]

Q[7..0]~reg0

Add0

8' h01 --

Test BenchTest BenchUsed to test the design functionalityUsed to test the design functionality

Not translated to real hardwareNot translated to real hardware

Wraps around the designWraps around the design

You can write everything you want (like Software)You can write everything you want (like Software)

Design Top Level

Test Bench

How Test Bench WorksHow Test Bench Works

DUTDUTInput Input

generationgenerationOutput Output

observationobservation=?=?Error Error ReportReport

Golden Golden OutputOutput

Golden ModelGolden Model

Error Reporting :Error Reporting :process(clk) beginprocess(clk) begin

if (clk'event and clk='1') thenif (clk'event and clk='1') thenASSERT out_dut = out_goldenASSERT out_dut = out_goldenREPORT “Test Failed"REPORT “Test Failed"SEVERITY error;SEVERITY error;

end if;end if;end process; end process;

Generic variablesGeneric variables

Instantiation :Instantiation :

U1: nand2 generic map (U1: nand2 generic map (tpdtpd => => 1ns1ns))port map (a => a_signal, b=>b_signal , c=>c_signal);port map (a => a_signal, b=>b_signal , c=>c_signal);

entity entity nand2nand2 is isgeneric (tpd: time);generic (tpd: time);port ( port ( a,b : in std_logic; c : out std_logica,b : in std_logic; c : out std_logic ) ; ) ;

end end nand2nand2 ; ;

architecture architecture rtlrtl of of nand2nand2 is isbeginbegin

c <= a NAND b after c <= a NAND b after tpdtpd;;end end rtlrtl ;;

Compilation Driven ParametersCompilation Driven Parameters

Can’t change at run timeCan’t change at run time

Generate loopsGenerate loops

D

Q

Q

R

Data

Clk

Reset

Data

D

Q

Q

R

Data

Clk

Reset

5 5

entity entity registerregister is port is port((reset, clkreset, clk: : in std_logicin std_logic;;dd: : inin std_logic_vectorstd_logic_vector((4 4 downtodownto 0 0));;qq: : out std_logic_vectorout std_logic_vector((4 4 downtodownto 0 0))));;

end end registerregister;;

architecture architecture structstruct of of registerregister is iscomponent dff portcomponent dff port((

reset, clk, d reset, clk, d : : in std_logic; q, q_not in std_logic; q, q_not : : out std_logicout std_logic));;end componentend component;;beginbegin

Array_Of_DFFsArray_Of_DFFs: : forfor i in i in D'rangeD'range generategeneratedffidffi: : dff port mapdff port map((reset reset ==> reset, clk > reset, clk ==> clk, d > clk, d ==> d> d((ii)),q ,q ==> q> q((ii))));;

end generate;end generate;end end structstruct;;

D

Q

Q

R

D

Q

Q

R

D

Q

Q

R

D

Q

Q

R

clk

D3

D2

D1

D0 D

Q

Q

R

Q4

Q3

Q2

Q1

Q0

reset

D4

PackagesPackages

Saves time on component declaration , no Saves time on component declaration , no need for code duplication.need for code duplication.

library IEEE;library IEEE;use IEEEuse IEEE..STD_LOGIC_1164STD_LOGIC_1164..ALL;ALL;PACKAGE sample_package isPACKAGE sample_package is

component nand2 portcomponent nand2 port((a,b a,b : : in std_logic; c in std_logic; c : : out std_logicout std_logic));; end component ;end component ; component not_gate portcomponent not_gate port((a a : : in std_logic; b in std_logic; b : : out std_logicout std_logic));;end component ;end component ;

end sample_package;end sample_package;

In design files add : In design files add : use WORKuse WORK. . sample_packagesample_package..ALL;ALL;

sample_packagesample_package..vhdvhd

Simulating DelaysSimulating Delays

In The Test bench :

a <= ‘1’, ‘0’ after 2 ns, ‘1’ after 7 ns;b <= ‘1’, ‘0’ after 4 ns, ‘1’ after 6 ns;

c

1 3 6 8t[ns[

t[ns[

t[ns[

0

a

b

2 4 5 7 9

All the times are relative to zero All the times are relative to zero

(Start of line execution)(Start of line execution)

architecture architecture rtlrtl of of and2and2 is isbeginbegin

c <= a c <= a andand b b afterafter 1ns; 1ns;end end rtlrtl ;;

Creating component delayCreating component delay for simulation for simulation

ModelSim SimulatorModelSim Simulator

Learn By ExampleLearn By Example

First ExampleFirst ExampleN Bit RegisterN Bit Register

Uses PackageUses Package

Download it from HL and simulateDownload it from HL and simulate

Are there any logic delays?Are there any logic delays?

D Q

Clk

Reset

NN

How to use ModelSim?How to use ModelSim?Create Project with “work” library Create Project with “work” library (“File->New->Project”)(“File->New->Project”)

Add files to project Add files to project (“Project->Add to Project”)(“Project->Add to Project”)

Edit .vhd filesEdit .vhd filesSet compilation orderSet compilation order (“Compile->Compile order”)(“Compile->Compile order”)

CompileCompile all the .vhd files all the .vhd files (“Compile->Compile All”)(“Compile->Compile All”)

LoadLoad the the “test bench” “test bench” configurationconfiguration file. file. (double-click on the configuration link of the complied test bench in “work” (double-click on the configuration link of the complied test bench in “work” library)library)

Add a new wave window Add a new wave window (“View->New Window->Wave”)(“View->New Window->Wave”)

How to use ModelSim? (cont’)How to use ModelSim? (cont’)Copy the relevant signals to the wave windowCopy the relevant signals to the wave windowRun simulation Run simulation (Simulate->Run->Run)(Simulate->Run->Run)

Work the right way… so u won’t loose grade:Work the right way… so u won’t loose grade: Change signal names to friendly ones Change signal names to friendly ones (Display Names)(Display Names)

Use “Dividers” between signalsUse “Dividers” between signals Mark time periodsMark time periods Zoom on the right signalsZoom on the right signals Use Hexadecimal notations when necessaryUse Hexadecimal notations when necessary Save the wave format to use it later Save the wave format to use it later (“File->Save(“File->Save))

Second ExampleSecond Example

Delay LineDelay Line

Download it from HL and run on your own.Download it from HL and run on your own.

Are there any logic delays?Are there any logic delays?

D Q

Clk

Reset

NN

D Q

Clk

Reset

N

D Q

Clk

Reset

NNInput Output

Clk

Make Changes on the Make Changes on the Second ExampleSecond Example

Change clock period to 20nChange clock period to 20n

Change delay line depth to 4Change delay line depth to 4

Run the simulation againRun the simulation again

Good luck!Good luck!

Any questions?