24
1 I/O and Interrupts I/O and Interrupts Today: First Hour: I/O Concepts Section 6.1-6.6 of Huang’s Textbook In-class Activity #1 Second Hour: Interrupt Code Example In-class Activity #2

I/O and Interrupts

  • Upload
    aram

  • View
    31

  • Download
    0

Embed Size (px)

DESCRIPTION

I/O and Interrupts. Today: First Hour : I/O Concepts Section 6.1-6.6 of Huang’s Textbook In-class Activity #1 Second Hour : Interrupt Code Example In-class Activity #2. Goal: Example Task. - PowerPoint PPT Presentation

Citation preview

Page 1: I/O and Interrupts

1

I/O and InterruptsI/O and Interrupts

Today:• First Hour: I/O Concepts

–Section 6.1-6.6 of Huang’s Textbook

– In-class Activity #1

• Second Hour: Interrupt Code Example

– In-class Activity #2

Page 2: I/O and Interrupts

2

Goal: Example TaskGoal: Example TaskRead the output of the 4-bit data source every time the push

button is pressed, and display the result.Read the output of the 4-bit data source every time the push

button is pressed, and display the result.

4-bit Data

Source

Push Button

Computer(HC11 chip)

Display

Page 3: I/O and Interrupts

3

ROM-8KB

RAM-256 bytes

EEPROM-512 bytes

PORTA

PULSE ACCUMULATOR

PERIODIC INTERRUPT

COP WATCHDOG

PAIOC2

OC3OC4OC5

OC1

IC1

IC2IC3

PA7

PA6PA5PA4PA3PA2PA1

PA0

PE7

PE6PE5PE4

PE3

PE2

PE1PE0

PORTE

VREFH

VREFL

A/DCONVERTER

DA

TA

DIR

EC

TIO

N

PORTD

SSSCK

MOSI

MISO

SPI

TxD

RxDSCI

PD5

PD4PD3

PD2

PD1

PD0

M68HC11 CPU

ADDRESS DATA BUS

INTERRUPTS

RESET

XIRQ

IRQ(V

PPBULK) HANDSHAKE I/O

DATA DIRECTION C

PORT CPORT B

PARALLELI/O

SINGLECHIP

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

STRA

STRB

A15

A14

A13

A12

A11

A10

A9

A8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

R/W ASEXPAND

OSCILLATOR

XTAL

EXTAL

E

MODALIR

MODB(VSTBY )

VDD

VSS

MODESELECT

POWER

M6811 PortsM6811 Ports

Page 4: I/O and Interrupts

4

PortsPorts• Way to read/write from/to peripheral devices• Some ports allow both input and output (see your PRG!)• Each port has:

–Control Registers–Status Registers–Data Registers–Data Direction Registers

• The ports are memory mapped, which means that you can access these registers via memory!– I/O becomes a simple matter of reading/writing to

these special memory locations!

Page 5: I/O and Interrupts

5

Look up PRG! - The 68HC11A8 has 40 I/O pins that are arranged in five I/O ports.- All I/O pins serve multiple functions.- Ports C and D are bi-directional I/O pins under the control of their associated data direction registers. - Port C, port B, the STRA pin, and the STRB pin are used for strobed and handshake parallel I/O, as well as for general-purpose I/O.

Port Registers- To input, the 68HC11 reads from the port data register- To output, the 68HC11 writes into the port data register- All except port C have one data register:

PORTA (at $1000)PORTB (at $1004)PORTC (at $1003)PORTCL (at $1005)PORTD (at $1008)PORTE (at $100A)

6811 Parallel I/O Using Ports6811 Parallel I/O Using Ports

Page 6: I/O and Interrupts

6

-Each pin of ports C and D has an associated bit in a specific data register and another in a data direction register.

-The primary direction of a pin is set by its associated bit in the data direction register.- When an output pin is read, the value at the input to the pin driver is returned.

-The data direction registers are cleared by reset to configure all bi-directional I/O pins for input.

- Before performing I/O operation to these two ports, the software should set up the data direction registers of these two ports.

Data & Direction RegistersData & Direction Registers

Page 7: I/O and Interrupts

7

Display

4-bit Data

SourceP

O

R

T

C

0

3

4

7

0

0

0

0

1

1

1

1

DDRC

Data & Direction RegistersData & Direction Registers

Page 8: I/O and Interrupts

8

Which PORTCpins areInput:Output:?

Which PORTCpins areInput:Output:?

Eg: Setting I/O Pin DirectionsEg: Setting I/O Pin DirectionsPORTC Example Program FragmentPORTC Example Program Fragment

PORTC EQU $1003

DDRC EQU $1007

IO_PAT EQU %11110000

NUMBER EQU %10010011

...

LDAA #IO_PAT

STAA DDRC

LDAA #NUMBER

STAA PORTC

LDAA PORTC

[3:0][7:4]

What bit patternis output:?

What bit patternis output:?

%1001

Page 9: I/O and Interrupts

9

REGBAS EQU $1000PORTD EQU $08DDRD EQU $09

LDX #REGBASLDAA #$3F ; directions of port D pinsSTAA DDRD,X

LDAA #$CD ; output $CD to port DSTAA PORTD,X

Eg: Output to Port DEg: Output to Port D

Page 10: I/O and Interrupts

10

- All strobed mode I/O and handshake I/O are controlled by this PIOC register

Parallel I/O Control RegisterParallel I/O Control Register

7 6 5 4 3 2 1 0

STAF STAI CWOM HNDS OIN PLS EGA INVB

value after

reset0 0 0 0 0 U 1 1

STAF: Strobe A flag . This bit is set when a selected edge occurs on theSTRA signal.

STAI: Strobe A interrupt enable . When the STAF and STAI bits areboth equal to 1, a hardware interrupt request will be made to the

CPU.

EGA: Active edge for STRA0: falling edge1: rising edge

INVB: Invert STRB0: STRB active low1: STRB active high

PIOC

at $1002

. . .

Page 11: I/O and Interrupts

11

- Strobe is an external signal which can be used to trigger the I/O from the port.- Eg: Push botton !

Strobe Setup: -Strobe mode I/O selected when the bit 4 (HNDS) of the PIOC register is set to 0 and port C becomes a strobe input port.

-The bit 1 (EGA) of the PIOC register when set to 1 selects the active edge of the STRA pin.- The active edge of the STRA signal latches the values of the port C pins into the PORTCL register.

Strobe Input Port CStrobe Input Port C

Page 12: I/O and Interrupts

12

Strobe I/O Port C (Contd)Strobe I/O Port C (Contd)- Reading the PORTC register returns the current values

on the port C pins.- Reading the PORTCL register returns the contents of

the latched PORTCL.

- When enabled using bit 6 (STAI) of the PIOC, the active edge of the STRA signal will generate an interrupt to the 68HC11.

- This interrupt shares the same vector as IRQ.- This can be used to force an interrupt-driven I/O !

Page 13: I/O and Interrupts

13

Do Activity #1 NowDo Activity #1 NowReference code

REGBAS EQU $1000PORTD EQU $08DDRD EQU $09

LDX #REGBASLDAA #$3F ; directions of port D pinsSTAA DDRD,X

LDAA #$CD ; output $CD to port DSTAA PORTD,X

Page 14: I/O and Interrupts

14

Goal: Example TaskGoal: Example TaskRead the output of the 4-bit data source every time the push

button is pressed, and display the result.Read the output of the 4-bit data source every time the push

button is pressed, and display the result.

4-bit Data

Source

Push Button

Computer(HC11 chip)

Display

Page 15: I/O and Interrupts

15

Recap: Polling MethodRecap: Polling Method4-bit Data

Source

Push Button

Computer(HC11 chip)

Display

START

BUTTON PRESSED?

1 ms delay

BUTTON PRESSED?

READ 4-BIT INPUTUPDATE DISPLAY

NO

NO

YES

YES

This style of computerinput/output is called

Polled I/OPolled I/Obecause we’re constantly

polling the pushbutton

This style of computerinput/output is called

Polled I/OPolled I/Obecause we’re constantly

polling the pushbutton

Page 16: I/O and Interrupts

16

Recap: Interrupt MethodRecap: Interrupt Method

STARTINTERRUPT SERVICE

ROUTINE

READ THE 4-BIT INPUTUPDATE THE DISPLAY

RETURNFROM

INTERRUPT

START

INITIALIZE

DO SOMETHING

USEFUL

KeyPressed

The CPU is temporarily interrupted. An Interrupt Service Routine is entered

The CPU is temporarily interrupted. An Interrupt Service Routine is entered

The CPU now resumes where it left off!The CPU now resumes where it left off!

STARTINTERRUPT SERVICE

ROUTINE

READ THE 4-BIT INPUTUPDATE THE DISPLAY

RETURNFROM

INTERRUPT

DO SOMETHING

USEFUL

Page 17: I/O and Interrupts

17

Interrupt DetailsInterrupt Details

RETURNFROM

INTERRUPT (RTI)

START

Initialize StackSetup Interrupt Vectors

Clear previous interrupts & initialize device keeping

interrupts disabled

MAIN LOOP

STARTINTERRUPT SERVICE

ROUTINE

Further identify source if neededService interrupt

Clear interrupt request flag*

Enable interrupts locally at deviceEnable interrupts globally

Identify source(s)Resolve priorityPush registers

Disable further interruptsCall interrupt service routine

Restore registersEnable Interrupts

InterruptRequest

Done by hardware

Page 18: I/O and Interrupts

18

Task: Hardware SetupTask: Hardware Setup• The low nibble of PORTC is connected to a 7-segment

display (output)

• The hi nibble of PORTC is connected to a 4-bit thumbwheel switch (input)

• The STRA line is connected to a high-asserting pushbutton

• Problem :

– Copy thumbwheel setting to display whenever pushbutton is pressed.

– This program should run on the EVB

– Also illustrates the general form of programs using interrupts.

Page 19: I/O and Interrupts

19

Code: initializationCode: initialization*Equates: define symbolic names for registers and constantsPIOC EQU $1002PORTC EQU $1003DDRC EQU $1007PORTCL EQU $1005VECLOC EQU $00EE ; see EVB manual sec 3.3 the STRA line generates an IRQ interruptJMPOP EQU $7E ; opcode for extended jmpIOPAT EQU $0F ; for data direction regCTRPAT1 EQU %00000011 ; for PIOC reg, STAI disabledCTRPAT2 EQU %01000011 ; for PIOC reg, STAI enabled

* Data Section - setup stack space and initial Stack Pointer ORG $D000STACK RMB $7FFINITSP EQU *-1

Page 20: I/O and Interrupts

20

Code: Init Port CCode: Init Port C* Setup and Initialization Program

ORG $C000

* initialize stack pointer

SETUPINT LDS #INITSP

* initialize PORT C and associated control registers

LDAA #CTRPAT1 ; STAI (temporarily) disabled

STAA PIOC

LDAA #IOPAT ; $0F => lower nibble output

; higher nibble input

STAA DDRC

CLR PORTC ; Clear Port C

Page 21: I/O and Interrupts

21

Code: Setup Software IVTCode: Setup Software IVT*setup interrupt vector in Buffalo jump table.

*See section 3.3 of EVB manual for details.

LDAA #JMPOP ; Load the Opcode for JMP

; at this vector location

STAA VECLOC

LDX #ISRIRQ ; Load the 16-bit RAM Address ; for the IRQ ISR (which is ; shared by STRA) in the next ; 2 bytes.

STX VECLOC+1 ; Total:3 bytes per IVT location

Page 22: I/O and Interrupts

22

Code: Enable Interrupts; MainCode: Enable Interrupts; Main*clear status of peripheral or subsystem that could cause*an immediate interrupt. See 6811 Reference manual Section 5.7,* Also see the textbook. LDAA PIOC LDAA PORTCL* Enable Interrupt in peripheral or subsystem LDAA #CTRPAT2 ; STAI enabled

STAA PIOC* Enable Interrupts globally CLI ; Clears I-bit in CCR. 0 => enable* Jump to main program JMP MAIN******************************************************* MAIN PROGRAM: trivial******************************************************

MAIN BRA MAIN

Page 23: I/O and Interrupts

23

Interrupt Service RoutineInterrupt Service RoutineOn entry, all registers (incl. CCR with I bit) have been pushed on stack,

and the I bit is set to 1 to mask further interrupts. * First check for valid interrupt. Branch to RTIIRQ if invalid.

ISRIRQ LDX #PIOC BRCLR 0,X %10000000,RTIIRQ* Execute the unique recipe for clearing device interrupt flag

LDAA PIOC LDAA PORTCL ; Wacky !!* Service interrupt

RORA RORA

RORA ; Rotate 4 times RORA ; Low nibble now has the 4 bits!

STAA PORTC ; Output to 7-segment display* Return from interrupt service routine

RTIIRQ RTI ; restore registers and return to main* Note that this restores CCR (hence I bit), re-enabling interrupts.

END

Page 24: I/O and Interrupts

24

Do Activity #2 NowDo Activity #2 NowDue: End of Class Today.

RETAIN THE LAST PAGE(S) (#3 onwards)!!

For Next Class:• Bring Huang Textbook, & HC11 PRG

• Required Reading:– Sec 4.1-4.7 of Huang

• This reading is necessary for getting points in the Studio Activity!