COMP303 Computer Architecture Lecture 18I/O System

Review: Major Components of a Computer

Important metrics for an I/O systemPerformanceExpandabilityDependabilityCost, size, weightSecurity

Processor

Control

Datapath

Memory

Devices

Input

Output

A Typical I/O System

Processor

Cache

Memory - I/O Bus

MainMemory

I/OController

Disk

I/OController

I/OController

Graphics Network

Interrupts

Disk

Input and Output DevicesI/O devices are incredibly diverse with respect to

Behavior – input, output or storagePartner – human or machineData rate – the peak rate at which data can be transferred between the I/O device and the main memory or processor

Device Behavior Partner Data rate (Mb/s)Keyboard input human 0.0001Mouse input human 0.0038Laser printer output human 3.2000Magnetic disk storage machine 800.0000-3000.0000Graphics display output human 800.0000-8000.0000Network/LAN input or

outputmachine 100.0000-

10000.0000

8 orders of magnitude range

I/O Performance MeasuresI/O bandwidth (throughput) – amount of information that can be input (output) and communicated across an interconnect (e.g., a bus) to the processor/memory (I/O device) per unit time1. How much data can we move through the system in a

certain time?2. How many I/O operations can we do per unit time?

I/O response time (latency) – the total elapsed time to accomplish an input or output operation

An especially important performance metric in real-time systems

Many applications require both high throughput and short response times

I/O System Interconnect IssuesA bus is a shared communication link (a single set of wires used to connect multiple subsystems) that needs to support a range of devices with widely varying latencies and data transfer rates

AdvantagesVersatile – new devices can be added easily and can be moved between computer systems that use the same bus standardLow cost – a single set of wires is shared in multiple ways

DisadvantagesCreates a communication bottleneck – bus bandwidth limits the maximum I/O throughput

The maximum bus speed is largely limited byThe length of the busThe number of devices on the bus

Types of BusesProcessor-memory bus (“Front Side Bus”, proprietary)

Short and high speedMatched to the memory system to maximize the memory-processor bandwidthOptimized for cache block transfers

I/O bus (industry standard, e.g., SCSI, USB, Firewire)Usually is lengthy and slowerNeeds to accommodate a wide range of I/O devicesUse either the processor-memory bus or a backplane bus to connect to memory

Backplane bus (industry standard, e.g., ATA, PCIexpress)

Allow processor, memory and I/O devices to coexist on a single busUsed as an intermediary bus connecting I/O busses to the processor-memory bus

I/O TransactionsAn I/O transaction is a sequence of operations over the interconnect that includes a request and may include a response either of which may carry data. A transaction is initiated by a single request and may take manyindividual bus operations. An I/O transaction typically includes two parts

1. Sending the address2. Receiving or sending the data

Bus transactions are defined by what they do to memoryA read transaction reads data from memory (to either the processor or an I/O device)A write transaction writes data to the memory (from either the processor or an I/O device)

input

output

Synchronous and Asynchronous Buses

Synchronous bus (e.g., processor-memory buses)Includes a clock in the control lines and has a fixed protocol for communication that is relative to the clockAdvantage: involves very little logic and can run very fastDisadvantages:

Every device communicating on the bus must use same clock rateTo avoid clock skew, they cannot be long if they are fast

Asynchronous bus (e.g., I/O buses)It is not clocked, so requires a handshaking protocol and additional control lines (ReadReq, Ack, DataRdy)Advantages:

Can accommodate a wide range of devices and device speedsCan be lengthened without worrying about clock skew or synchronization problems

Disadvantage: slow(er)

ATA Cable SizesCompanies have transitioned from synchronous, parallel wide buses to asynchronous narrow buses

Reflection on wires and clock skew makes it difficult to use 16 to 64 parallel wires running at a high clock rate (e.g., ~400MHz) so companies have moved to buses with a few one-way wires running at a very high “clock” rate (~2GHz)

Serial ATA cables (red) are much thinner than parallel ATA cables (green)

Asynchronous Bus Handshaking Protocol

7. I/O device sees DataRdy go low and drops Ack

Output (read) data from memory to an I/O device

I/O device signals a request by raising ReadReq and putting the addr on the data lines

1. Memory sees ReadReq, reads addr from data lines, and raises Ack2. I/O device sees Ack and releases the ReadReq and data lines3. Memory sees ReadReq go low and drops Ack

4. When memory has data ready, it places it on data lines and raises DataRdy

5. I/O device sees DataRdy, reads the data from data lines, and raises Ack

6. Memory sees Ack, releases the data lines, and drops DataRdy

12

3

ReadReq

Data

Ack

DataRdy

addr data

4

56

7

Key Characteristics of I/O Standards

Firewire USB 2.0 PCIe Serial ATA SA SCSIUse External External Internal Internal External

Devices per

channel

63 127 1 1 4

Max length 4.5 meters 5 meters 0.5 meters 1 meter 8 metersData Width 4 2 2 per lane 4 4

Peak Bandwidth

50MB/sec (400)

100MB/sec (800)

0.2MB/sec (low)

1.5MB/sec (full)

60MB/sec (high)

250MB/sec per lane

(1x)Come as

1x, 2x, 4x, 8x, 16x,

32x

300MB/sec 300MB/sec

Hot pluggable?

Yes Yes Depends Yes Yes

A Typical I/O System

MemoryController

Hub(north bridge)

5000P

Intel Xeon 5300processor

Intel Xeon 5300processor

MainmemoryDIMMs

Front Side Bus (1333MHz, 10.5GB/sec)FB DDR2 667

(5.3GB/sec)

PCIe 8x (2GB/sec)ESI (2GB/sec)

I/OController

Hub(south bridge)

EntrepriseSouth

Bridge 2

CD/DVD

Disk

Disk Serial ATA(300MB/sec)

Keyboard,Mouse, …

LPC(1MB/sec)

USB ports USB 2.0(60MB/sec)

PCIe 4x(1GB/sec)PCIe 4x

(1GB/sec)PCI-X bus(1GB/sec)PCI-X bus(1GB/sec)

Parallel ATA(100MB/sec)

Interfacing I/O Devices to the Processor, Memory, and OS

The operating system acts as the interface between the I/O hardware and the program requesting I/O since

Multiple programs using the processor share the I/O systemI/O systems usually use interrupts which are handled by the OSLow-level control of an I/O device is complex and detailed

Thus OS must handle interrupts generated by I/O devices and supply routines for low-level I/O device operations, provide equitable access to the shared I/O resources, protect those I/O devices/activities to which a user program doesn’t have access, and schedule I/O requests to enhance system throughput

OS must be able to give commands to the I/O devicesI/O device must be able to notify the OS about its statusMust be able to transfer data between the memory and the I/O device

Communication of I/O Devices and ProcessorHow the processor directs the I/O devices

Special I/O instructionsMust specify both the device and the command

Memory-mapped I/OPortions of the high-order memory address space are assigned to each I/O deviceRead and writes to those memory addresses are interpretedas commands to the I/O devicesLoad/stores to the I/O address space can only be done by the OS

How I/O devices communicate with the processorPolling – the processor periodically checks the status of an I/O device (through the OS) to determine its need for service

Processor is totally in control – but does all the workCan waste a lot of processor time due to speed differences

Interrupt-driven I/O – the I/O device issues an interrupt to indicate that it needs attention

Interrupt Driven I/OAn I/O interrupt is asynchronous wrt instruction execution

Is not associated with any instruction so doesn’t prevent any instruction from completing

You can pick your own convenient point to handle the interrupt

With I/O interruptsNeed a way to identify the device generating the interruptCan have different urgencies (so need a way to prioritize them)

Advantages of using interruptsRelieves the processor from having to continuously poll for an I/O event; user program progress is only suspended during the actualtransfer of I/O data to/from user memory space

Disadvantage – special hardware is needed toIndicate the I/O device causing the interrupt and to save the necessary information prior to servicing the interrupt and to resume normal processing after servicing the interrupt

Interrupt Priority LevelsPriority levels can be used to direct the OS the order in which the interrupts should be serviced

MIPS Status register

Determines who can interrupt the processor (if Interrupt enable is 0, none can interrupt)

MIPS Cause register

To enable a Pending interrupt, the corresponding bit in the Interrupt mask must be 1Once an interrupt occurs, the OS can find the reason in the Exception codes field

Inte

rrup

t en

able

Exce

ptio

n le

vel

Use

r

mod

e

Interrupt mask

15 8 4 01

Pendinginterrupts

15 8 6 2

Branchdelay

31

Exceptioncodes

Interrupt Handling Steps1. Logically AND the Pending interrupt field and the Interrupt mask

field to see which enabled interrupts could be the culprit. Make copies of both Status and Cause registers.

2. Select the higher priority of these interrupts (leftmost is highest)3. Save the Interrupt mask field4. Change the Interrupt mask field to disable all interrupts of equal or

lower priority5. Save the processor state prior to “handling” the interrupt6. Set the Interrupt enable bit (to allow higher-priority interrupts)7. Call the appropriate interrupt handler routine8. Before returning from interrupt, set the Interrupt enable bit back to

0 and restore the Interrupt mask field

Interrupt priority levels (IPLs) assigned by the OS to each process can be raised and lowered via changes to the Status’s Interrupt mask field

Direct Memory Access (DMA)For high-bandwidth devices (like disks) interrupt-driven I/O would consume a lot of processor cyclesWith DMA, the DMA controller has the ability to transfer large blocks of data directly to/from the memory without involving the processor1. The processor initiates the DMA transfer by supplying the I/O

device address, the operation to be performed, the memory address destination/source, the number of bytes to transfer

2. The DMA controller manages the entire transfer (possibly thousand of bytes in length), arbitrating for the bus

3. When the DMA transfer is complete, the DMA controller interrupts the processor to let it know that the transfer is complete

There may be multiple DMA devices in one systemProcessor and DMA controllers contend for bus cycles and for memory

The DMA Stale Data (Coherence) ProblemIn systems with caches, there can be two copies of a data item, one in the cache and one in the main memory

For a DMA input (from disk to memory) – the processor will be using stale data if that location is also in the cacheFor a DMA output (from memory to disk) and a write-back cache – the I/O device will receive stale data if the data is in the cache and has not yet been written back to the memory

The coherency problem can be solved by1. Routing all I/O activity through the cache – expensive and a

large negative performance impact2. Having the OS invalidate all the entries in the cache for an I/O

input or force write-backs for an I/O output (called a cache flush)

3. Providing hardware to selectively invalidate cache entries – i.e., need a snooping cache controller

DMA and Virtual Memory ConsiderationsShould the DMA work with virtual addresses or physical addresses?If working with physical addresses

Must constrain all of the DMA transfers to stay within one page because if it crosses a page boundary, then it won’t necessarily be contiguous in memoryIf the transfer won’t fit in a single page, it can be broken into a series of transfers (each of which fit in a page) which are handled individually and chained together

If working with virtual addressesThe DMA controller will have to translate the virtual address to a physical address (i.e., will need a TLB structure)

Whichever is used, the OS must cooperate by not remapping pages while a DMA transfer involving that page is in progress