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Quantum Dot Cellular Automata Magnitude Comparators

Bahniman Ghosh Shoubhik Gupta Smriti Kumari Department of Electrical Engineering Department of Electrical Engineering Department of Electrical Engineering IIT Kanpur IIT Kanpur IIT Kanpur Kanpur, India Kanpur, India Kanpur, India

bahniman@iitk.ac.in shoubhik@iitk.ac.in smritik@iitk.ac.in

Abstract—In this paper, first a 1-bit magnitude comparator design is presented that reduces the number of QCA cells compared to previously reported design. The proposed design requires only about 49 % of the area as compared to previous design with the same speed and clocking performance. Then, we have proposed novel 2 and 3 bit comparator designs in QCA.

Keywords-component; quantum dot cellular automata;magnitude comparator

I. INTRODUCTION

A digital magnitude comparator is an electronic device that takes two numbers as inputs in binary form and determines whether one number is greater than, less than or equal to the other number. Comparators are extensively used in central processing units and microcontrollers and thus have been researched upon and optimized in CMOS technology. Since not a lot of study effort has been made for comparator design [1] [2] in QCA, so this paper deals with QCA based comparators designs. QCA based circuits are better in terms of speed (high), integrity (high) and power consumption (low) and the ability of high parallel processing.

II. QCA BASICS

A QCA cell contains four quantum dots which are arranged in the form of a square and is occupied by two electrons. These two electrons have two stable configurations which are diagonal positions due to presence of the columbic repulsion between them. Each electron can tunnel into any of the quantum dots within a cell when the tunneling barrier is low. Tunneling barriers between quantum dots are changed with the help of QCA clocks. Due to coulombic repulsion, cells affect the configuration of the adjacent cells to them. Cell on the left influences the cell just beside it to the same logic state as itself and thus acts as a wire. This process goes on for every cell and finally the output cell changes into same logic cell as is the input cell [3]. The main function of QCA clocks is to ensure the proper transfer of the data from one place to another in a circuit. QCA clocks change the tunneling barrier between quantum dot so as to facilitate the movement of electrons within a cell

and allow them to change their configuration in a predefined manner. The direction of flow of the data is from clock 0 to clock 1 to clock 2 to clock 3 and then to clock 0 of the next clock period. Each clock has four parts which are high level, falling edge, low level and rising edge. These phases are named hold, release, relax and switch respectively. In QCA, the basic logic blocks are the inverter gate and the majority gate, where Maj(A,B,C)=AB+BC+CA (1) These two gates can be further utilized in making bigger logic gates and blocks [4]. Also, there are two types of crossings possible- multilayer and coplanar. In multilayer crossing more than one layer of cells are used like multiple layers of metal in conventional ICs [5].

III. PROPOSED DESIGNS A) 1-bit comparator

Fig. 1 and Fig. 2 show the schematic and QCA layout respectively of the proposed 1-bit magnitude comparator respectively where A and B are the inputs and A<B, A=B, A>B are the outputs and the logic functions of the comparator can be expressed as:(i) A<B � A’B (ii) A=B�AB+A’B’ (iii) A>B�AB’

Figure 1: Schematic of 1- bit comparator

Figure 2: QCA layout of 1- bit comparator

978-1-4673-5696-1/12/$26.00 ©2012 IEEE

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Simulation Result of 1-bit comparator

Figure 3: The simulation result of 1- bit comparator

B) 2-bit comparator

Figure 4: QCA layout of 2-bit comparator

Simulation Result of 2- bit comparator

Figure 5: The simulation result of 2- bit comparator

C) 3-bit comparator

Figure 6: QCA layout of 3-bit comparator

Table I Comparison of QCA comparators

QCA comparators

No. of cells

Area

(in μm2)

Delay

Previous 1-bit comparator [1]

100

0.32x0.42 = 0.13

1

Proposed 1-bit comparator

73 0.22x0.30 = 0.06

1

2-bit comparator 260 0.62X0.45 = 0.27

2.5

3-bit comparator 662 1.04x0.88 = 0.91

5

IV. CONCLUSION

In this paper, a new design of 1-bit comparator and novel design of 2 and 3 bit comparators have been proposed. The 1-bit comparator design improves upon the previous design[1] in terms of area as well as complexity.The operation of the proposed designs have been verified using QCADesigner tool. Finally designs are compared according to no. of cells, area and delay.

V. REFERENCES

[1] Q. Ke-ming and X. Yin-shui. “Quantum Dots cellular automata comparator”. In 7th International Conference on ASIC, ASICON 2007., Page(s) 1297-1300.[2] Blaz Lampreht, Luka Stepancic, Igor Vizec, Bostjan Zankar,Miha Mraz, Iztok Lebar Bajec and Primoz Pecar “Quantum-Dot Cellular Automata Serial Comparator,” 11th Euromicro on Digital System Design Architectures, Methods and Tools, 2008 Page(s) 447-452.[3] Sara Hashemi, Mohammad Tehrani and Keivan Navi“An efficient quantum-dot cellular automata full-adder,”Scientific Research and Essays Vol. 7(2), Page(s) 177-189.[4] Hema Sandhya Jagarlamudi, Mousumi Saha, and Pavan Kumar Jagarlamudi: “Quantum Dot Cellular Automata Based Effective Design of Combinational and Sequential Logical Structures,” World Academy of Science, Engineering and Technology 60 2011, Page(s) 671-675.[5] Heumpil Cho and Earl E. Swartzlander, “Adder Designs and Analyses for Quantum-Dot Cellular Automata” IEEEtransaction on Nanotechnology, Vol. 6, No.3, May 2007, Page(s) 374-383.