Novel Nickel-Alloy Silicides for Source/Drain Contact Resistance Reduction in N-Channel Multiple-Gate Transistors with Sub-35nm Gate Length

Rinus T. P. Lee, Tsung-Yang Liow, Kian-Ming Tan, Andy Eu-Jin Lim, Hoong-Shing Wong,

Poh-Chong Lim*, Doreen M.Y. Lai*, Guo-Qiang Lo**, Chih-Hang Tung**, Ganesh Samudra, Dong-Zhi Chi*, and Yee-Chia Yeo

Silicon Nano Device Lab., Dept .of Electrical & Computer Engineering, National University of Singapore, 117576

*Institute of Materials Research and Engineering, 3 Research Link, 117260 **Institute of Microelectronics, 11 Science Park Road, 117685

Phone: +65 6516-2298, Fax: +65 6779-1103, E-mail: yeo@ieee.org

ABSTRACT

In this work, we examined the Schottky-Barrier height modulation of NiSi by the incorporation of Aluminum (Al), Titanium (Ti), Erbium (Er), and Yterbium (Yb) in NiSi to form different NiSi-alloys. Among the NiSi-alloy candidates investigated, it was found that the NiAl-alloy silicide provides the most effective Schottky-Barrier height lowering (~250 meV) on n-Si(001) substrates. Integration of NiAl-alloy silicides as the source and drain (S/D) silicide material for Multiple-Gate transistors (MuGFETs) was explored, and shown to deliver a drive current IDsat enhancement of 34% compared to MuGFETs employing NiSi S/D. We further showed that the novel NiAl-alloy silicidation process is compatible with lattice-mismatched silicon-carbon (SiC) S/D stressors. NiAl-alloy silicide is therefore a promising S/D silicide material for reducing the high parasitic series resistance in narrow fin MuGFETs for enhanced device performance.

INTRODUCTION

Multiple-gate transistors (MuGFET) offer superior control of short-channel effects and enable scalability well beyond the 32 nm technology node. However, the drive current IDsat of MuGFETs would be severely compromised if the source and drain (S/D) resistances (RSD) are large. High parasitic series resistance (PSR) can arise from the use of narrow Si-Fins for MuGFETs. It has been shown that the contact resistance between the S/D silicide and Si-Fin dominates the S/D PSR behavior for MuGFETs [1]. Therefore, it is important to reduce this resistance to enable MuGFETs to demonstrate competitive performance compared to conventional planar transistors. Currently, SiGe S/D and NiPt germanosilicide have been proposed to alleviate concerns of S/D PSR in p-channel transistors [2],[3]. However, a similar effort for the reduction of S/D PSR in n-channel transistors is lacking.

In this work, we examine the material and electrical characteristics of different NiSi-alloy silicide candidates (i.e. silicides of alloys of Ni and Al, Ti, Er, or Yb) for reduction of S/D parasitic series resistance in n-channel multiple-gate

transistors. Based on the study, a novel NiAl-alloy silicide [4] was selected for integration as the S/D silicide material in n-channel MuGFETs. Performance enhancement in NiAl-alloy silicide S/D MuGFETs was explored and discussed. We further investigated the impact of NiAl-alloy silicide on silicon-carbon (SiC) S/D stressors for the future realization of strained MuGFETs with SiC S/D stressors [5].

EXPERIMENT Ni-alloy (Al, Ti, Er, Yb) films were deposited by co-

sputtering in Ar ambient. The ratio of the Ni-to-alloy metal was controlled by adjusting the respective Ni and alloy metal deposition rate and sputtering time. The total metal thickness was kept at ~ 15 nm to minimize the lateral encroachment into the channel from the S/D region. The silicidation process was completed with a one step annealing at 550oC for 30 s. Selective metal etch was then performed to remove the remaining unreacted Ni and alloy metals using a sulphuric peroxide mixture, H2SO4:H2O2 [4:1] at 75 oC for 90 s.

RESULTS AND DISCUSSION A. MATERIALS CHARACTERIZATION

Fig. 1 shows the phase transformation curve of NiSi and Ni-alloy silicides. It is seen that NiAl- and NiEr-alloy silicide films have the lowest sheet resistances and matches strongly to that obtained from pure NiSi films. The current-voltage measurements and Schottky-barrier height extraction as shown in Fig. 2 and Fig. 3, respectively, revealed that the incorporation of Al, Ti, Er and Yb in Ni modulates the NiSi Schottky-Barrier height effectively. The incorporation of Al in NiSi provided the most effective or largest reduction (~ 250 meV) in the Schottky-Barrier height of NiSi. SIMS analysis in Fig. 4 shows that the incorporated Al is distributed uniformly within the bulk NiSi film, which is likely to be responsible for the lower Schottky-Barrier height obtained on n-Si(001) substrates. In contrast, SIMS analysis for NiTi-alloy silicides (Fig. 5) showed that Ti redistributes to the NiSi

400 450 500 550 600 650 700 7500

2040

6080

100120140

NiSi NiAlSi NiTiSi NiEr Si NiYbSi

Shee

t Res

ista

nce

(Ω/

)

Annealing Temperature (oC)

Fig. 1. Phase transformation curve for Ni and Ni-alloy silicides. For the NiSi curve, it is evident that a dramatic increase in RS occers at 700 oC and this is due to the formation of Ni2Si. The annealing time at each point was for 30s in N2 ambient.

-2 -1 0 1 210-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

NiSi NiAlSi NiTiSi NiErSi NiYbSi

Cur

rent

(A)

Applied Voltage VA (V)

NiAlSi/n-Si(001)

Fig. 2. Current-Voltage characteristics of Ni and Ni-alloy (Al, Ti, Er, Yb) silicide Schottky diodes formed on n-Si(001) substrates annealed at 550 oC for 30 s in N2 ambient.

0.300.350.400.450.500.550.600.650.70

Bar

rier

Hei

ght φ

b (eV

)

Ni NiYb NiEr NiTi NiAl

Silicide Materials

Fig. 3. Schottky-Barrier heights of the Ni and Ni-alloy silicide diodes investigated in this work. Modulation of φb

n is achieved with the incorporation of Aluminum (Al), Titanium (Ti), Erbium (Er), and Yterbium (Yb) in NiSi.

top surface after silicidation. This phenomenon was also observed for NiEr- and NiYb-alloy silicide films (not shown). This is attributed to the fact that the dominant diffusion species in a Ni (Ti, Er, Yb) system during silicidation are Ni and Si. Therefore, we postulate that the effective reduction of the Schottky-Barrier height observed in this work for Ti, Er and Yb doped NiSi films to be related with the structural changes in the underlying NiSi film [6].

0 100 200 300 400 500 600 700

Time (seconds)

Inte

nsity

(cou

nts/

seco

nd)

Si

Al

NiSputter source:Cs @ 1KeV

NiAlSi-Si Interface

Fig. 4. The SIMS depth profile for the NiAl-alloy silicide shows that Al is distributed uniformly in the NiAlSi layer after a 550 oC, 30 s rapid thermal anneal in N2 ambient.

0 100 200 300 400 500 600 700

Sputter source:Cs @ 1KeV

NiTiSi-Si Interface

Inte

nsity

(cou

nts/

seco

nd)

Time (seconds)

Ti

Ni

Si

Fig. 5. The SIMS depth profile for the NiTi-alloy silicide shows that Ti redistributes such that it is at the top surface of the silicide layer. Similar Er and Yb profiles were obtained for NiEr- and NiYb-alloy silicides.

30 35 40 45 50 55 60

Inte

nsity

(cou

nts/

seco

nd)

2θ (o)

NiSi FilmsNiSi (112)

NiSi (211)

NiSi (103)

NiSi (020)

NiAlSi Films Ni2AlSi (100)

Fig. 6. X-ray diffraction reveals that the incorporation of Al in NiSi results in a phase transformation from NiSi to Ni2AlSi when annealed at 550 oC for 30 s in N2 ambient. It should be noted that the matrix effect is responsible for the long tail of the Ni signal beyond the silicide-Si interface observed in Fig 5 and 6. XRD analysis further confirms the formation of an Al-doped NiSi phase, i.e. Ni2AlSi with a preferred orientation of (100).

VA

n

VAVA

n

SiO2 Gate Oxidation (20 Å) Poly-Si deposition and Gate

SDE and Spacer Formation

Metal Deposition (Co-sputter)

P-well and Vt Adjust Fin Definition

Gate Definition

S/D Implant and RTA @ 950 °C, 30s

Silicidation Selective Metal Removal

Fig. 7. Process sequence for the fabrication of tri-gate n-channel MuGFETs. NiSi or Ni2AlSi S/D silicides are integrated.

BOX Si Fin

(b) Ni2AlSi S/D

(a) Control

Si Fin

NiSi Gate

Spacer Fin

Si S/D

Ni2AlSi S/D

Gate

Ni2AlSi S/D

(c)

(d)

Fig. 8. Schematics showing (a) control MuGFET with NiSi S/D, and (b) MuGFET with Ni2AlSi S/D. SEM micrographs showing MuGFET (c) before and (d) after Ni2AlSi formation. Ni2AlSi formed in the S/D regions shows excellent morphology.

LG = 33 nm

Ni2 AlSi

Buried Oxide

LG = 33 nm

Ni2 AlSi

Buried Oxide

GS

D

LG = 33 nm

Ni2 AlSi

Buried Oxide

LG = 33 nm

Ni2 AlSi

Buried Oxide

GS

D

Fig. 9. TEM micrograph of a transistor with Ni2AlSi silicided S/D showing a 33 nm poly-Si gate and the successful formation of ~30 nm thick Ni2AlSi silicide on the S/D region. B. DEVICE FABRICATION

Fig. 7 summarizes the key process steps employed in the fabrication of tri-gate n-channel MuGFETs on SOI substrates with a 45 nm thick Si film and a 140 nm buried oxide layer.

The device structures fabricated in this work (Fig. 8) include (a) control MuGFETs with NiSi S/D, and (b) MuGFETs with Ni2AlSi S/D. P-well and Vt adjust implants were performed and activated. Active regions with fin widths down to 30 nm were defined using 248 nm lithography, resist trimming, and reactive ion etching. 20 Å of SiO2 was used as the gate dielectric. 100 nm poly-Si was then deposited as the gate electrode, subsequently implanted and activated. Gate lithography and gate etch were performed. Spacers were formed followed by S/D implant and activation. Fig. 8(c) shows the SEM image of a MuGFET structure prior to silicidation and Fig. 8(d) shows the SEM image of a completed MuGFET with Ni2AlSi silicided S/D. Fig. 9 shows the TEM image of a LG = 33 nm n-channel transistor featuring Ni2AlSi S/D. C. ELECTRICAL CHARACTERIZATION

Fig. 10 shows the incorporation of Al in NiSi does not degrade the silicided S/D junction integrity, evident from the tight distribution of leakage currents for Ni2AlSi. Inset shows a well behaved Ni2AlSi silicided n+/p junction. Fig. 11 shows the IDS-VGS characteristics of two comparable Ni2AlSi and NiSi S/D MuGFETs with LG = 33 nm, fin width WFin= 40 nm. Similar DIBL (0.23V/V) and substhreshold swing (125 mV/dec.) values were also obtained for these two devices. In this work, MuGFETs with Ni2AlSi S/D shows 34% higher IDsat than NiSi S/D MuGFETs (Fig. 12). The IDsat enhancement is attributed to a combination of reduced PSR and also possibly silicide strain effects arising from the use of a Ni2AlSi S/D silicide material. Raman analysis supports the speculation of silicide strain revealing a more tensile strain at the silicide/Si interface with the use of Ni2AlSi. The calculated stress generated by Ni2AlSi is ~400 MPa at the silicide/Si interface with ∆ωm = 1 cm-1 when compared to unstrained bulk Si. Fig. 13 also shows an enhancement in Gm of 60% for Ni2AlSi MuGFETs compared to NiSi MuGFETs, which is indicative of enhanced electron mobility for Ni2AlSi MuGFETs.

5x10-14 1x10-13 2x10-13 2x10-13

0

20

40

60

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100

-2 -1 0 1 210-12

10-10

10-8

10-6

10-4

10-2 Ni2AlSi/n-Si(001)

Cur

rent

(A)

Applied Voltage VA (V)

Cum

ulat

ive

Prob

ablit

y (%

)

Junction Leakage Current (A/µm2)

Ni2AlSi NiSi

Measured @ 1.0 V

Fig. 10. The cumulative distribution of the junction leakage for NiSi and Ni2AlSi silicided n+/p junctions, showing a tight distribution at around 10-14 A/µm2. The inset shows a well behaved Ni2AlSi silicided n+/p junction.

510 515 520 525 530

Inte

nsity

(cou

nts/

seco

nd)

Raman shift (cm-1)

Ni2AlSi

NiSi0.69 cm -1

Fig. 11. The Raman spectra show a more tensile strain at the silicide-Si interface for Ni2AlSi when compared to NiSi.

-1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.510-12

10-10

10-8

10-6

10-4

10-2

NiSi S/D MuGFET Ni2AlSi S/D MuGFET

Dra

in C

urre

nt I D

S (A/µ

m)

Gate Voltage VGS (V)

VDS = 1.2 V

VDS = 50 mV

LG = 33 nm

WFin

= 40 nm

Fig. 12. IDS-VGS characteristics of NiSi S/D and Ni2AlSi S/D MuGFETs show comparable DIBL and subthreshold swing at the same off-state current.

0.0 0.2 0.4 0.6 0.8 1.0 1.20

100

200

300

400

500

600 NiSi S/D MuGFET Ni

2AlSi S/D MuGFET

Dra

in C

urre

nt I D

S (µA

/µm

)

Drain Voltage VDS (V)

VGS

- Vt = 1.2 V

LG

= 33 nmWFin = 40 nm

Fig. 13. IDS-VDS characteristics of Ni2AlSi S/D MuGFET shows 34 % saturation drive current enhancement over the NiSi S/D MuGFET at a gate overdrive of 1.2 V.

-1.0 -0.5 0.0 0.5 1.0 1.5 2.00

1x10-6

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3x10-6

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8x10-6

NiSi S/D MuGFET Ni

2AlSi S/D MuGFET

Tra

nsco

nduc

tanc

e G

m (S

)

Gate Voltage VGS (V)

VDS = 50 meV

LG = 33 nmWFin = 40 nm

Fig. 14. Significant enhancement in Gm of 60% is observed for MuGFETs with Ni2AlSi S/D compared to MuGFET with NiSi S/D, which is indicative of peak electron mobility enhancement.

D. NiAlSi:C MATERIALS CHARACTERIZATION

The formation of Ni2AlSi on silicon-carbon (SiC) was investigated. Epitaxial growth of Si0.99C0.01 films with a thickness of ~50 nm was performed on Si (001) substrates. High resolution XRD shows excellent crystalline quality for SiC with a 1 % substitutional carbon concentration (Fig. 16) after the completion of a 550oC, 30s NiAlSi silicidation process. The SiC peak positions for both samples in Fig. 16 are the same. (004) and (224) reciprocal space maps further reveal that the Si0.99C0.01 film remains fully strained with the Si and SiC peaks in perfect alignment even in the case of a 40 nm thick Ni2AlSi:C silicide layer formed on ~10 nm of SiC film, which was left unconsumed after the completion of the NiAlSi:C silicidation process.

34.2 34.4 34.6 34.8 35.0 35.2101

102

103

104

105

106

107

108

SiC SiC + Ni2AlSi silicidation

Inte

nsity

(cou

nts/s

econ

d)

Bragg Angle (o)

Si substrate

Si0.99

C0.01

550 oC, 30s

Fig. 15. High resolution XRD spectra show that the excellent crystalline quality of the SiC film on Si with 1% substitutional carbon is preserved even after NiAlSi:C silicidation (~40 nm) at 550 oC for 30 s.

Si peak

SiC peak (004) (224)

Fig. 16. (004) and (224) reciprocal space maps show the perfect alignment between SiC and Si peaks, showing no evidence of strain relaxation in a 40 nm thick NiAlSi:C silicidation process.

CONCLUSIONS

Ni2AlSi silicide was shown to alleviate the concerns of high parasitic S/D series resistances in narrow fins MuGFETs. Significant IDsat enhancement was observed in the Ni2AlSi S/D MuGFET and is attributed to a reduced S/D series resistance and possible silicide strain effects. Ni2AlSi was also found to be a suitable silicide material for the future realization of strained MuGFETs with SiC S/D stressors. REFERENCES [1] A. Dixit et al., IEEE TED, pp. 1132-1140, 2005. [2] S. Gannavaram et al., IEDM Tech. Dig., pp. 437-400, 2000. [3] M. C. Öztürk et al., Symp. VLSI Tech., pp. 194-195, 2005. [4] Y. H. Kim et al., IEDM Tech. Dig., pp. 1069-1072, 2005. [5] T.-Y. Liow et al., Symp. VLSI Tech., pp. 68-69, 2006. [6] A.E.-J. Lim et al., J. Electrochem. Soc., pp. G337-G340, 2006.