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Constant-�� Techniques for Rail-to-Rail CMOSAmplifier Input Stages: A Comparative Study

Shouli Yan, Jingyu Hu, Tongyu Song, and Edgar Sanchez-Sinencio*Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX 78712, USA

* Department of Electrical Engineering, Texas A&M University, College Station, TX 77843, USAemail:�slyan, hu, tsong�@ece.utexas.edu, sanchez@ee.tamu.edu

Abstract— This paper presents a comparative study of anumber of constant-transconductance (��) techniques for CMOSamplifier input stages. The pros and cons of each technique arediscussed. Theoretical analysis along with simulation results arediscussed to demonstrate the performance of each constant-��technique. Finally, we propose a novel technique which achieveswithin ��� �� variation over the full input common-modevoltage range. The new technique exhibits improvement overother existing techniques.

I. INTRODUCTION

During the past decade, there have been considerableinterests in the design of low-voltage CMOS operationalamplifiers (opamps). Rail-to-rail common-mode (CM) inputvoltage range is demanding for a high signal swing and thus ahigh signal-to-noise ratio in certain amplifier (such as unitygain buffer) configurations. The total effective input stagetransconductance (��) of rail-to-rail input CMOS amplifiersshould be maintained as constant as possible over the entireinput CM voltage range [1]�[20]. Hence, necessary constant-�� techniques need to be developed for rail-to-rail CMOSopamps. A number of rail-to-rail schemes were proposed in thepast years, and necessitate a detailed review and comparison.This paper is organized as follows. In section II, several dif-ferent schemes of constant-�� input stages are discussed andcompared. Section III introduces a new constant-�� technique.In section IV concludes this paper with with a comparisontable of different input stage schemes.

Throughout this paper we use the following notations.Total transconductance of the amplifier input stage is denotedby ��� . The ����� � and ���� � are the transconductanceand tail current of the n(p)-channel input differential pairs,respectively. ����=����� and ����=����� are the transcon-ductance parameter of the N and P input transistors. The inputCM voltage and slew rate are denoted by ��� and ��,respectively. The current summation circuits [2] to add thecurrents from the constant-�� N- and P- input differential pairstogether and converts to a single-ended output, are omitted inthe figures for simplicity.

II. REVIEW AND DESIGN GUIDELINES OF CONSTANT-��TECHNIQUES

Techniques to maintain a nearly constant �� over theentire ��� range in rail-to-rail amplifiers have been reportedin [2]�[20]. Most of them used N-P complementary input

differential pairs (except the ones in [13], [15], [21]). Asimple N-P complementary input stage is shown in Fig. 1(a).This circuit has a limitation that, at the middle of the inputCM range (i.e., Region II), the total transconductance hasnearly twice the value of a single pair in Region I or III,as illustrated in Fig. 1(b), due to the fact that there is a largeoverlap between the CM swings of the N differential pair M1n-M2n and the P differential pair M1p-M2p, as illustrated inFig. 1(c). This drawback results in variable DC gain, unity-gain bandwidth, nonconstant SR, and non-optimal frequencycompensation [1]�[22].

Several guidelines could be followed for constant-�� cir-cuits. First, the large-signal and small-signal performances ofthe rail-to-rail stage should be maintained constant regardlessof the varying ��� level. Second, the accuracy of thetechnique does not rely on any particular characteristic (suchas the MOS drain current square law) and any strict ����

and ���� matching of the input devices. In other words,the technique should be universal and robust. Thirdly, thecircuit should allow high-frequency/high-speed operation andconsume low power. Finally, the complexity of the techniqueshould be moderate. Please note that different applicationsmay demand different design requirements. For example, highbandwidth is needed for video applications, while compactnessis demanded for VLSI cell libraries. In this section, we willgive a brief overview of several reported techniques. Due tothe space limitations, not all published constant-�� techniquesare included.

A. Constant-�� Technique I – Varying Tail Current

Stabilization of the total �� can be tackled by altering theeffective tail currents of the input differential pairs. A typicalexample is to use square-root circuit [2], [3]. The work in [3]used new bias circuits not requiring ���� and ���� matchingof input pair transistors for proper operation. Another schemeis to employ current switches to increase the tail current when��� is near power supply rails ��� or ��� to 4 times of thetail current when ��� is in the mid-range [2], [4], [5]. Theconceptual circuit is shown in Fig. 2(a) and the real circuit inFig. 2(b). When ��� is close to either ��� (or ���), onlySW1 (or SW2) is on. SW1 (or SW2) diverts tail current ��from P (or N) pair to the N (or P) pair through a 1:3 currentmirror and thus increase the effective tail current of the activeN (or P) pair by four times. For mid-range ��� levels, bothswitches are off thus the total �� stays as the nominal value.

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The above square-root circuit and 1:3 current mirror circuithave two limitations. First, both depend heavily on draincurrent quadratic characteristic (i.e., the square-law model)of the input MOS transistors, thus they can not be applieduniversally to strong and weak inversion operation regions, andare not compatible with deep submicrometer CMOS devicesthat do not follow quadratic characteristic accurately. Second,the SR is a function of ��� and has a variation of 2 timesfrom rail to rail. The input stage in Fig. 3(a) overcome theseproblems by employing two backup pairs to replace two pri-mary pairs [6]. Transistors M1A-M4A are biased normally andform two primary pairs, and transistors M1B-M4B are backuppairs biased with current steered (through either current switchSWN or SWP) from the primary pairs. Another scheme [9]has similar underlying idea to that of [6]. Fig. 3(b) depictsthe circuit with a hex-pair structure. Three differential pairsof each polarity are used. At supply rails when one of inputpairs (M1A-M2A or M3A-M4A) loses sufficient gate driveto operate, another pair similar to the active pair is activated.As a result, two similar pairs of same polarity generate signalcurrent in parallel, hence the input �� doubles to have thesame �� as that when both pairs are active.

The tail-current-varying constant-�� techniques exhibit sub-stantial improvements over the simple circuit in Fig. 1, but stillpossess a serious drawback, 15�-20� systematic �� variation(see Appendix for the proof) over the entire input commonmode range. The �� variations of some circuits based onconstant-�� technique I are shown in Fig. 4.

B. Constant-�� Technique II – Maximum/Minimum CurrentSelection

To further reduce the input stage �� variation, maxi-mum/minimum current selection constant-�� techniques areused in [7], [8], [10]. The working principle of this techniqueis illustrated in Fig. 5(a). When ��� drives the tail currenttransistor out of saturation region, the tail current will decreasesignificantly. The differential pair with the larger tail currentshould be working properly. Fig. 5(b) describes one circuitimplementation of a maximum current selection technique [8].In this technique, the input pair with the larger working currentis always chosen while the output of another pair is discarded.There is another configuration of this technique which utilizesfolded-cascode circuit and minimum selection circuit to getthe maximum �� in a similar way [8]. The advantage of thelatter scheme is that a wider CM range can be achieved.

The maximum/minimum current selection technique pro-vides better constant-�� behavior (5� in [8] and 6� in [7])than technique I. As only the largest signal current is chosen,the SR is kept constant. In addition, this technique can workfor all operation regions of input MOS transistors. However,the transient settling behavior of this technique is imperfectbecause the current selection circuit may present open loophigh impedance nodes, preventing high-speed operation.

C. Constant-�� Technique III – Level Shifting

A few years ago, the idea of level shifting to achieveconstant �� was reported [11]. As shown in Fig. 6(a), the

transition region (i.e. the ��� range where its tail currentsource operates in the triode) of the p-channel input differentialpair is shifted up by DC level shifters to overlap with thatof the N pair. Two P source followers are used as DC levelshifters in [11], as shown in Fig. 6(b). It has very goodconstant-�� behavior (��� �� deviation) but also a majorlimitation: there is a need to manually tune the bias currentsof the input DC level shifters (�� in Fig. 6(b)). The workin [12] employs two automatic tuning sections to obtain theoptimum current value for the level shifter thus variations��� � over ��� range is minimized, as shown in Fig. 7(a).

In a recent work [13], unlike traditional approaches based oncomplementary input pairs, the authors uses two N differentialpairs which avoids the matching requirement between N andP pairs (Fig. 7(b)). Two identical source followers are usedin front of the input pair M1-M2. In addition, a feedforward(FF) canceling section is designed to ensure that only onedifferential pair contributes to the total �� for any ��� levels.This technique accomplishes all of the necessary features ofan ideal rail-to-rail input stage except that the measured ��deviation exceeds ���.

Very small �� and SR variations (within ���) can beachieved using technique III if the DC shift level is tunedcarefully. It is worth noting that circuits designed using levelshifting techniques are sensitive to �� and power supplyvoltage variations and mismatch between N and P input pairs.

Other constant-�� techniques include, i) sensing and regula-tion of the amplifier �� [14], ii) single input differential pairwith boosted ��� for the input stage using a charge pump[21], or tunable DC level shifters via multiple input floatinggate transistors [15], and iii) electronic zener diode regulation[16].

D. Constant-�� Techniques for Extremely Low Supply Volt-ages

Most previous published techniques are only valid for powersupply voltage �� � � ������� higher than ��� �������������� (see Fig. 1). For very low voltage supply (less than2V), there is a forbidden input voltage region where neither ofthe input pair is turned on, which makes it extremely difficultto obtain a rail-to-rail constant-�� input stage. Dynamic-levelshifting techniques was first proposed in [17] and later studiedin [18]. Similar constant-�� techniques for very low supplyvoltages has been studied in [19], [20]. Boosting ��� hasthe potential to work with a low supply voltage, but a highbreakdown voltage is required for critical transistors in thecharge pump.

III. NEW CONSTANT-�� INPUT-STAGE ARCHITECTURE

FOR 3-V POWER SUPPLY

In this section, we introduce a novel constant-�� technique.The basic structure of the new rail-to-rail constant-�� inputstage is shown in Fig. 8(a). It is designed using a dynamiccurrent scaling technique. The output signal currents of theinput N and P channel differential pairs are scaled dynamicallyby a factor of ����� and ��� ������, respectively. Thusa constant �� can be obtained while the tail currents of the

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TABLE I

SUMMARY AND COMPARISON OF CONSTANT-�� TECHNIQUES.

technique I II III new�� variation 15� �20� 5� �7� 8� �9� 3�SR variation 2 times or constant constant constant constantuniversality some (e.g. [2]) universal universal universal

relies onthe square law

complexity simple moderate moderate simplespeed fast moderate fast fast

input transistors are unchanged. The new constant-�� schemeachieves ����� and ���� �� variation, respectively, forinput devices in strong and weak inversion operation regions.Simulation results with transistors in strong inversion region isgiven are Fig. 8(b). The advantage of the new scheme is that,it can be applied to both short and long channel transistors,and is compatible with deep sub-micrometer CMOS devices.Interested readers can refer to [22] for details.

IV. CONCLUSION

We have investigated several published constant-�� tech-niques for low-voltage rail-to-rail CMOS amplifier inputstages. The tail-current varying technique is relatively simplebut has large �� variations. The maximum/minimum selectiontechnique has smaller �� variation but lacks good transientperformance. Level shifting technique only needs additionalsource followers but its �� variation is sensitive to mismatchand power supply voltage change. In Section III, we brieflypresent an innovative constant-�� technique based on dynamiccurrent scaling technique. Table I provides a brief comparisonof the characteristics of the constant-�� techniques discussedin the previous sections. The authors cordially acknowledgethe critical comments and suggestions from the anonymousreviewers.

V. APPENDIX

In this appendix, we will prove that the total �� of theinput stage in Fig. 2(b) has around 15� deviation over thefull input common-mode range. Refer to Fig. 2(b), if ��� isbetween ������� and �������� , transistor M116 is partlyconducting, and the rest of tail current flows through M3 andM4, which is assumed to be �� here. The tail current of theP input pair M1-M2 is thus �� ���� � ���. Therefore,the total �� of the input stage is given by

��� �������� �

��� � ��� � ����� (1)

where �= �������

�������

= �������

�������

. Calculate themaximum value of (1), we can obtain that when �� � �

��� ,��� reaches its maximum value, which yields

��� �������

��

��� � �

������� � �������

(2)hence ��� is about 15� above its nominal value

����� .

REFERENCES

[1] S. Yan and E. Sanchez-Sinencio, “Low voltage analog circuit designtechniques: A tutorial,” IEICE Trans. Analog Integrated Circuits andSystems, vol. E00-A, no. 2, pp. 1-17, Feb. 2000.

[2] R. Hogervorst, R. J. Wiegerink, P. A. L. de Jong, J. Fonderie, R.F. Wassenaar, and J. H. Huijsing, “CMOS low-voltage operationalamplifiers with constant-�� rail-to-rail input stage,” in IEEE Proc.ISCAS ’92, vol. 6, May 1992, pp. 2876-2879.

[3] S. Sakurai and M. Ismail, “Robust design of rail-to-rail CMOS opera-tional amplifiers for a low power supply voltage,” IEEE J. Solid-StateCircuits, vol. 31, no. 2, pp. 146-156, Feb. 1996.

[4] R. Hogervorst, J. P. Tero, R. G. H. Eschauzier, and J. H. Huijsing, “Acompact power-efficient 3-V CMOS rail-to-rail input/output operationalamplifier for VLSI cell libraries,” IEEE J. Solid-State Circuits, vol. 29,no. 12, pp. 1505-1513, Dec. 1994.

[5] J. H. Huijsing, R. Hogervorst, and K.-J. de Langen, “Low-power low-voltage VLSI operational amplifier cells,” IEEE Trans. Circuits andSystems-I, vol. 42, no. 11, pp. 841-852, Nov. 1995.

[6] R. Hogervorst, S. M. Safai, and J. H. Huijsing, “A programmable 3-VCMOS rail-to-rail opamp with gain boosting for driving heavy loads,”in IEEE Proc. ISCAS ’95, vol. 2, May 1995, pp. 1544-1547, .

[7] S. Yan and E. Sanchez-Sinencio, “A programmable rail-to-rail constant-�� input structure for LV amplifier,” in IEEE Proc. ISCAS ’00, vol.5, May 2000, pp. 645-648.

[8] C. Hwang, A. Motamed, and M. Ismail, “Universal constant-�� input-stage architecture for low-voltage op amps,” IEEE Trans. Circuits andSystems-I, vol. 42, no. 11, pp. 886-895, Nov. 1995.

[9] W. Redman-White, “A high bandwidth constant �� and slew-rate rail-to-rail CMOS input circuit and its application to analog cell for lowvoltage VLSI systems,” IEEE J. Solid-State Circuits, vol. 32, no. 5, pp.701-712, May 1997.

[10] C. Hwang, A. Motamed, and M. Ismail, “LV opamp with pro-grammable rail-to-rail constant-�� ,” in IEEE Proc. ISCAS ’97, vol.3, June 1997, pp. 1988-1991.

[11] M. Wang, T. L. Mayhugh, Jr., S. H. K. Embabi, and E. Sanchez-Sinencio, “Constant-�� rail-to-rail CMOS op-amp input stage withoverlapped transition region,” IEEE J. Solid-State Circuits, vol. 34,no.2, pp.148-156, Feb. 1999.

[12] J. M. Carrillo, J. F. Duque-Carrillo, J. L. Ausin, and G. Torelli,“Rail-to-rail constant-�� operational amplifier for video applications,”Integration, the VLSI Journal, vol. 37, no. 1, pp. 1-16, Feb. 2004.

[13] J. M. Carrillo, J. F. Duque-Carrillo, G. Torelli, and J. L. Ausin,“Constant-�� constant-slew-rate high-bandwidth low-voltage rail-to-rail CMOS input stage for VLSI cell libraries,” IEEE J. Solid-StateCircuits, vol. 38, no. 8, pp. 1364-1372, Aug. 2003.

[14] J. F. Duque-Carrillo, J. M. Carrillo, J. L. Ausin and E. E. Sanchez-Sinencio, “Robust and universal constant-�� circuit technique,” Elec-tronics Letters, vol. 38, no. 9, Apr. 2002.

[15] T. W. Fischer and A. I. Karsilayan, “Rail-to-rail amplifier input stagewith constant �� and commomode elimination,” Electronics Letters,vol. 38, no. 24, Nov. 2002.

[16] R. Hogervorst, J. P. Tero and J. H. Huijsing, “Compact CMOS constant-�� rail-to-rail input stage with ��-control by an electronic zenerdiode,” IEEE J. Solid-State Circuits, vol. 31, no. 7, pp. 1035-1040,July 1996.

[17] J. Fonderie, M. M. Maris, E. J. Schnitger, and H. Huijsing, “1-Voperational amplifier with rail-to-rail input and output ranges,” IEEEJ. Solid-State Circuits, vol. 24, no. 6, pp. 1551-1559, Dec. 1989.

[18] J. F. Duque-Carrillo, J. L. Ausin, G. Torelli, J. M. Valverde, and M. A.Dominguez, “1-V rail-to-rail operational amplifiers in standard CMOStechnology,” IEEE J. Solid-State Circuits, vol. 35, no. 1, pp. 33-34,Jan. 2000.

[19] J. M. Carrillo, J. F. Duque-Carrillo, G. Torelli, and J. L. Ausin, “1-Vquasi constant-�� input/output rail-to-rail CMOS op-amp,” in IEEEProc. ISCAS ’03, vol. 1, May 2003, pp. 277-280.

[20] G. Ferri and W. Sansen, “A rail-to-rail constant-�� low-voltage CMOSoperational transcondcutor amplifier,” IEEE J. Solid-State Circuits, vol.32, no. 10, pp. 1563-1567, Oct. 1997.

[21] T.A.F. Duisters and E. C. Dijkmans, “A -90-dB THD rail-to-rail inputopamp using a new local charge pump in CMOS,” IEEE J. Solid-StateCircuits, vol. 33, no. 7, pp. 947-955, July 1998.

[22] S. Yan, J. Hu, T. Song, and E. Sanchez-Sinencio, “A constant-�� rail-to-rail Op Amp input stage using dynamic current scaling technique,”to be published in IEEE Proc. ISCAS ’05.

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Input Common-Mode Voltage Vi,cm

VSS VDD

gm

gmT, the sum of gmN and gmP

gmNgmP

Region II

Region IIIRegion I

(b)

Cur

rent

Sum

mat

ion

and

Sub

sequ

ent S

tage

s

Vi+

(a)

VSS

VDD

M1n M2n

IN

IP

M1p M2p

MBn

MBp N-channel

pair active

region

Both pairs

active

region

P-channel

pair active

region

VCMP

VCMN

(c)

VSS

VDD

Vi–

Fig. 1. Conventional N-P complementary rail-to-rail input stage, (a) basiccircuit, (b) �� vs input CM voltage, and (c) CM swings of N and P inputpairs (���� and ���� ).

M1 M3 M4 M2IN

IP

Iref

Cur

rent

Sum

mat

ion

and

Sub

sequ

ent

Stag

es

In

In

VDD

VSS

1:3

1:3

Iref

SW1

SW2

(a)

M121 M122

M1

M3 M4

M2

M116

Iref

1.4V

1.4V

Iref

M124

M113 M114C

urre

nt S

umm

atio

n an

d S

ubse

quen

t St

ages

Vi+ Vi– Vi+

(b)

Vi–

VDD

VSSSW1

SW2

Fig. 2. Rail-to-rail constant-�� input stage using constant-�� technique I[4], (a) conceptual circuit, (b) real circuit.

VDD

Iref

IrefVSS

M1B M1A

M3B M3A M4A M4B

M2A M2B

M5 M6

M10

M8 M9

M7

Vb1

Vb2

To

the

sum

mat

ion

and

subs

eque

nt s

tage

s

Vi–Vi+

(a)

Iref Iref Iref

IrefIref Iref

Cur

rent

Sum

mat

ion

VDD

VSS

M1A M1B M2B

M2A M2CM1C

M3A M3B M4B M4A M4CM3C

Vi–

Vi+

(b)

Iref Iref Iref

IrefIref Iref

Cur

rent

Sum

mat

ion

VDD

VSS

M1A M1B M2B

M2A M2CM1C

M3A M3B M4B M4A M4CM3C

Vi–

Vi+

(b)

SWN

SWP

Fig. 3. Rail-to-rail input stages using constant-�� technique I, (a) backup-pair circuit in [6], (b) backup-pair circuit in [9].

VSS VDD

Vi,cm

1.0

2.0

gm

1.0

2.0

gm

2.4

1.0

2.0

gm

2.4

gmT of rail-to-rail input stage with gm control

gmT of rail-to-rail input stage without gm control

VSS VDD

Vi,cm

VSS VDD

Vi,cm

(a) (b) (c)

Fig. 4. Transconductance vs. input CM voltage of rail-to-rail input stages in(a) [4], (b) [6], and (c) [9].

Vss VDD

Itail (gm)

M11 M12 M13 M14 M15

M1 M2

M3 M4

M16 M17

M21 M22 M23 M24 M25

M16 M17

VDD

VSS

Io+

Io–

To

the

next

sta

ge

Maximum Selection I Maximum Selection II

Vi+ Vi–

Input Common-Mode Voltage Vi,cm

IN (gmN) IP (gmP)

gmT of rail-to-rail input stage with maximum current selection

(a) (b)

IN

IP

Fig. 5. Rail-to-rail constant-�� input stage using constant-�� technique II[8], (a) working principle, (b) circuit example.

VSS VDD

gm

gmT ( after level shift )

gmN

gmP( before level shift )

gmP( after level shift )

VSS

M5

M3 M4

M2M6

M8

M7

M10

M9Mb3

M1

Mb2Mb1

Iref IP

IN

To the next stage

(a) (b)

Vi+ Vi–

VDD

Input Common-Mode Voltage Vi,cm

Overlapped transition regions

DC level

shifters

Fig. 6. Rail-to-rail constant-�� input stage using constant-�� technique III[11], (a) working principle, (b) circuit example.

VSS

M5

M3 M4

M2M6

M8

M7

M10

M9

Mb3

M1

Mb2

IP

IN

To the next stage

Vi+ Vi–

VDD

Tun

ing

for

tran

sitio

n re

gion

ov

erla

ppin

g

VSS

M5

M3 M4

M2M6

Mb3

M1

Mb2

Iref

To the next stage

Vi+ Vi–

VDD

FF C

ance

ling

Stag

e

(a) (b)

Vis+ Vis–

Vi+ Vi–

Vis+Vis–

Iref

Fig. 7. Rail-to-rail input stages using constant-�� technique III, (a) circuitexample [12], (b) circuit example [13].

Vi+ Vi–

IN

IP

MPA

MNA MNB

MPB

p(Vi,cm)

p(Vi,cm)

1-p(Vi,cm)

1-p(Vi,cm)

VDD

Dynamic Current Scaling CircuitVSS

Cur

rent

Sum

mat

ion

(a) (b)

Fig. 8. The new input-stage, (a) basic architecture, (b) simulation result of�� vs. ����� characteristics of the proposed input stage .

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