GOVERNMENT OF INDIA, DEPARTMENT OF SPACE .... 5...ISRO Satellite Centre [ISAC], HAL Airport Road, Vimanapura Post, Bangalore – 560 017, invites sealed tenders for the supply of the

ISAC/PUBLIC TENDER NOTICE NO. 05 14th May, 2015

On behalf of the President of India, Head, Purchase & Stores, ISRO Satellite Centre [ISAC], HAL Airport Road, Vimanapura Post, Bangalore – 560 017, invites sealed tenders for the supply of the following items:

TWO PART TENDER

01 ISGE-2014-0-28293-01 100% Polyester knitted screen

02 ISIR -2014-0-30096-01 GNSS RF Front End ASICs

03 ISIR-2015-0-30659-01 Design & Fabrication of High Density Interconnect Printed Circuit Boards

SUBMISSION OF TENDER : 25TH June 2015 AT 16.00HRS (IST) OPENING OF TENDER : 26TH June 2015 AT 10.30HRS (IST)

Tender documents can be downloaded from www.isro.gov.in. Tender fees at Rs. 229/- by Demand Draft shall be drawn separately for each Tender and submitted along with offer. Tenders will be opened in presence of attending Tenderers or their authorized representatives on production of valid Authorisation Letter.

Head, Purchase & Stores

GOVERNMENT OF INDIA, DEPARTMENT OF SPACE ISRO SATELLITE CENTRE (ISAC)

TWO PART

SL. No. 03 FILE NO. ISIR-2015-0-30659-01 Description: Design & Fabrication of High Density Interconnect Printed Circuit Boards Quantity : As per Tender document

Specifications For

Design and fabrication of

High Density Interconnect Printed Circuit Boards

Table of Contents

1. Introduction .................................................................................................................

2. Scope of the document ...............................................................................................

3. Applicable Documents ................................................................................................

4. Terms and Definitions .................................................................................................

5. Scope of the Indent.....................................................................................................

6. PCB Design and Analysis and Fabrication .................................................................

7. Deliverables for Design and fabrication ......................................................................

8. Types of circuits and Quantity ....................................................................................

9. Responsibility Matrix ...................................................................................................

10. General Terms and Conditions ................................................................................

11. Other Terms and Conditions ...................................................................................

12. Quote Details ...........................................................................................................

13. Compliance Matrix ...................................................................................................

14. Quote Matrix ............................................................................................................

15. Annexure 1 – Circuit Details for Design and analysis ..............................................

16. Annexure 2 - Circuit Details for Proto-model Fabrication.........................................

17. Annexure 3 - Circuit Details for Qualification model Fabrication ..............................

18. Constraint Manager Inputs ......................................................................................

1. Introduction

ISRO Satellite Centre is the nodal centre for development of communication and remote sensing satellites for Indian space programmes.

Electronic packaging is the backbone of any satellite systems and continuous research and development are being carried out to improve the performance and reduce the weight and volume, which are a premium.

High Density Interconnect technology is proposed for electronic packaging in space systems due to its advantages in performance, weight and volume and ability to accommodate fine-pitch high pin count components, especially array components.

2. Scope of the document

The scope of this document is to provide the requirementsfor design, design analysis, fabrication and testing of High Density Interconnect PCBs and their supply to ISAC.

3. Applicable Documents

1. IPC/JPCA-2315 Design Guide for High Density Interconnects and microvias 2. IPC-2226 Sectional Design Standard for High Density Interconnect Printed

Boards 3. IPC-6016 Qualification and performance specification for High Density

Interconnect Layers or Boards 4. IPC-6012 Qualification and performance specification for rigid printed Boards 5. IPC-4761Design guide for protection of printed board via structures 6. ISRO-PAX-304 –Issue 2 Acceptance and tests requirements for Printed

circuit boards

4. Terms and Definitions

1. ISAC : ISRO Satellite Centre 2. MCHF: Micro Circuits and High Density Interconnect Facility at ISAC 3. ECAD: Electronic CAD Design Facility at ISAC 4. PCF: Printed Circuits Facility at ISAC 5. Vendor: The entity responsible for carrying out the activities as mentioned in

the scope. The vendor will interact directly with ISAC during design, fabrication and testing phases.

6. HDI: High Density Interconnect 7. MLB: Multilayer Printed Circuit Board 8. SRG: System Reliability Group at ISAC

5. Scope of the Indent

The scope of the indent includes the following:

5.1. PCB Design and Analysis Design of HDI layout from the schematic provided

Analysis of the design

Design Verification

5.2. Protomodel Fabrication Fabrication of Protomodel PCB

Testing of fabricated PCB

Acceptance of PCB by ISAC

5.3. Qualification model Fabrication Fabrication of qualification model PCB

Testing of fabricated PCB

Approval and Acceptance of PCB by ISAC

6. PCB Design and Analysis and Fabrication

6.1. General guidelines IPC Performance Class: Class 3, High Reliability Electronic Products

IPC Producibility Level: Level A, General Design Complexity

IPC Board Type/Construction: Type 3, Multilayer board with Blind Via

The vendor should use Expedition / Allegro / CR5000 / CR8000 for design

Design Analysis should be done by Hyperlynx.

Copy of the license of all tools used should be enclosed in the bid.

6.2. Inputs from ISAC Schematic with constraint manager inputs

Footprint drawing in pdf format

Datasheets in pdf format for pin assignments

Components List in Excel / pdf with dissipation.

PCB Mechanical Drawing in dxf format

IBIS/Spice Models of components in ASCII format, if required. Wherever IBIS/Spice models are not available, the same should be generated by the vendor using Hyperlynx Visual IBIS Editor/Spice Model Generator and should be used after ISAC approval

6.3. Design of HDI layout from the schematic using Integrated Design Environment for schematic entry, Layout and Analysis - Activities involved

Footprint generation for the part and mapping with circuit symbol

Generation of PCB outline as per given mechanical dimensions (imported DXF) and placement of stacking holes

Schematictransfer

Placement of fixed position components as per mechanical drawing

Component Placement using component file and as suggested by designer.

Layer Stack-up Definition

Design Rule generation as per Table 2

Routing

Copper pouring as per design requirement

Design Rule and electrical rules checking

Completion of layout

6.4. Design analysis The vendor should use Hyperlynx tool for analysis.

The analysis should be performed as per the details of each design.

The vendor should enclose the results of each analysis for verification.

Signal Integrity (SI) analysis

SI analysis at pre-layout stage, if applicable SI analysis at post layout stage as per constraints manager Cross talk analysis SSN Analysis Reflection analysis – Overshoot, undershoot, rise and fall time, settling

time. Suggest termination type and value of components. Impedance analysis Preparation of report based on analysis

Power Integrity (PI) analysis

IR Drop analysis Decoupling analysis and suggest value of decoupling capacitors and

locations Resonance analysis. Frequency plot should be given. Preparation of report based on analysis

EMI/EMC Analysis

Compliance analysis based onstandards DFT plot for specified nets as per constraints manager Preparation of report based on analysis

Thermal Analysis

Identification of hotspots and design analysis under vacuum condition. Board design in STEP format to be provided.

6.5. Design Verification ISAC will perform verification of design by intelligent pdf, reports and verification at

Vendor’s site, if required.

Modification suggested by ISAC should be incorporated in the design with maximum 5% modification in nets/components.

6.6. Design Approval On successful verification and implementation of changes if any, ISAC will approve the

design for fabrication.

Approval of the design will be subject to compliance / clearance of all design requirements and applicable analysis requirements like thermal, EMI, EMC, SI and PI. All iterations to meet the design or analysis compliance should be done at no additional charges.

A copy of all the details in hard and soft form after approval should be handed over to ISAC.

6.7. PCB fabrication Raw Materials

The vendor should provide details of the materials used in the fabrication process and their technical datasheets and Certificate of Compliance

The materials should meet the specs as provided in Table 1 Sl No Material Description Specification / Compliance

1 Laminate High Tg FR4 with Tg >175 0C and complying to IPC 4101/29 or IPC4101/24

2 Prepreg High Tg FR4 with Tg >175 0C and complying to IPC 4101/29 or IPC4101/24

3 Laser Drillable Prepreg High Tg FR4 with Tg >175 0C

4 Via plugging materials Compatible CTE for laminates mentioned and shall be stable in thermo vacuum environment. Material should also meet the requirement of outgassing requirements of TML<1% and CVCM<0.1% and comply with IPC-4761

5 Soldermask Epoxy based and shall be stable in thermo vacuum environment. Material should also meet the requirement of outgassing requirements of TML<1% and CVCM<0.1%. Should be compatible with polyurethane conformal coating

Table 1 Details of Materials

The specifications for the PCB are provided in Table 2. Sl No Parameter Specifications Remarks

1 No. of layers (N) Maximum 14 -

2 Core layers (n) N-4 -

3 Construction 2+n+2. n can be max. 10 Eg. Stacked via 1-2, 2-3, 12-13,13-14

4 Through Via 200 µ 650µ pad

6 Through via plating 35 + 10 µ -

7 Inner layer copper thickness (core)

35 µ -

7 Stacked vias 150 µ 450µ pad

8 Stacked via filling with copper

9 Through Via filling Hole plugging material

10 Cap plating thickness 30µ minimum -

Sl No Parameter Specifications Remarks

11 Outer layer basic copper thickness (foil thickness)

~9 + 4 microns

-

12 Total Outer layer copper thickness without cap plating

40µ minimum -

13 Total Outer layer copper thickness with cap plating

60µ minimum -

14 Layer 2 and Layer N-1 basic copper thickness (foil thickness)

~9 + 4 microns

-

15 Total copper thickness for Layer 2 and Layer N-1

40 µ minimum Without cap plating

16 Layer 3 and Layer N-2 basic copper thickness (foil thickness)

~9 + 4 microns

17 Total copper thickness for Layer 3 and Layer N-2 without cap plating

40 µ minimum

18 Total copper thickness for Layer 3 and Layer N-2 with cap plating

60 µ minimum

19 Line width 125 microns

20 Spacing 125 microns

21 Surface finish HASL Corner : Just coverage sufficient

22 Dielectric thickness in L1-L2, L2-L3, N-2)-(N-1), (N-1)-N

Minimum 50 microns. Max. 100 microns

23 Core layers Dielectric thickness

100 microns minimum

25 Card thickness 2.2+ 0.15 mm

Table 2 Specifications for the PCB Test coupon requirements

Each MLB/Panel shall have four test coupons (as per the standard test pattern of ISAC) integrated with card by routing process. Two test coupons shall be sent to ISAC for the verification tests. Other two coupons shall be used for conducting tests at vendor facility. Gerber files of test coupon will be

supplied by ISAC. The test coupon details and layout / placementare as per ISRO-PAX-304 Issue 2 Clause 7.9.

Process

The vendor should provide the detailed process flow with flow chart and equipments and process parameters used in each process and Process Identification Document (PID) / Standard Operating Procedures (SOP)

Details of chemicals used in each chemical process with part number are preferred to be given.

Details of metallization techniques should be provided. Direct metallization shall not be used. Blind vias should be metal (copper) filled. Via dimples should not be more than 10 microns Buried vias should be filled with via plugging material. Adequate test coupons should be processed along with the panel for quality

analysis of PCBs. ISAC supplied coupon gerber should be incorporated in the PCB panel.

In-process Inspection

The details of in-process inspections stages, activities carried out and reports for the same should be provided.

Final Inspection

The final inspection at vendor’s place should include, but not limited to, the following

Visual inspection Mechanical Inspection Bare board electrical testing Impedance tests Micro section tests. HATS (500 cycles) for Qualification model PCB

Tests and reports

The details of the acceptance tests to be carried out is listed in ISRO-PAX-304 Issue-2 Clause 7.10

The inspection reports that shall accompanied PCBs being supplied is as per ISRO-PAX-304 Issue-2 Clause 7.10.5

Packing, storage and shipment

Adequate care should be taken during, packaging, handling and transportation of the PCBs to avoid the damage during transportation from rough handling, heat, humidity, dust, mechanical shock, vibration and ionic

contamination. The packaging, storage and shipment for PCBs should be as per the details provided in ISRO-PAX-304 Issue-2 Clause 7.12

Proto model PCB acceptance at ISAC

ISAC will accept the PCBs based on the test results from the vendor. ISAC also reserves the right to conduct the following tests for quality

evaluation of the PCBs at ISAC. If PCBs are rejected, replacement PCBs to be provided free of cost. Visual Inspection

Mechanical Inspection

Impedance tests

Microsection tests of two test coupons provided along with the panel.

Performance evaluation by Subsystem

Qualification model PCB Evaluation and Acceptance by ISAC

ISAC will conduct the following tests for quality evaluation of the PCBs at ISAC Visual Inspection

Mechanical Inspection

Impedance Tests

Microsection and Electrical tests of two test coupons provided along with the panel.

Any rejection will be intimated to the vendor and the same needs to be replaced at the earliest.

7. Deliverables for Design and fabrication

7.1. Deliverables from ISAC The deliverables from ISAC will be given in soft form through mail to the vendors.

Other inputs if any, in CDs or hard formats should be collected by the vendor from ISAC.

The following are the deliverables from ISAC.

Schematic with constraint manager inputs Footprint drawing in pdf format Datasheets in pdf format for pin assignments Components List in Excel / pdf PCB Mechanical Drawing in dxf format IBIS/Spice Models of components in ASCII format. Any model not provided and

mentioned to be required should be generated by Vendor with approval from ISAC.

Test Coupon Gerber ISRO standards as mentioned in applicable documents

7.2. Deliverables from Vendor Layout Design and Analysis

Stage1:Schematic Design file and intelligent pdf Stage 2: Component placement report Stage 3: Stack-up report Stage 4: Routing completion report Stage 5: DRC report, board status reports and constraints set file. Stage 6: Post layout analysis reports as per Clause 6.4 Stage 6: Final Data pack with the following

Soft Formats Gerber files in extended gerber format

Drill file and rout files in Excellon-2 format

PCB file

Design File

Silk screen files

Soldermask files

Paste mask files

Placement files with body centering

PDF files for all layers

Component marking print for top and bottom layers

Component list

Drill report

Printed Formats ( hard copy) All layer print outs

Silk screen prints

Component marking & placement print for top and bottom layers

Component list

PTH marking print

Drilling details

Drill report

The vendor should provide the deliverables at each stage to ISAC and ISAC will verify the same

PCB Fabrication

PCBs in ordered quantity with associated test coupons Test / inspection reports as mentioned in ISRO-PAX-304 Issue 2 Clause

7.10.5 Reports of any other additional tests, if conducted. In-process inspection records Traveler cards Non-conformance reports, if any, and close-outs.

8. Types of circuits and Quantity

8.1. Design As per Annexure 1

8.2. Proto Model As per Annexure 2

8.3. Qualification Model As per Annexure 3

9. Responsibility Matrix

SL No Activity Responsibility Deliverables from ISAC

Deliverables from Vendor

ISAC Vendor

1 Schematic Design √ √ - -

2 Layout Design as per clause 6.3

√ As per Clause 6.2 -

3 Design Analysis as per clause 6.4

√ As per Clause 6.2 -

4 Design Verification √ √ Design, reports and intelligent pdf

5 Design Modification √ √ Design changes

SL No Activity Responsibility Deliverables from ISAC

Deliverables from Vendor

ISAC Vendor

required

6 Design Verification and approval

√ √ Design changes required

Design, reports and intelligent pdf

7 Proto-model PCB fabrication

√ Fabrications specifications as per clause 6.7.1 to 6.7.7

PID, process details and flow chart

8 Review of fabrication process

√ - Traveler cards

9 Proto-model PCB Delivery √ - As per Clause 7.2.2

10 Proto-model PCB Acceptance

√ √ As per Clause 0

11 Qualification model PCB fabrication

√ Fabrications specifications as per clause 6.7.1 to 6.7.7

12 Qualification model PCB Delivery

√ As per Clause 7.2.2

13 Qualification model PCB acceptance

√ √ As per clause 0

10. General Terms and Conditions

10.1. The indent is for the entire scope as mentioned in Clause 3.0. The offer should include design, analysis of design, proto and qualification model fabrication and testing.

10.2. ISAC prefers to have both proto-model and qualification model PCBs from the same process line.

10.3. ISAC reserves the right to review the progress of work at various stages. ISAC reserves the right to verify & audit at any time, adherence by thecontractor to the workmanship standards and procedures.

10.4. The vendor should facilitate for verification of design at Bangalore. 10.5. The given jobs are to be evaluated and should be completed in mutually

agreed time frame. 10.6. The technical information, drawings and other related documents given by

ISAC in the course of the work should remain the property of Government of India, Department of Space. The given Material / Documents should not be used for any other purpose or be duplicated in any case.

10.7. The vendor shall be binding to the terms and conditions of ISAC Work Order/Agreement.

11. Other Terms and Conditions

11.1. Payment The payment terms may be

100% payment after completion of all activities as per the scope of the work or

100% Performance bank Guarantee in case of milestone based payment as per the milestones mentioned below. Sl No Mile Stone Payment %

1 Layout completion & approval by ISAC 30%

Protomodel

2 PCB fabrication by Vendor & acceptance by ISAC 30%

Qualification Model

3 PCB fabrication by Vendor & acceptance by ISAC 40%

12. Quote Details

12.1. The bid should contain compliance for all specifications and terms and conditions as set by ISAC.

12.2. The vendor should enclose the capability and facility details including major / critical equipments used in HDI fabrication along with technical bid.

12.3. The vendor should make a statement that he has understood the requirements of work and confirms feasibility of taking up the work as per the scope mentioned in Clause 5.0.

12.4. Rates quoted should be valid throughout the completion of the work under the scope of the proposal from the date of placing order.

12.5. The quote should be separate for design, proto-model fabrication and qualification model fabrication and should be as per the quote matrix in Clause 13.0.

12.6. The L1 (lowest quote) will be arrived based on the cumulative cost of all activities as mentioned Clause 12.0

13. Compliance Matrix

Sl. No.

DESCRIPTION SPECIFICATIONS VENDOR COMPLIANCE

1. Availability of CAD tools with Vendor

Cadence allegro / Mentor Expedition / CR5000 / CR8000

2. Analysis Tools availability with Vendor

Hyperlynx

3. Design Verification by ISAC using vendor software

Should be at Bangalore

4. Approval status of fabrication of IPC Type-3 HDI

MIL / NASA / ESA / JAXA

5. HATS acceptance test

Should comply

6. Agreeable to Clause 5 to 12 in the specifications

NOTE: COMPLIANCE TO ALL THE PARAMETERS ARE MANDATORY FOR TECHNICAL ACCEPTANCE OF THE OFFER.

14. Quote Matrix

PCB Name: Qty:

Sl No Description Rate (Rs) Remarks

1 Layout Design

1.1 Component Placement

1.2 Routing

1.3 SI Analysis

1.4 PI Analysis

1.5 Thermal Analysis

1.6 EMI / EMC Simulation

2 Proto Model Fabrication

2.1 PCB Fabrication

3 Qualification Model Fabrication

3.1 PCB Fabrication

15. Annexure 1 –Circuit Details for Design and analysis

Sl No PCB Name Qty Design Input Reference

1. SSR DDRAM PCB 1 Clause 17.1

16. Annexure 2 - Circuit Details for Proto-model Fabrication

Sl No PCB Name Qty

1. SSR DDRAM PCB 1

17. Annexure 3 - Circuit Details for Qualification model Fabrication

Sl No PCB Name Qty

1. SSR DDRAM PCB 1

18. Constraint Manager Inputs

18.1. Design Name: SSR DDRAM PCB Table 3 Layout Design Inputs

Sl No Parameters Input from ISAC

1. Placement Parameters

1.1. Total number of Components to place As per Component List on 12” x 12” size

1.2. Number of SMD pins 4424

1.3. Number of through hole pins 197

1.4. High pin count component like BGAs or CCGAs No BGA / CCGA components

1.5. Preferred components mounting (Top only/Both/Bottom only)

As per Component List

1.6. Placement height restriction requirement As per mech. dwg

1.7. Passive Components allowed only on bottom Side Yes

1.8. Test-Point Assignments for ICT -

2. Routing parameters

2.1. Number of connections 3137

2.2. Power / Ground connections 1288

2.3.

Hand route critical connections

1. Crystal clock to FPGA, 2. SSR Controller FPGA 80

MHz clock to Memory Controller FPGA,

3. DDR lines: Chip select (CS[0-31]#), Clock Enables (CKE[0-

31]), Clock, DQ, DQS, Address, Bank Address, Control lines for DDR (

RAS, CAS, WE, LDM, UDM)

4. LVDS i/o lines ( As per list attached)

2.4. Non-critical hand route connections None

2.5.

Number of differential pairs

DDR clock - 4

LVDS i/o lines – 8 + 1 + 1+8+1+1+1 : Total : 21

Total: 25

2.6. Number of signals to be delay matched LVDS – 21 diff pairs DDR

o clock – 4 diff pairs o Chip select (CS[0-

31]#), o Clock Enables

(CKE[0-31]), o Set 1/2 Addr - 14

lines o Set 1/2 BA – 2 lines o Set 1/2 RAS, CAS,

WE, LDM, UDM – 5 lines

o DDR DQ – 80 lines o DQS - 10 lines

2.7. High Current Signal List and Rating Power planes provided appropriately

2.8. Is Auto routing acceptable Yes, other than for critical signals mentioned above

3. Major interfaces

3.1. Major Interfaces e.g - DDR,Ethernet,Video,Audio,PCI Express etc.

DDR

3.2. Major chipset Part numbers NIL

3.3. Product families such as Virtex-II,Virtex-IV Pro etc. Actel RTAX2000S – CQ352 – 2 numbers.

4. Analysis requirement

4.1. Thermal Analysis Required (table 4)

4.2. SI Analysis Required (Table 5)

4.3. EMI Analysis Required (Table 5)

4.4. Power Integrity Analysis Required (Table 7, 8)

Table 4Thermal analysis Inputs Sl No Parameter Input from ISAC

1 Incoming air Velocity 0 mm/s

Table 5SI analysis Inputs Sl No Parameter Input from ISAC

1. Type of Analysis Required

1.1. Reflection & Cross Talk Required

1.2. EMI Required

1.3. Timing Required

1.4. Type of EMI Analysis Required Near Field radiated emissions analysis – board level

2. RE Standard MIL461

3. Native CAD format of PCB Design Cadence Allegro / Mentor Expedition

4. List of Critical signals As per Table 6

Table 6List of Critical Signals

Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/

Differential Remarks

1 MEMDATA_0 U17 5

U22 5 80 MHz (DQ has switching at Yes Single

One of the 4 receiver pins drives in the reverse direction at a

U27 5 U32 5

Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/


U37 5 both edges of clock)

time. Others are tristated

2 MEMDATA_1 U17 6

U22 7

80 MHz Yes Single Same as above

U27 7 U32 7 U37 7

3 MEMDATA_2 U17 7

U22 8


U27 8 U32 8 U37 8

4 MEMDATA_3 U17 10

U22 10


U27 10 U32 10 U37 10

5 MEMDATA_4 U17 11

U22 11


U27 11 U32 11 U37 11

6 MEMDATA_5 U17 12

U22 13


U27 13 U32 13 U37 13

7 MEMDATA_6 U17 13

U22 14


U27 14 U32 14 U37 14

8 MEMDATA_7 U17 16

U22 16


U27 16 U32 16 U37 16

9 MEMDATA_8 U17 17

U22 63


U27 63 U32 63 U37 63

10 MEMDATA_9 U17 18

U22 65


U27 65 U32 65 U37 65

11 MEMDATA_10 U17 19

U22 66 U27 66

80 MHz Yes Single Same as above U32 66 U37 66


U22 68


Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/


U37 68


U22 69


U27 69 U32 69 U37 69


U22 71


U27 71 U32 71 U37 71


U22 72


U27 72 U32 72 U37 72


U22 74


U27 74 U32 74 U37 74


U21 5


U26 5 U31 5 U36 5


U21 7


U26 7 U31 7 U36 7


U21 8


U26 8 U31 8 U36 8


U21 10


U26 10 U31 10 U36 10


U21 11


U26 11 U31 11 U36 11


U21 13 U26 13 U31 13

80 MHz Yes Single Same as above U36 13


U21 14


U26 14 U31 14 U36 14

Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/



U21 16


U26 16 U31 16 U36 16


U21 63


U26 63 U31 63 U36 63


U21 65


U26 65 U31 65 U36 65


U21 66


U26 66 U31 66 U36 66


U21 68


U26 68 U31 68 U36 68


U21 69


U26 69 U31 69 U36 69


U21 71


U26 71 U31 71 U36 71


U21 72


U26 72 U31 72 U36 72


U21 74


U26 74 U31 74 U36 74


U20 5 U25 5



U20 7


U25 7 U30 7 U35 7

35 MEMDATA_34 U17 58 U20 8 80 MHz Yes Single Same as above

Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/


U25 8 U30 8 U35 8


U20 10


U25 10 U30 10 U35 10


U20 11


U25 11 U30 11 U35 11


U20 13


U25 13 U30 13 U35 13


U20 14


U25 14 U30 14 U35 14


U20 16


U25 16 U30 16 U35 16


U20 63


U25 63 U30 63 U35 63


U20 65


U25 65 U30 65 U35 65


U20 66


U25 66 U30 66 U35 66


U20 68


U25 68 U30 68 U35 68


U20 69


U25 69 U30 69 U35 69

46 MEMDATA_45 U17 73 U20 71 80 MHz Yes Single Same as above

Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/


U25 71 U30 71 U35 71


U20 72


U25 72 U30 72 U35 72


U20 74


U25 74 U30 74 U35 74


U19 5


U24 5 U29 5 U34 5


U19 7


U24 7 U29 7 U34 7


U19 8


U24 8 U29 8 U34 8


U19 10


U24 10 U29 10 U34 10


U19 11


U24 11 U29 11 U34 11


U19 13


U24 13 U29 13 U34 13


U19 14


U24 14 U29 14 U34 14


U19 16


U24 16 U29 16 U34 16

57 MEMDATA_56 U17 94 U19 63

80 MHz Yes Single Same as above U24 63

Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/


U29 63 U34 63


U19 65


U24 65 U29 65 U34 65


U19 66


U24 66 U29 66 U34 66


U19 68


U24 68 U29 68 U34 68

61 MEMDATA_60 U17 100

U19 69


U24 69 U29 69 U34 69

62 MEMDATA_61 U17 101

U19 71


U24 71 U29 71 U34 71

63 MEMDATA_62 U17 104

U19 72


U24 72 U29 72 U34 72

64 MEMDATA_63 U17 105

U19 74


U24 74 U29 74 U34 74

65 MEMDATA_64 U17 106

U18 5


U23 5 U28 5 U33 5

66 MEMDATA_65 U17 107

U18 7


U23 7 U28 7 U33 7

67 MEMDATA_66 U17 110

U18 8


U23 8 U28 8 U33 8

68 MEMDATA_67 U17 111

U18 10


Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/


U33 10

69 MEMDATA_68 U17 112

U18 11


U23 11 U28 11 U33 11

70 MEMDATA_69 U17 113

U18 13


U23 13 U28 13 U33 13

71 MEMDATA_70 U17 118

U18 14


U23 14 U28 14 U33 14

72 MEMDATA_71 U17 119

U18 16


U23 16 U28 16 U33 16

73 MEMDATA_72 U17 146

U18 63


U23 63 U28 63 U33 63

74 MEMDATA_73 U17 147

U18 65


U23 65 U28 65 U33 65

75 MEMDATA_74 U17 152

U18 66


U23 66 U28 66 U33 66

76 MEMDATA_75 U17 153

U18 68


U23 68 U28 68 U33 68

77 MEMDATA_76 U17 154

U18 69


U23 69 U28 69 U33 69

78 MEMDATA_77 U17 155

U18 71


U23 71 U28 71 U33 71

79 MEMDATA_78 U17 158

U18 72


U23 72 U28 72 U33 72

Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/


80 MEMDATA_79 U17 159

U18 74


U23 74 U28 74 U33 74

81 MEMUDQS4 U17 160

U18 60 80 MHz(DQS has Switching at both edges of clock) Yes Single

One of the 4 receiver pins drives in the reverse direction at a time. Others are tristated

U28 60 U33 60

U23 60

82 MEMUDQS3 U17 161

U29 60


U35 60 U19 60 U24 60

83 MEMUDQS2 U17 164

U30 60


U35 60 U20 60 U25 60

84 MEMUDQS1 U17 165

U31 60


U37 60 U21 60 U26 60

85 MEMUDQS0 U17 166

U27 60


U32 60 U37 60 U22 60

86 MEMLDQS4 U17 167

U18 19


U28 19 U33 19 U23 19

87 MEMLDQS3 U17 170

U29 19


U35 19 U19 19 U24 19

88 MEMLDQS2 U17 171

U30 19


U35 19 U20 19 U25 19

89 MEMLDQS1 U17 180

U31 19


U37 19 U21 19 U26 19

90 MEMLDQS0 U17 181

U27 19


Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/


U22 19

91 CK_ROW0 U17 123

U18 54

80 MHz Clock No

Differential (+)

U19 54 U20 54 U21 54 U22 54

92 CK#_ROW0 U17 122

U18 55

80 MHz Clock No

Differential (-)

U19 55 U20 55 U21 55 U22 55

93 CK_ROW1 U17 129

U23 54

80 MHz Clock No

Differential (+)

U24 54 U25 54 U26 54 U27 54

94 CK#_ROW1 U17 128

U23 55

80 MHz Clock No

Differential (-)

U24 55 U25 55 U26 55 U27 55

95 CK_ROW2 U17 137

U28 54

80 MHz Clock No

Differential (+)

U29 54 U30 54 U31 54 U32 54

96 CK#_ROW2 U17 136

U28 55

80 MHz Clock No

Differential (-)

U29 55 U30 55 U31 55 U32 55

97 CK_ROW3 U17 143

U33 54

80 MHz Clock No

Differential (+)

U34 54 U35 54 U36 54 U37 54

98 CK#_ROW3 U17 142

U33 55

80 MHz Clock No

Differential (-)

U34 55 U35 55 U36 55 U37 55

99 CS0# U16 5

U18 27 80 MHz (Does not switch on every clock No Single

U19 27 U20 27 U21 27

Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/


U22 27

but can have 80 MHz equivalent pulse widths)

100 CS1# U16 6

U18 1 80 MHz (Does not switch on every clock but can have 80 MHz equivalent pulse widths) No Single

U19 1 U20 1 U21 1

U22 1

101 CS2# U16 7


U19 2 U20 2 U21 2

U22 2

102 CS3# U16 10


U19 3 U20 3 U21 3

U22 3

103 CS4# U16 11


U19 37 U20 37 U21 37

U22 37

104 CS5# U16 12

U18 38 80 MHz (Does not switch on every clock but can have 80 No Single

U19 38 U20 38 U21 38

U22 38

Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/


MHz equivalent pulse widths)

105 CS6# U16 13


U19 39 U20 39 U21 39

U22 39

106 CS7# U16 16


U19 28 U20 28 U21 28

U22 28

107 CS8# U16 17


U24 27 U25 27 U26 27

U27 27

108 CS9# U16 18


U24 1 U25 1 U26 1

U27 1

109 CS10# U16 19

U23 2 80 MHz (Does not switch on every clock but can have 80 MHz equivalent No Single

U24 2 U25 2 U26 2

U27 2

Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/


pulse widths)

110 CS11# U16 22


U24 3 U25 3 U26 3

U27 3

111 CS12# U16 23


U24 37 U25 37 U26 37

U27 37

112 CS13# U16 24


U24 38 U25 38 U26 38

U27 38

113 CS14# U16 25


U24 39 U25 39 U26 39

U27 39

114 CS15# U16 28


U24 28 U25 28 U26 28

U27 28

Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/


115 CS16# U16 29


U29 27 U30 27 U31 27

U32 27

116 CS17# U16 30


U29 1 U30 1 U31 1

U32 1

117 CS18# U16 31


U29 2 U30 2 U31 2

U32 2

118 CS19# U16 34


U29 3 U30 3 U31 3

U32 3

119 CS20# U16 35


U29 37 U30 37 U31 37

U32 37

120 CS21# U16 36 U28 38 80 MHz

(Does not No Single U29 38

Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/


U30 38 switch on every clock but can have 80 MHz equivalent pulse widths)

U31 38

U32 38

121 CS22# U16 37


U29 39 U30 39 U31 39

U32 39

122 CS23# U16 40


U29 28 U30 28 U31 28

U32 28

123 CS24# U16 41


U34 27 U35 27 U36 27

U37 27

124 CS25# U16 42


U34 1 U35 1 U36 1

U37 1

125 CS26# U16 43


U34 2 U35 2 U36 2

Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/


U37 2


126 CS27# U16 47


U34 3 U35 3 U36 3

U37 3

127 CS28# U16 48


U34 37 U35 37 U36 37

U37 37

128 CS29# U16 49


U34 38 U35 38 U36 38

U37 38

129 CS30# U16 52


U34 39 U35 39 U36 39

U37 39

130 CS31# U16 53

U33 28 U34 28

80 MHz (Does not switch on every clock but can have 80 No Single

U35 28 U36 28

U37 28

Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/



131 CKE0 U16 54


U19 53 U20 53 U21 53

U22 53

132 CKE1 U16 55


U19 40 U20 40 U21 40

U22 40

133 CKE2 U16 58


U19 41 U20 41 U21 41

U22 41

134 CKE3 U16 59


U19 42 U20 42 U21 42

U22 42

135 CKE4 U16 60


U19 76 U20 76 U21 76

U22 76

Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/


pulse widths)

136 CKE5 U16 61


U19 77 U20 77 U21 77

U22 77

137 CKE6 U16 64


U19 78 U20 78 U21 78

U22 78

138 CKE7 U16 65


U19 52 U20 52 U21 52

U22 52

139 CKE8 U16 66


U24 53 U25 53 U26 53

U27 53

140 CKE9 U16 67


U24 40 U25 40 U26 40

U27 40

Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/


141 CKE10 U16 70


U24 41 U25 41 U26 41

U27 41

142 CKE11 U16 71


U24 42 U25 42 U26 42

U27 42

143 CKE12 U16 72


U24 76 U25 76 U26 76

U27 76

144 CKE13 U16 73


U24 77 U25 77 U26 77

U27 77

145 CKE14 U16 76


U24 78 U25 78 U26 78

U27 78

146 CKE15 U16 77 U23 52 80 MHz

(Does not No Single U24 52

Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/


U25 52 switch on every clock but can have 80 MHz equivalent pulse widths)

U26 52

U27 52

147 CKE16 U16 78


U29 53 U30 53 U31 53

U32 53

148 CKE17 U16 79


U29 40 U30 40 U31 40

U32 40

149 CKE18 U16 82


U29 41 U30 41 U31 41

U32 41

150 CKE19 U16 83


U29 42 U30 42 U31 42

U32 42

151 CKE20 U16 84


U29 76 U30 76 U31 76

Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/


U32 76


152 CKE21 U16 85


U29 77 U30 77 U31 77

U32 77

153 CKE22 U16 86


U29 78 U30 78 U31 78

U32 78

154 CKE23 U16 342


U29 52 U30 52 U31 52

U32 52

155 CKE24 U16 341


U34 53 U35 53 U36 53

U37 53

156 CKE25 U16 338

U33 40 80 MHz (Does not switch on every clock but can have 80 No Single

U34 40 U35 40 U36 40

U37 40

Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/



157 CKE26 U16 337


U34 41 U35 41 U36 41

U37 41

158 CKE27 U16 336


U34 42 U35 42 U36 42

U37 42

159 CKE28 U16 335


U34 76 U35 76 U36 76

U37 76

160 CKE29 U16 332


U34 77 U35 77 U36 77

U37 77

161 CKE30 U16 331


U34 78 U35 78 U36 78

U37 78

Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/


pulse widths)

162 CKE31 U16 326


U34 52 U35 52 U36 52

U37 52

163 A0_SET1 U17 182

U18 32

80 MHz (Does not switch on every clock but can have 80 MHz equivalent pulse widths) No Single

U19 32 U20 32 U21 32 U22 32 U23 32 U24 32 U25 32 U26 32 U27 32

164 A1_SET1 U17 183

U18 33


U19 33 U20 33 U21 33 U22 33 U23 33 U24 33 U25 33 U26 33 U27 33

165 A2_SET1 U17 184

U18 33


U19 33 U20 33 U21 33 U22 33 U23 33 U24 33 U25 33 U26 33 U27 33

166 A3_SET1 U17 187

U18 35 80 MHz (Does not switch on every clock but can No Single

U19 35 U20 35 U21 35 U22 35

Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/


U23 35 have 80 MHz equivalent pulse widths)

U24 35 U25 35 U26 35 U27 35

167 A4_SET1 U17 188

U18 44


U19 44 U20 44 U21 44 U22 44 U23 44 U24 44 U25 44 U26 44 U27 44

168 A5_SET1 U17 189

U18 45


U19 45 U20 45 U21 45 U22 45 U23 45 U24 45 U25 45 U26 45 U27 45

169 A6_SET1 U17 190

U18 46


U19 46 U20 46 U21 46 U22 46 U23 46 U24 46 U25 46 U26 46 U27 46

170 A7_SET1 U17 193

U18 47


U19 47 U20 47 U21 47 U22 47 U23 47 U24 47 U25 47 U26 47 U27 47

Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/


171 A8_SET1 U17 194

U18 48


U19 48 U20 48 U21 48 U22 48 U23 48 U24 48 U25 48 U26 48 U27 48

172 A9_SET1 U17 195

U18 49


U19 49 U20 49 U21 49 U22 49 U23 49 U24 49 U25 49 U26 49 U27 49

173 A10_SET1 U17 196

U18 31


U19 31 U20 31 U21 31 U22 31 U23 31 U24 31 U25 31 U26 31 U27 31

174 A11_SET1 U17 199

U18 50


U19 50 U20 50 U21 50 U22 50 U23 50 U24 50 U25 50 U26 50 U27 50

175 A12_SET1 U17 200


U19 51 U20 51 U21 51 U22 51

Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/



U24 51 U25 51 U26 51 U27 51

176 A13_SET1 U17 201

U18 20


U19 20 U20 20 U21 20 U22 20 U23 20 U24 20 U25 20 U26 20 U27 20

177 BA0_SET1 U17 225

U18 29


U19 29 U20 29 U21 29 U22 29 U23 29 U24 29 U25 29 U26 29 U27 29

178 BA1_SET1 U17 226

U18 30


U19 30 U20 30 U21 30 U22 30 U23 30 U24 30 U25 30 U26 30 U27 30

179 RAS#_SET1 U17 232

U18 26


U19 26 U20 26 U21 26 U22 26 U23 26 U24 26 U25 26 U26 26 U27 26

Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/


180 CAS#_SET1 U17 235

U18 25


U19 25 U20 25 U21 25 U22 25 U23 25 U24 25 U25 25 U26 25 U27 25

181 WE#_SET1 U17 231

U18 24


U19 24 U20 24 U21 24 U22 24 U23 24 U24 24 U25 24 U26 24 U27 24

182 LDM_SET1 U17 236

U18 23


U19 23 U20 23 U21 23 U22 23 U23 23 U24 23 U25 23 U26 23 U27 23

183 UDM_SET1 U17 237

U18 56


U19 56 U20 56 U21 56 U22 56 U23 56 U24 56 U25 56 U26 56 U27 56

184 A0_SET2 U17 202


U29 32 U30 32 U31 32 U32 32

Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/



U34 32 U35 32 U36 32 U37 32

185 A1_SET2 U17 205

U28 33


U29 33 U30 33 U31 33 U32 33 U33 33 U34 33 U35 33 U36 33 U37 33

186 A2_SET2 U17 206

U28 34


U29 34 U30 34 U31 34 U32 34 U33 34 U34 34 U35 34 U36 34 U37 34

187 A3_SET2 U17 207

U28 35


U29 35 U30 35 U31 35 U32 35 U33 35 U34 35 U35 35 U36 35 U37 35

188 A4_SET2 U17 208

U28 44


U29 44 U30 44 U31 44 U32 44 U33 44 U34 44 U35 44 U36 44 U37 44

Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/


189 A5_SET2 U17 211

U28 45


U29 45 U30 45 U31 45 U32 45 U33 45 U34 45 U35 45 U36 45 U37 45

190 A6_SET2 U17 212

U28 46


U29 46 U30 46 U31 46 U32 46 U33 46 U34 46 U35 46 U36 46 U37 46

191 A7_SET2 U17 213

U28 47


U29 47 U30 47 U31 47 U32 47 U33 47 U34 47 U35 47 U36 47 U37 47

192 A8_SET2 U17 214

U28 48


U29 48 U30 48 U31 48 U32 48 U33 48 U34 48 U35 48 U36 48 U37 48

193 A9_SET2 U17 217


U29 49 U30 49 U31 49 U32 49

Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/



U34 49 U35 49 U36 49 U37 49

194 A10_SET2 U17 218

U28 31


U29 31 U30 31 U31 31 U32 31 U33 31 U34 31 U35 31 U36 31 U37 31

195 A11_SET2 U17 219

U28 50


U29 50 U30 50 U31 50 U32 50 U33 50 U34 50 U35 50 U36 50 U37 50

196 A12_SET2 U17 220

U28 51


U29 51 U30 51 U31 51 U32 51 U33 51 U34 51 U35 51 U36 51 U37 51

197 A13_SET2 U17 224

U28 20


U29 20 U30 20 U31 20 U32 20 U33 20 U34 20 U35 20 U36 20 U37 20

Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/


198 BA0_SET2 U17 229

U28 29


U29 29 U30 29 U31 29 U32 29 U33 29 U34 29 U35 29 U36 29 U37 29

199 BA1_SET2 U17 230

U28 30


U29 30 U30 30 U31 30 U32 30 U33 30 U34 30 U35 30 U36 30 U37 30

200 RAS#_SET2 U17 241

U28 26


U29 26 U30 26 U31 26 U32 26 U33 26 U34 26 U35 26 U36 26 U37 26

201 CAS#_SET2 U17 242

U28 25


U29 25 U30 25 U31 25 U32 25 U33 25 U34 25 U35 25 U36 25 U37 25

202 WE#_SET2 U17 238


U29 24 U30 24 U31 24 U32 24

Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/



U34 24 U35 24 U36 24 U37 24

203 LDM_SET2 U17 243

U28 23


U29 23 U30 23 U31 23 U32 23 U33 23 U34 23 U35 23 U36 23 U37 23

204 UDM#_SET2 U17 244

U28 56


U29 56 U30 56

U31 56 U32 56 U33 56 U34 56 U35 56 U36 56 U37 56

205 REC_DATA0+IN K1 20 U39 2 20 MHz No Differential (+)

206 REC_DATA0-IN K1 1 U39 1 20 MHz No Differential (+)


208 REC_DATA1-IN K1 21 U39 7 20 MHz No Differential (-)








Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/







221 REC_CLK+IN K1 15 U41 6 20 MHz No Differential (+)

222 REC_CLK-IN K1 33 U41 7 20 MHz No Differential (-)

223 REC_DV+IN K1 32 U41 2

20 MHz (does not switch every clock) No

Differential (+)

224 REC_DV-IN K1 13 U41 1


Differential (-)

225 PB_CLK+IN K1 18 U41 10 20 MHz No Differential (+)

226 PB_CLK-IN K1 36 U41 9 20 MHz No Differential (-)

227 PB_DV+IN K1 35 U41 14


Differential (+)

228 PB_DV-IN K1 16 U14 15


Differential (-)

229 REC_DATA0_IN U39 3 U16 296 20 MHz No Single 230 REC_DATA1_IN U39 5 U16 295 20 MHz No Single 231 REC_DATA2_IN U39 11 U16 290 20 MHz No Single 232 REC_DATA3_IN U39 13 U16 289 20 MHz No Single 233 REC_DATA4_IN U40 3 U16 288 20 MHz No Single 234 REC_DATA5_IN U40 5 U16 287 20 MHz No Single 235 REC_DATA6_IN U40 11 U16 284 20 MHz No Single 236 REC_DATA7_IN U40 13 U16 283 20 MHz No Single 237 REC_CLK_IN U41 5 U16 241 20 MHz No Single

238 REC_DV_IN U41 3 U16 282

20 MHz (does not switch every clock)

No Single

239 PB_CLK_IN U41 11 U16 238 20 MHz No Single

Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/


240 PB_DV_IN U41 13 U16 281

20 MHz (does not switch every clock)

No Single

241 PB_DATA0_OUT U16 278 U42 1

20 MHz No Single

242 PB_DATA1_OUT U16 277 U42 7

20 MHz No Single

243 PB_DATA2_OUT U16 276 U42 9

20 MHz No Single

244 PB_DATA3_OUT U16 275 U42 15

20 MHz No Single

245 PB_DATA4_OUT U16 272 U43 1

20 MHz No Single

246 PB_DATA5_OUT U16 271 U43 7

20 MHz No Single

247 PB_DATA6_OUT U16 270 U43 9

20 MHz No Single

248 PB_DATA7_OUT U16 269 U43 15

20 MHz No Single

249 PB_DV_OUT U16 179 U44 1

20 MHz No Single

250 PB_DATA0+OUT U42 2 K2 2 20 MHz No Differential (+)

251 PB_DATA0-OUT U42 3 K2 1 20 MHz No Differential (-)













Sl.No Signal Name

Driver (pin)

Receiver (pin)

Frequency of

Operation Bi -

Directional

Single-ended/




266 PB_DV+OUT U44 2 K2 18


Differential (+)

267 PB_DV-OUT U44 3 K2 17


Differential (-)

Table 7 De-coupling Analysis Inputs

DC power net Voltage Level

Source pin Devices (loads) connecting the supply net

Maximum current consumption in Amps

2.5 V 2.5 V U2 3

U16 U17 U18 U19 U20 U21 U22

250 mA

250 mA

250 mA

250 mA

250 mA

250 mA

250 mA

U23 U24 U25 U26 U27 U28 U29

250 mA

250 mA

250 mA

250 mA

250 mA

250 mA

250 mA

U30 U31 U32 U33 U34 U35 U36

250 mA

250 mA

250 mA

250 mA

250 mA

250 mA

250 mA

U37

250 mA

Note:

At one instance of time only 5 memories will be active.i.e., U18-U22 or U23-U27 or U28-U32 or U33-37 will be active.Others will consume 60 mA current max. each.

PCB size is 304.8mm x 304.8mm

Table 8 : Power Integrity analysis:

The following are the power nets in the design where power integrity analysis is to be carried out:

SI. No Power Net Source

1 VCC_K K4 P01, P02, P03, P04

2 5V D2 P1

3 3.3 V U1 P3

4 2.5 V U2 P3

5 2.5V_ST U4 P3

6 1.5 V U3 P3

7 VREF U45 P63

8 VTT Driven by U45; Filtered Output at L1

COMPONENTS FOR WHICH IBIS MODELS NEED TO BE GENERATED

Type/Value Package Function

CD4093B 14 PIN FP SCHMITT QUAD NAND

CD4050B 16 PIN FP CMOS HEX BUFFER

SN55LVDS32W-CFP16 16 PIN FP QUAD LVDS RECEIVER



*****